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12 Commits

Author SHA1 Message Date
Ian Lance Taylor 8d67dc3077 Add support for mips16 (16 bit MIPS implementation): 
* mips16-opc.c: New file.
	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
	(mips16_reg_names): New static array.
	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
	after seeing a 16 bit symbol.
	(print_insn_little_mips): Likewise.
	(print_insn_mips16): New static function.
	(print_mips16_insn_arg): New static function.
	* mips-opc.c: Add jalx instruction.
	* Makefile.in (mips16-opc.o): New target.
	* configure.in: Use mips16-opc.o for bfd_mips_arch.
	* configure: Rebuild.
 1996-11-26 15:59:18 +00:00
Ian Lance Taylor f27ab33041 * mips-opc.c: Add r4650 mul instruction. 1995-02-16 22:35:36 +00:00
Ian Lance Taylor 470feacfab * mips-opc.c: Add uld and usd macros for unaligned double load and 
store.
 1995-02-15 20:47:31 +00:00
Ian Lance Taylor 27faaa41e6 * mips-opc.c: Add dli as a synonym for li. 1994-12-20 16:27:45 +00:00
Ian Lance Taylor 8490907307 * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. 
PR 5632
 1994-09-14 21:53:14 +00:00
Ian Lance Taylor 942a4965b7 * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions 
which store a value into memory.
PR 5433.
 1994-09-06 15:42:11 +00:00
Ian Lance Taylor 9978cd4dc9 * mips-opc.c: Correct lwu opcode value (book had it wrong). 1993-10-05 21:49:04 +00:00
Ian Lance Taylor 547998d2c8 * mips-opc.c: Change div machine instruction to be z,s,t rather 
than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
 1993-09-02 17:14:10 +00:00
Ian Lance Taylor a9c686adf5 * mips-opc.c: Move div machine instruction after macro forms. 
Change d,s,t form to d,v,t.  Likewise for divu, ddiv and ddivu.
	This is for compatibility with the MIPS assembler, which only
	generates the simple machine instruction when an explicit
	destination of $0 is used.
 1993-09-02 14:42:31 +00:00
Ian Lance Taylor a5ba0d3f48 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set 
WR_31 hazard for bal, bgezal, bltzal.
 1993-08-27 14:55:22 +00:00
Ian Lance Taylor 2bef2d3e57 * mips-opc.c: Added r6000 and r4000 instructions and macros. 
Changed hazard information to distinguish between memory load
	delays and coprocessor load delays.
 1993-08-20 15:40:51 +00:00
Ian Lance Taylor 45b1470513 * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. 1993-08-18 19:40:37 +00:00