Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend. This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.
As an example assembling this program:
$ cat test.s
.text
foo:
b bar
b baz
.set bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s
produces this binary code:
$ objdump -dr test-o32.o test-n32.o
test-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
test-n32.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*+0x1230
4: 00000000 nop
8: 10000000 b c <foo+0xc>
8: R_MIPS_PC16 baz-0x4
c: 00000000 nop
$
where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word. In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.
Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise. This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.
Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function. The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.
With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:
$ objdump -dr fixed-o32.o
fixed-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000048c b 1234 <bar>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
$
Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used. Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
bfd/
* reloc.c (bfd_perform_relocation): Try the `howto' handler
first with relocations against absolute symbols.
(bfd_install_relocation): Likewise.
gas/
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/branch-absolute.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `branch-absolute-addend' and
`micromips-branch-absolute-addend', referred indirectly only.
Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c95 ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e ("Add in a JALRC
alias and fix the NAL instruction."). As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.
The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':
$ cat test.s
.text
foo:
nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o
nal.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo> 04100000 0x4100000
...
$
This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.
Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code. Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people. This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code. Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.
Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.
Add a suitable test case to the GAS test suite. While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
annotation from the "nal" entry and reorder it beyond "bltzal".
gas/
* testsuite/gas/mips/nal-1.d: New test.
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
* testsuite/gas/mips/nal-2.d: New test.
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
* testsuite/gas/mips/nal.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch adds support for the LDTXA instructions, along with the
corresponding ASIs. Tests for GAS are included.
opcodes/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (ldtxa): New macro.
(sparc_opcodes): Use the macro defined above to add entries for
the LDTXA instructions.
(asi_table): Add the ASI_TWINX_* asis used in the LDTXA
instruction.
gas/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/ldtxa.s: New file.
* testsuite/gas/sparc/ldtxa.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
gas/ChangeLog:
2016-07-05 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is
no longer needed.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Complement:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), and remove a call to
`install_insn' from `append_insn', which as from that change has become
redundant. This is because such a call, to place an instruction's bit
pattern in output, is already made from `move_insn', called from
`add_relaxed_insn' or `add_fixed_insn' as appropriate, either of which
now always is and has to be made from `append_insn' before the repeated
call to `install_insn' is made. Previously the place where this second
invocation is made was the only one where the output stream was updated,
although the update was made inline rather than with a function call.
Remove the repeated call then, to reclaim some performance.
gas/
* config/tc-mips.c (append_insn): Remove extraneous
`install_insn' call.
A missing 'r' (or wrong 'e') register prefix needs to be complained
about if the template allows for a 64-bit register, not a 32-bit one.
I assume this was a copy-and-paste type of mistake
(from check_long_reg()).
Move `branch-misc-2' tests for non locally-defined-global symbols into
separate files. These tests have been introduced with:
commit 6f171daac9
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Thu Dec 12 04:40:22 2002 +0000
<https://sourceware.org/ml/binutils/2002-11/msg00631.html>, ("mips:
branches to external labels are broken"), and:
commit d17b874b6c
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Wed Mar 12 23:07:22 2003 +0000
<https://sourceware.org/ml/binutils/2003-03/msg00136.html>, ("On
resolving the MIPS gas branch reloc issue"), while the test case served
a different purpose. With the original intent of the test case brought
back with:
commit bad36eacda
Author: Daniel Jacobowitz <drow@false.org>
Date: Wed Nov 23 14:04:18 2005 +0000
<https://sourceware.org/ml/binutils/2005-11/msg00324.html>,
("R_MIPS_PC16, again"), these stand in the way for linker testing.
gas/
* testsuite/gas/mips/branch-misc-2.s: Move non
locally-defined-global symbol tests...
* testsuite/gas/mips/branch-misc-5.s: ... to this new test.
* testsuite/gas/mips/branch-misc-2.d: Update accordingly.
* testsuite/gas/mips/branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/branch-misc-5.d: New test.
* testsuite/gas/mips/branch-misc-5pic.d: New test.
* testsuite/gas/mips/branch-misc-5-64.d: New test.
* testsuite/gas/mips/branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test.
* testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: New test.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
Feature flag handling was not perfect, +nofp16 disabled fp
instructions too.
New feature flag macros were added to check features with multiple
bits set (matters for FP_F16 and SIMD_F16 opcode feature tests).
The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should
use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE
now checks all feature bits.
The aarch64_features table now contains the dependencies as
a separate field (so when the feature is enabled all dependencies
are enabled and when it is disabled everything that depends on it
is disabled).
Note that armv8-a+foo+nofoo is not equivalent to armv8-a if
+foo turns on dependent features that nofoo does not turn off.
gas/
* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
require field.
(aarch64_features): Initialize require fields.
(aarch64_parse_features): Handle dependencies.
(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
* testsuite/gas/aarch64/illegal-nofp16.s: New.
* testsuite/gas/aarch64/illegal-nofp16.l: New.
* testsuite/gas/aarch64/illegal-nofp16.d: New.
include/
* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
(AARCH64_CPU_HAS_ANY_FEATURES): New.
(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
(AARCH64_OPCODE_HAS_FEATURE): Remove.
binutuils* prdbg.c (pr_enum_type): Use a buffer big enough to hold an
extremely large decimal value.
(pr_range_type): Likewise.
(pr_array_type): Likewise.
(pr_struct_field): Likewise.
(pr_class_baseclass): Likewise.
(pr_class_method_variant): Likewise.
(pr_tag_type): Likewise.
(pr_int_constant): Likewise.
(pr_typed_constant): Likewise.
(pr_variable): Likewise.
(pr_function_parameter): Likewise.
(pr_start_block): Likewise.
(pr_lineno): Likewise.
(pr_end_block): Likewise.
(tg_enum_type): Likewise.
(tg_int_constant): Likewise.
(tg_typed_constant): Likewise.
(tg_start_block): Likewise.
gas * macro.c (macro_expand_body): Use a buffer big enough to hold an
extremely large integer.
While address overrides are ignored in 64-bit mode (and hence shouldn't
really result in an error, but upon v1 converting this to a warning I
was told otherwise), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt. (The
added test case at once also checks that bndc{l,n,u} won't accept
16-bit register operands.)
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
Fix an assertion failure like:
test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.
triggered by assembling MIPS16 code like:
hello:
addiu $4, $4, 4
jr $31
with the generation of a listing file enabled, e.g.:
$ as -mips16 -O2 -aln=test.lst
The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag. It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.
This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.
This effectively complements:
commit 464ab0e55a
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Mon Aug 6 20:33:00 2012 +0000
<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.
The assertion itself was introduced with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.
gas/
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
case MIPS16 handling.
* testsuite/gas/mips/branch-swap-3.d: New test.
* testsuite/gas/mips/branch-swap-4.d: New test.
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
* testsuite/gas/mips/branch-swap-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify non-MIPS16 branch swapping by copying the MIPS16 variant, which
sets the new position for the current instruction first and reduces the
calculation of the new position of the previous instruction. Also refer
to previous instruction's frag and position via `delay' for consistency.
Reintroduce an explanatory comment, updated, previously removed with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]").
gas/
* config/tc-mips.c (append_insn): Simplify non-MIPS16 branch
swapping sequence.
Correct a regression from commit 85024cd8bc ("Run write_object_file
after errors") causing unsuccessful assembly, which may be due to any
reason, such as supplying a valid source like this:
.text
.byte 0
.err
to terminate with an assertion failure like:
test.s: Assembler messages:
test.s:3: Error: .err encountered
../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg
../as-new: Please report this bug.
on targets whose default text section alignment is above 0, typically
RISC machines.
This is due to an attempt to set last text section's frag alignment to
0, requested from `subsegs_finish_section' where `frag_align_code
(alignment, 0)' is called with `alignment' set to 0 rather than the
section alignment if `had_errors' has returned true. The call to
`subsegs_finish_section' is made from `subsegs_finish' from
`write_object_file' at unsuccessful completion, which previously wasn't
made.
Always set last section's frag alignment from the section alignment
then, forcing no section padding instead if completing unsuccessfully,
so that in that case alignment padding is still suppressed from any
listing generated, fixing assertion failures for these targets:
alpha-linuxecoff -FAIL: all pr20312
arm-aout -FAIL: all pr20312
mips-freebsd -FAIL: all pr20312
mips-img-linux -FAIL: all pr20312
mips-linux -FAIL: all pr20312
mips-mti-linux -FAIL: all pr20312
mips-netbsd -FAIL: all pr20312
mips-sgi-irix5 -FAIL: all pr20312
mips-sgi-irix6 -FAIL: all pr20312
mips-vxworks -FAIL: all pr20312
mips64-freebsd -FAIL: all pr20312
mips64-img-linux -FAIL: all pr20312
mips64-linux -FAIL: all pr20312
mips64-mti-linux -FAIL: all pr20312
mips64-openbsd -FAIL: all pr20312
mips64el-freebsd -FAIL: all pr20312
mips64el-img-linux -FAIL: all pr20312
mips64el-linux -FAIL: all pr20312
mips64el-mti-linux -FAIL: all pr20312
mips64el-openbsd -FAIL: all pr20312
mipsel-freebsd -FAIL: all pr20312
mipsel-img-linux -FAIL: all pr20312
mipsel-linux -FAIL: all pr20312
mipsel-mti-linux -FAIL: all pr20312
mipsel-netbsd -FAIL: all pr20312
mipsel-vxworks -FAIL: all pr20312
mipsisa32-linux -FAIL: all pr20312
mipsisa32el-linux -FAIL: all pr20312
mipsisa64-linux -FAIL: all pr20312
mipsisa64el-linux -FAIL: all pr20312
sh-pe -FAIL: all pr20312
sparc-aout -FAIL: all pr20312
gas/
PR gas/20312
* write.c (subsegs_finish_section): Force no section padding to
alignment on failed assembly, always set last frag's alignment
from section.
* testsuite/gas/all/pr20312.l: New list test.
* testsuite/gas/all/pr20312.s: New test source.
* testsuite/gas/all/gas.exp: Run the new test
GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a
when assembling NEON instructions. The patch corrects this, making
-march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions
introduced with ARMv8.1-A.
include/
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
of enabled FPU features.
gas/
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/arm/armv8_2+rdma.d: New.
--enable-compressed-debug-sections=gas added to binutils 2.26. Make it
default for Linux/x86 targets in 2.27.
* NEWS: Mention --enable-compressed-debug-sections=gas is the
default for Linux/x86 targets.
* configure.tgt (ac_default_compressed_debug_sections): Default
to yes for Linux/x86 targets.
Remove an internal diagnostic regression introduced with the inclusion of
"libbfd.h" from write.c, added with:
commit e7ff5c732e
Author: Alan Modra <amodra@gmail.com>
Date: Fri Feb 16 03:40:17 2007 +0000
That change made "libbfd.h" override the `abort' definition provided by
"as.h" earlier on, making the message produced by any calls reached from
write.c, which is a part of the GAS proper, look like they came from
BFD, e.g.:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg
../as-new: Please report this bug.
vs:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
.../gas/testsuite/gas/elf/type.s: Internal error, aborting at .../gas/write.c:602 in size_seg
Please report this bug.
With the removal of "libbfd.h" restore the latter message format.
gas/
* write.c: Remove "libbfd.h" inclusion.
Complement commit a43942db49 ("LD/ELF: Unify STB_GNU_UNIQUE handling")
and use `supports_gnu_unique' with the `unique_symbol' and `type' tests,
fixing failures like:
.../binutils/testsuite/binutils-all/unique.s: Assembler messages:
.../binutils/testsuite/binutils-all/unique.s:2: Error: symbol type "gnu_unique_object" is supported only by GNU targets
ERROR: .../binutils/testsuite/binutils-all/unique.s: assembly failed
UNRESOLVED: ar unique symbol in archive
.../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o
Executing on host: .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o (timeout = 300)
.../binutils/ar: tmpdir/unique.o: No such file or directory
FAIL: ar unique symbol in archive
and:
.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg
../as-new: Please report this bug.
.../gas/testsuite/../../binutils/readelf -s dump.o | grep "1 *\[FIONTCU\]" > dump.out
Executing on host: sh -c {.../gas/testsuite/../../binutils/readelf -s dump.o >readelf.out 2>gas.stderr} /dev/null (timeout = 300)
readelf: Error: dump.o: Failed to read file's magic number
FAIL: elf type list
on MIPS/FreeBSD targets:
mips-freebsd -FAIL: ar unique symbol in archive
mips-freebsd -FAIL: elf type list
mips64-freebsd -FAIL: ar unique symbol in archive
mips64-freebsd -FAIL: elf type list
mips64el-freebsd -FAIL: ar unique symbol in archive
mips64el-freebsd -FAIL: elf type list
mipsel-freebsd -FAIL: ar unique symbol in archive
mipsel-freebsd -FAIL: elf type list
binutils/
* testsuite/binutils-all/ar.exp: Use `supports_gnu_unique' with
the `unique_symbol' test.
gas/
* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
`type' test.
aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked. This meant large invalid indices could be silently
truncated to smaller valid indices.
The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index. I went for the latter for two
reasons:
- Doing the range checking in operand_general_constraint_met_p
seems structurally cleaner than doing it while parsing.
- The bitfields didn't really buy us anything. The imm field
of the union is already 128 bits, so we can use a full int64_t
index without growing the structure.
The patch also adds missing range checks for the elements in a register
list index.
include/
* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
opcodes/
* aarch64-opc.c (operand_general_constraint_met_p): Check the
range of ldst_elemlist operands.
(print_register_list): Use PRIi64 to print the index.
(aarch64_print_operand): Likewise.
gas/
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
cfi_add_CFA_def_cfa to generate default CFA with offset
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
PR gas/20247
* as.h (do_not_pad_sections_to_alignment): New global variable.
* as.c (show_usage): Add --no-pad-sections.
(parse_args): Likewise.
* write.c (size_seg): Skip padding the end of the section if
requested from the command line.
(SUB_SEGMENT_ALIGN): Likewise.
* doc/as.texinfo: Document the new option.
* NEWS: Mention the new feature.
* testsuite/gas/elf/section11.s: New test.
* testsuite/gas/elf/section11.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
gas/ChangeLog:
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal
element in relax_table.
its only called with an argument of 0, so we might as well remove the code
supporting other values.
gas/ChangeLog:
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_set_default_include): remove argument
and simplify accordingly.
(tic54x_include): Adjust.
(tic54x_mlib): Likewise.
Correct a MIPS16 relocation handling regression in GAS introduced with:
commit 177b4a6ad0
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Mon Mar 18 18:56:18 2002 +0000
discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>,
which removed a preparatory call to `mips16_extended_frag' previously
made from `md_estimate_size_before_relax'. As a result the function is
never called with its `sec' parameter non-NULL and consequently all the
unsupported relocation checks within are dead and never trigger, causing
any unhandled relocations to silently resolve to 0. Unfortunately there
was no sufficient test suite coverage back then to catch this.
Remove all dead code then, and all the associated comments. Update the
remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass
the relocation section as the `sec' parameter and use it to mark frags
which require an external relocation, as extended. Finally handle any
outstanding MIPS16 relocations in `md_convert_frag' and report an error
since we don't support any except with percent operators.
gas/
* config/tc-mips.c (append_insn): Use any `O_symbol' expression
unchanged with relaxed MIPS16 instructions.
(mips16_extended_frag): Adjust accordingly. Return 1 right
away if a relocation will be required for the symbol requested.
Remove dead first relaxation pass code.
(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
(md_convert_frag): Adjust symbol value calculation. Raise an
error if a relocation is required for the symbol requested.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
add error output.
* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
* testsuite/gas/mips/mips16-branch-absolute.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Maciej W. Rozycki
Jose E. Marchesi
Claudiu Zissulescu
Jan Beulich
Szabolcs Nagy
Nick Clifton
Tristan Gingold
Andrew Burgess
Matthew Fortune
Matthew Wahab
H.J. Lu
Alan Modra
Richard Sandiford
Vineet Gupta
Trevor Saunders