* config/tc-i386.c (md_assemble): Swap template arguments to
CONSISTENT_REGISTER_MATCH macro in reverse direction test.
This macro is currently symmetric, so passing them the wrong
way didn't cause any problem, but may if the macro is changed
in the future.
After copying template to i.tm, use i.tm. rather than t-> to
access fields, and make t a const*
Move i.tm.operand_types[] swap to immediately after the copy.
(md_convert_frag): Delete.
(TC_FIX_TYPE): New fields wl,cl,user_value;
* config/tc-dvp.c (insert_mpg_marker): New argument ignore.
All callers updated.
(insert_unpack_marker): New function.
(insert_file): New argument insert_marker_arg. All callers updated.
(gif_user_value): New static local.
(vif_data_start,vif_data_end): New static locals.
(mpgloc_sym,unpackloc_sym): New static locals.
(cur_varlen_frag,cur_varlen_insn,cur_varlen_value): Delete.
(cur_opcode,cur_operand): New static locals.
(endmpg_caller): New enum.
(md_pseudo_table): Pass ENDMPG_USER to s_endmpg.
(md_begin): Initialize mpgloc_sym, unpackloc_sym.
(dvp_fixup): New members user_value,wl,cl;
(assemble_vif): Rewrite.
(assemble_gif): Tweak name of data start label.
(assemble_one_insn): Allow special parser to punt and call the
normal expression parser. Set cur_opcode,cur_operand for md_operand.
(md_operand): Handle '*' value for mpgloc,unpackloc.
(md_estimate_size_before_relax): New function.
(dvp_relax_frag,md_convert_frag): New functions.
(md_pcrel_from_section): Handle end data label for variable length
vif insns.
(md_apply_fix3): Handle count field for variable length vif insns.
Handle address field for mpg,unpack.
(eval_expr): Initialize user_value,wl,cl fields of the fixup.
(cur_vif_insn_length): Delete.
(vif_length_value): New function.
(install_vif_length): Don't perform logical->physical conversion here.
(s_enddirect,s_endmpg,s_endunpack): Rewrite.
* config/tc-i386.h (LinearAddress): Define.
* config/tc-i386.c (md_assemble): If LinearAddress is set for the
instruction, don't use a default segment.
"name.completer" where only the name is actually in the opcode
table. Allow various operands for base register in load/store
instructions. Handle various new argument characters for the
cop2/vu0 co-processor.
* config/tc-dvp.c (compute_nloop,check_nloop): New functions.
(gif_insn_frag_loc): New static global.
(assemble_gif): Record frag and location frag of insn.
(md_apply_fix3): Validate user specified nloop if we couldn't do
it earlier.
(s_endgif): Queue fixup to install nloop if we can't compute it here.
(insert_file): New args insert_marker, size. All callers updated.
(assemble_vif): Rewrite varlen insn handling.
(assemble_vu): Call insert_mpg_marker when 256th insn reached.
(s_enddirect,s_endunpack): Rename arg to internal_p.
* gas/dvp/vif-1.[sd]: Add more tests.
* gas/dvp/gif{packed,reglist,image}-1.[sd]: New testcases.
* gas/dvp/dvp.exp: Run them. Pass -I${srcdir}/${subdir} to gas.
Recognize -GN and -relax.
(md_begin): Initialize gp size from -G switch.
(alpha_force_relocation): Always force if -relax.
(alpha_align): Take a new argument that will specify when to
emit an R_ALPHA_ALIGN relocation (though we don't do that now).
Change all callers. Emit nop alignment padding as nop+unop pair.
