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8 Commits

Author SHA1 Message Date
Andrew Cagney 4e0bf4c4d0 2002-11-21 Andrew Cagney <ac131313@redhat.com> 
* filter.c: Re-indent.
	* filter.h, filter_host.h, gen-engine.c, gen-engine.h: Ditto.
	* gen-icache.c, gen-icache.h, gen-idecode.c: Ditto.
	* gen-idecode.h, gen-itable.c, gen-itable.h: Ditto.
	* gen-model.c, gen-model.h, gen-semantics.c: Ditto.
	* gen-semantics.h, gen-support.c, gen-support.h: Ditto.
	* gen.c, gen.h, igen.c, igen.h, ld-cache.c, ld-cache.h: Ditto.
	* ld-decode.c, ld-decode.h, ld-insn.c, ld-insn.h, lf.c: Ditto.
	* lf.h, misc.c, misc.h, table.c, table.h: Ditto.
 2002-11-22 04:20:49 +00:00
Andrew Cagney feaee4bdbb 2002-11-21 Andrew Cagney <ac131313@redhat.com> 
* Makefile.in: Update copyright.  IGEN contributed to the FSF.
        * filter.c, filter.h, filter_host.c, filter_host.h: Ditto.
        * gen-engine.c, gen-engine.h, gen-icache.c, gen-icache.h: Ditto.
        * gen-idecode.c, gen-idecode.h, gen-itable.c: Ditto.
        * gen-itable.h, gen-model.c, gen-model.h, gen-semantics.c: Ditto.
        * gen-semantics.h, gen-support.c, gen-support.h, gen.c: Ditto.
        * gen.h, igen.c, igen.h, ld-cache.c, ld-cache.h: Ditto.
        * ld-decode.c, ld-decode.h, ld-insn.c, ld-insn.h, lf.c: Ditto.
        * lf.h, misc.c, misc.h, table.c, table.h: Ditto.
 2002-11-22 04:09:40 +00:00
Stan Shebs c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs 071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Andrew Cagney 346a3d6c11 Add support for instruction word conditionals of the form `XXX!YYY' 
and XXX=YYY'.  See mn10300 for examples.
 1998-04-14 00:00:15 +00:00
Andrew Cagney 278bda4050 Cleanup INLINE support for simulators using common framework. 
Make IGEN responsible for co-ordinating inlining of generated files.
By default, aclocal.m4 disabled all inlining.
 1998-04-04 12:33:11 +00:00
Andrew Cagney 8782bfcfc4 Add -Wnodiscard option so that warning about discarded instructions 
can be suppressed.
Allow ``<insn-spec> { <nmemonic> | <model> }'' in instruction file.
 1997-10-09 08:35:33 +00:00
Andrew Cagney 2f2e6c5d5b Extend xor-endian and per-cpu support in core module. 
Allow negated test when watching value within core.
 1997-05-27 06:48:20 +00:00