This reverts part of the earlier version.in change. It moves
version.in back to the gdb directory. This works around the CVS bug
we've found.
gdb
* Makefile.in (version.c): Use version.in, not
common/version.in.
* common/create-version.sh: Likewise.
* common/version.in: Move...
* version.in: ...here.
gdb/doc
* Makefile.in (version.subst): Use version.in, not
common/version.in.
* gdbint.texinfo (Versions and Branches, Releasing GDB):
Likewise.
gdb/gdbserver
* Makefile.in (version.c): Use version.in, not
common/version.in.
sim/common
* Make-common.in (version.c): Use version.in, not
common/version.in.
* create-version.sh: Likewise.
sim/ppc:
* Make-common.in (version.c): Use version.in, not
common/version.in.
This change is required now that gdb/version.in has been moved to
gdb/common/version.in and now that the date needs to be fetched
from bfd/version.h.
sim/common/ChangeLog:
* create-version.sh: New script. Adapted from
gdb/commong/create-version.sh.
* Make-common.in (version.c): Update rule dependencies,
and re-implement using create-version.sh.
sim/ppc/ChangeLog:
* Makefile.in (srccom): New variable.
(version.c): Update rule dependencies, and re-implement using
sim/common/create-version.sh.
The SEARCH insn is an oddball when it comes to parallel usage. It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this). Add a note for now in case we get around to it.
For many of the 32bit dsp shift related insns, we were just ignoring the HLs
field. The hardware does not though and will reject the insn if it's set
incorrectly. Update the sim to match.
Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them. Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns. On the
hardware, these are proper invalid insns, and the table catches that.
The main body of the "all insn" test is executed once per tested insn, and
we test millions of insns here. Any shrinkage we can do in this loop will
speed things up nicely (since it's multiplied per tested insn).
To that end, simplify the end-of-table test into one less insn, and omit
the SSYNC when we build for the sim. When we build to run on the hardware,
this insn matters, but the sim doesn't have write store buffers in the chip
that might get in the way (memory writes are atomic).
We wrote a test case that tries every single 32bit opcode on the hardware
and compared it to the sim. There were a bunch of places in the sim where
we weren't strict enough (requiring certain parts of the opcode be set) so
we were treating a lot of invalid opcodes as valid ones. This sprinkles
out a lot additional checks in the dsp32alu class.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Since these insns run in usermode, there should be no need to setup
RET[ENI] to safe values. They won't be dereferenced, and any insn
that returns via them are valid only in supervisor mode. Since this
is in the main exception code path, saving any insn at all is good
as it gets multiplied quickly (as in O(n^2) times).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Since many people don't have a Blackfin toolchain available, only try to
regenerate the header file when in maintainer mode. This file rarely changes,
and when it does, we commit the generated output, so there's almost never a
need to run directly on an end system.
I noticed the sim code is using an old implementation of the maintainer logic.
I cut it over to the new macro (like gdb has been doing). In practice, it
makes no difference currently as nothing in the sim tree uses it, but I have a
follow up commit for the Blackfin tree that needs it.
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com>
This patch adds simulator support for handling the armv7 instructions
'movw (immediate)' and 'movt'.
Compiler frequently use these instructions to load the 32bit addresses of
global variables, string pointers etc. into the general registers.
In absence of support of these instructions:
1. GDB run simulator fails to print even simple "hello world" string
on console.
2. Loading of global variable addresses into the registers fail causing
arithmetic operation failures.
Patch has been regression tested for arm-none-eabi (-march=armv7-a).
These sims have optional support for the dv-sockser model, so do not make
them hard failures. The Makefile made it seem like they didn't actually
support things dynamically, but a further code dive into the source and
the Makefile shows that things work out.
There's no need to put the majority of the logic into the 3rd arg of the
AC_ARG_ENABLE. Coupled with the lack of indentation, it makes it hard to
follow, error prone to update, and duplicates code (with the 4th arg).
So pull the logic out of the 3rd arg and outside of the AC_ARG_ENABLE
macro. This allows us to gut the 4th arg entirely, merge with the code
that followed the macro, and fix bugs related to the new dv-sockser in
the process.
Hopefully building the various sims with the default sim-hardware
settings, as well as with explicit --{dis,en}able-sim-hardware flags,
should all just work now.
* configure.ac: Fail if dv-sockser.o not available.
Error when --disable-sim-hardware is specified.
* tconfig.in: Conditionalize use of dv_sockser_install.
* configure: Regenerated.
* config.in: Regenerated.
* configure.ac: Address use of dv-sockser.o.
* tconfig.in: Conditionalize use of dv_sockser_install.
* configure: Regenerated.
* config.in: Regenerated.
* acinclude.m4: Add SIM_DV_SOCKSER_O which is empty on hosts
which do not support dv-sockser.o. Add always as option to
first argument to SIM_AC_OPTION_HARDWARE. Fail if hardware
is always required to be enabled by simulator.
(v850_bins): New function.
* simops.h: Add prototypes fir v850_rotl and v850_bins.
* v850-dc: Add entries for V850e3v5.
* v850.igen: Add support for v850e3v5.
(ld.dw, st.dw, rotl, bins): New patterns.
architecture type. Add support for bfd_mach_v850e2 and
bfd_mach_v850e2v3 machine numbers.
* v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
(cmpf.d): Correct order of operands.
(cmpf.s): Likewise.
(trncf.dul): New pattern.
(trncf.duw): New pattern.
(trncf.sul): New pattern.
(trncf.suw): New pattern.
* v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
