Commit Graph

11 Commits

Author SHA1 Message Date
Jose E. Marchesi d8740be159 cpu,gas,opcodes: remove no longer needed workaround from the BPF port
cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
	* bpf.opc (bpf_print_insn): Do not set endian_code here.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
	bpf_cgen_cpu_open.
	(md_assemble): Remove no longer needed hack.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-06-04 16:17:42 +02:00
Jose E. Marchesi b3db6d07be opcodes: support insn endianness in cgen_cpu_open
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument
for @arch@_cgen_cpu_open.  This is useful for architectures in
which the endianness of the instruction words is not the same
than the endianness used for data.

An accompanying patch has been sent to the CGEN mailing list that
adds support for this argument on the CGEN side [1].  Its been
already pre-approved [2], and will be applied simultaneously with
this binutils series.

[1] https://sourceware.org/pipermail/cgen/2020q2/002733.html
[2] https://sourceware.org/pipermail/cgen/2020q2/002737.html

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* opcode/cgen.h (enum cgen_cpu_open_arg): New value
	CGEN_CPU_OPEN_INSN_ENDIAN.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
	(print_insn_): Handle instruction endian.
	* bpf-dis.c: Regenerate.
	* bpf-desc.c: Regenerate.
	* epiphany-dis.c: Likewise.
	* epiphany-desc.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-desc.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-desc.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-desc.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-desc.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-desc.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-desc.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-desc.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-desc.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-desc.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-desc.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-desc.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-desc.c: Likewise.

binutils/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* objdump.c (disassemble_data): Set disasm_info.endian_code to
        disasm_info.endian after the latter is initialized to the
        endianness reported by BFD.
2020-06-04 16:17:42 +02:00
Alan Modra 3c3d03769e Regen opcodes/bpf-desc.c
The last regen used an old version of cgen.

	* bpf-desc.c: Regenerate.
2020-06-01 19:53:05 +09:30
Jose E. Marchesi 78c1c35437 cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes
This patch adds semantic RTL descriptions to the eBPF instructions
defined in cpu/bpf.cpu.  It also contains a couple of minor
improvements.

Tested in bpf-unknown-none targets.
No regressions.

cpu/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
	(define-alu-insn-mov): Likewise.
	(daib): Likewise.
	(define-alu-instructions): Likewise.
	(define-endian-insn): Likewise.
	(define-lddw): Likewise.
	(dlabs): Likewise.
	(dlind): Likewise.
	(dxli): Likewise.
	(dxsi): Likewise.
	(dsti): Likewise.
	(define-ldstx-insns): Likewise.
	(define-st-insns): Likewise.
	(define-cond-jump-insn): Likewise.
	(dcji): Likewise.
	(define-condjump-insns): Likewise.
	(define-call-insn): Likewise.
	(ja): Likewise.
	("exit"): Likewise.
	(define-atomic-insns): Likewise.
	(sem-exchange-and-add): New macro.
	* bpf.cpu ("brkpt"): New instruction.
	(bpfbf): Set word-bitsize to 32 and insn-endian big.
	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
	(h-pc): Expand definition.
	* bpf.opc (bpf_print_insn): Set endian_code to BIG.

opcodes/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-05-28 21:52:31 +02:00
Alan Modra d96bf37ba8 Replace "if (x) free (x)" with "free (x)", opcodes
cpu/
	* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
	"if (x) free (x)" with "free (x)".
opcodes/
	* arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
	* sparc-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* xtensa-dis.c: Likewise.
	* bpf-desc.c: Regenerate.
	* epiphany-desc.c: Regenerate.
	* fr30-desc.c: Regenerate.
	* frv-desc.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* iq2000-desc.c: Regenerate.
	* lm32-desc.c: Regenerate.
	* m32c-desc.c: Regenerate.
	* m32r-desc.c: Regenerate.
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mt-desc.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xstormy16-desc.c: Regenerate.
2020-05-21 10:45:33 +09:30
David Faust c54a9b5669 cpu,gas,opcodes: support for eBPF JMP32 instruction class
Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.
2020-04-16 09:52:57 +02:00
Alan Modra b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Jose E. Marchesi 231097b03a cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 15:35:43 +02:00
Jose E. Marchesi 3719fd55b6 cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.

cpu/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlabs): New pmacro.
	(dlind): Likewise.

opcodes/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

gas/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
	register as an argument.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
	explicit arguments to ldabs and ldind instructions.
2019-07-15 16:00:28 +02:00
Jose E. Marchesi 92434a14b9 cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument.  Instead, they put the loaded value in %r0, implicitly.

This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.

Tested in a x86-64 host.

cpu/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
	explicit 'dst' argument.

opcodes/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.

gas/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
	ldabs and ldind instructions.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 14:45:31 +02:00
Jose E. Marchesi 79472b4532 opcodes: add support for eBPF
This patch adds support for the Linux kernel eBPF architecture to the
opcodes.  The port is based on CGEN.

opcodes/ChangeLog:

2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
	* configure: Regenerated.
	* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
	and cpu/bpf.opc.
	(HFILES): Add bpf-desc.h and bpf-opc.h.
	(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
	bpf-ibld.c and bpf-opc.c.
	(BPF_DEPS): Define.
	* Makefile.in: Regenerated.
	* disassemble.c (ARCH_bpf): Define.
	(disassembler): Add case for bfd_arch_bpf.
	(disassemble_init_for_target): Likewise.
	(enum epbf_isa_attr): Define.
	* disassemble.h: extern print_insn_bpf.
	* bpf-asm.c: Generated.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-ibld.c: Likewise.
	* bpf-dis.c: Likewise.
	* bpf-desc.h: Likewise.
	* bpf-desc.c: Likewise.
2019-05-23 19:33:56 +02:00