This fix keeps the section with the highest alignment when folding sections with ICF.
PR gold/17704
* icf.cc (match_sections): Add new parameter section_addraligns.
Check section alignment and keep the section with the strictest
alignment.
(find_identical_sections): New local variable section_addraligns.
Store each section's alignment.
* testsuite/pr17704a_test.s: New file.
* testsuite/Makefile.am (pr17704a_test): New test.
* testsuite/Makefile.in: Regenerate.
When we see an unversioned symbol reference in a shared library, followed
by a default definition of the symbol in another shared library, we were
treating them as separate symbols. That should only happen when both are
definitions.
gold/
PR gold/20238
* symtab.cc (Symbol_table::define_default_version): Check that
unversioned symbol is defined.
This patch adds a little more debug output, and replaces two variables
with one, tracking current max group size by group_size_ rather than
by has14_.
* powerpc.cc (class Stub_control): Delete stub14_group_size_
and has14_. Add group_size_.
(Stub_control::can_add_to_stub_group): Adjust to suit. Print
debug info when switching to adding sections before stubs.
This patch rewrites the rather obscure can_add_to_stub_group, fixing
a problem with the handling of sections containing conditional
external branches. When a section group contains any such section,
the group size needs to be limited to a much smaller size than groups
with only non-conditional external branches.
PR 20523
* powerpc.cc (class Stub_control): Add has14_. Comment owner_.
(Stub_control::can_add_to_stub_group): Correct grouping of
sections containing 14-bit external branches. When returning
false, set state_ to reflect the fact that we have one section
for the next group. Rewrite most of function for clarity.
Add and expand comments.
(Target_powerpc::do_relax): Print stub group size retry in hex.
gold/ChangeLog
2016-08-26 Han Shen <shenhan@google.com>
* powerpc.cc (Stub_table::min_size_threshold_): New member to
limit size.
(Stub_table::set_min_size_threshold): New member function.
(Stub_table::set_address_and_size): Add code to only allow size
increase.
(Target_powerpc::do_relax): Add code to record last size.
Build the test objects with the in-tree assembler. Also fix some cascading
error messages caused by not resetting the skip_call_tls_get_addr_ flag
after printing the error.
gold/
* i386.cc (Target_i386): Reset skip_call_tls_get_addr_ after printing
error message.
* testsuite/Makefile.am (pr20216a): Add missing dependencies.
(pr20308a): Add -Bgcctestdir/ to compile rules.
* testsuite/Makefile.in: Regenerate.
With some versions of gas, the call to tls_get_addr uses a GOTPCREL
relocation instead of a GOTPCRELX relocation. We should allow for that
when skip_call_tls_get_addr_ is true. We should also build the test
objects with the in-tree assembler.
This patch also fixes some cascading error messages caused by not
resetting the skip_call_tls_get_addr_ flag after printing the error.
gold/
PR gold/20216
* x86_64.cc (Target_x86_64::Relocate::relocate): Add check for
R_X86_64_GOTPCREL. Reset skip_call_tls_get_addr_ after printing
error message.
* testsuite/Makefile.am (pr20216_gd.o): Add -Bgcctestdir/.
(pr20216_ld.o): Likewise.
* testsuite/Makefile.in: Regenerate.
2016-08-10 James Clarke <jrtc27@jrtc27.com>
gold/
PR gold/20443
* symtab.cc (Symbol_table::add_from_relobj): Handle NULL symbols,
which will be present for STT_SPARC_REGISTER.
(Symbol_table::add_from_pluginobj): Likewise.
(Symbol_table::add_from_dynobj): Likewise.
(Symbol_table::add_from_incrobj): Removed dead code.
The fall-through in Target_sparc::Relocate::relocate for
R_SPARC_GOTDATA_OP_LOX10 is currently R_SPARC_GOT13, but should
clearly be R_SPARC_GOT10. GCC has been seen to emit a sethi/xor
rather than a sethi/or sequence to load a 32-bit immediate, but
if R_SPARC_GOT13 is used then bits 10-12 get zeroed out as both
the sethi and xor immediates contain them.
gold/
PR gold/20442
* sparc.cc (Target_sparc::Relocate::relocate): R_SPARC_GOTDATA_OP_LOX10
should fall back on R_SPARC_GOT10, not R_SPARC_GOT13.
This CL implemented the following relocs for AArch64 target.
- R_AARCH64_MOVW_UABS_G*
- R_AARCH64_MOVW_SABS_G* relocations
gold/ChangeLog
2016-07-26 Igor Kudrin <ikudrin@accesssoftek.com>
* aarch64-reloc-property.cc (Rvalue_bit_select_impl): New class.
(rvalue_bit_select): Use Rvalue_bit_select_impl.
* aarch64-reloc.def (MOVW_UABS_G0, MOVW_UABS_G0_NC,
MOVW_UABS_G1,
MOVW_UABS_G1_NC, MOVW_UABS_G2, MOVW_UABS_G2_NC, MOVW_UABS_G3,
MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2): New relocations.
* aarch64.cc (Target_aarch64::Scan::local): Add cases for new
MOVW_UABS_* and MOVW_SABS_* relocations.
(Target_aarch64::Scan::global): Likewise.
(Target_aarch64::Relocate::relocate): Add cases and handlings
for new MOVW_UABS_* and MOVW_SABS_* relocations.
* testsuite/Makefile.am (aarch64_relocs): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/aarch64_globals.s: New test source file.
* testsuite/aarch64_relocs.s: Likewise.
* testsuite/aarch64_relocs.sh: New test script.
With GCC 6 when not using -static-libstdc++, the operator delete(void*)
function is defined in the shared C++ support library, rather than in
the main program. The test script is too aggressive in checking for
this symbol's presence among the exported symbols. This patch removes
the check for that symbol.
gold/
PR gold/20310
* testsuite/dynamic_list.sh: Remove check for _ZdlPv.
There are extensions to 386 psABI:
https://groups.google.com/forum/#!topic/ia32-abi/awsRSvJOJfs
to call tls_get_addr via GOT:
call *___tls_get_addr@GOT(%reg)
where EBX register isn't required as GOT base.
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, 7-byte lea instruction before call
instruction is replaced by 6-byte one to make room for indirect call.
For local dynamic model, we simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction
patterns. For local dynamic model to local exec model transition,
we generate a 6-byte lea instruction as nop, instead of a 1-byte nop
plus a 4-byte lea instruction.
PR gold/20308
* i386.cc (Target_i386::Relocate::relocate): Allow
R_386_GOT32X relocation against ___tls_get_addr.
(Target_i386::Relocate::tls_gd_to_ie): Support indirect
call to __tls_get_addr.
(Target_i386::Relocate::tls_gd_to_le): Likewise.
(Target_i386::Relocate::tls_ld_to_le): Likewise.
* testsuite/Makefile.am (check_PROGRAMS): Add pr20308a_test,
pr20308b_test, pr20308c_test, pr20308d_test, pr20308e_test.
(pr20308a_test_SOURCES): New.
(pr20308a_test_DEPENDENCIES): Likewise.
(pr20308a_test_CFLAGS): Likewise.
(pr20308a_test_LDFLAGS): Likewise.
(pr20308a_test_LDADD): Likewise.
(pr20308b_test_SOURCES): Likewise.
(pr20308b_test_DEPENDENCIES): Likewise.
(pr20308b_test_CFLAGS): Likewise.
(pr20308b_test_LDFLAGS): Likewise.
(pr20308b_test_LDADD): Likewise.
(pr20308c_test_SOURCES): Likewise.
(pr20308c_test_DEPENDENCIES): Likewise.
(pr20308c_test_CFLAGS): Likewise.
(pr20308c_test_LDFLAGS): Likewise.
(pr20308c_test_LDADD): Likewise.
(pr20308d_test_SOURCES): Likewise.
(pr20308d_test_DEPENDENCIES): Likewise.
(pr20308d_test_CFLAGS): Likewise.
(pr20308d_test_LDFLAGS): Likewise.
(pr20308d_test_LDADD): Likewise.
(pr20308e_test_SOURCES): Likewise.
(pr20308e_test_DEPENDENCIES): Likewise.
(pr20308e_test_CFLAGS): Likewise.
(pr20308e_test_LDFLAGS): Likewise.
(pr20308e_test_LDADD): Likewise.
(pr20308a.so): Likewise.
(pr20308b.so): Likewise.
(pr20308_gd.o): Likewise.
(pr20308_ld.o): Likewise.
(MOSTLYCLEANFILES): Add pr20308a.so pr20308b.so.
* testsuite/Makefile.in: Regenerated.
* testsuite/pr20308_def.c: New file.
* testsuite/pr20308_gd.S: Likewise.
* testsuite/pr20308_ld.S: Likewise.
* testsuite/pr20308_main.c: Likewise.
There are extensions to x86-64 psABI:
https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI
to call tls_get_addr via GOT:
call *__tls_get_addr@GOTPCREL(%rip)
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, one 0x66 prefix before call instruction is
removed to make room for indirect call. For local dynamic model, we
simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction
patterns. For local dynamic model to local exec model transition, we
generate 4 0x66 prefixes, instead of 3, before mov instruction in 64-bit
and generate a 5-byte nop, instead of 4-byte, before mov instruction in
32-bit.
PR gold/20216
* configure.ac (DEFAULT_TARGET_X86_64_OR_X32): New
AM_CONDITIONAL.
* configure: Regenerated.
* x86_64.cc (Target_x86_64<size>::Relocate::relocate): Allow
R_X86_64_GOTPCRELX relocation against __tls_get_addr.
(Target_x86_64<size>::Relocate::tls_gd_to_ie): Support indirect
call to __tls_get_addr.
(Target_x86_64<size>::Relocate::tls_gd_to_le): Likewise.
(Target_x86_64<size>::Relocate::tls_ld_to_le): Likewise.
* testsuite/Makefile.am (check_PROGRAMS): Add pr20216a_test,
pr20216b_test, pr20216c_test, pr20216d_test, pr20216e_test.
(pr20216a_test_SOURCES): New.
(pr20216a_test_DEPENDENCIES): Likewise.
(pr20216a_test_CFLAGS): Likewise.
(pr20216a_test_LDFLAGS): Likewise.
(pr20216a_test_LDADD): Likewise.
(pr20216b_test_SOURCES): Likewise.
(pr20216b_test_DEPENDENCIES): Likewise.
(pr20216b_test_CFLAGS): Likewise.
(pr20216b_test_LDFLAGS): Likewise.
(pr20216b_test_LDADD): Likewise.
(pr20216c_test_SOURCES): Likewise.
(pr20216c_test_DEPENDENCIES): Likewise.
(pr20216c_test_CFLAGS): Likewise.
(pr20216c_test_LDFLAGS): Likewise.
(pr20216c_test_LDADD): Likewise.
(pr20216d_test_SOURCES): Likewise.
(pr20216d_test_DEPENDENCIES): Likewise.
(pr20216d_test_CFLAGS): Likewise.
(pr20216d_test_LDFLAGS): Likewise.
(pr20216d_test_LDADD): Likewise.
(pr20216e_test_SOURCES): Likewise.
(pr20216e_test_DEPENDENCIES): Likewise.
(pr20216e_test_CFLAGS): Likewise.
(pr20216e_test_LDFLAGS): Likewise.
(pr20216e_test_LDADD): Likewise.
(pr20216a.so): Likewise.
(pr20216b.so): Likewise.
(pr20216_gd.o): Likewise.
(pr20216_ld.o): Likewise.
(MOSTLYCLEANFILES): Add pr20216a.so pr20216b.so.
* testsuite/Makefile.in: Regenerated.
* testsuite/pr20216_def.c: New file.
* testsuite/pr20216_gd.S: Likewise.
* testsuite/pr20216_ld.S: Likewise.
* testsuite/pr20216_main.c: Likewise.
PowerPC gcc aligns char arrays to a word which results in the test
failing since it expects a char alignment. As the test already uses
gcc attributes to assign variables to sections, we may as well use an
attribute to align too.
* testsuite/plugin_layout_with_alignment.c: Explicitly align all
variables.
A target like powerpc64 that is PIC by default doesn't need copy relocs.
* testsuite/Makefile.am (copy_test_protected): Disable for powerpc.
* testsuite/Makefile.in: Regenerate.
According to "ELF for the ARM(r) 64-bit Architecture (AArch64)",
this relocation can be used "to prevent removal of sections that
might otherwise appear to be unused."
gold/
* aarch64-reloc.def (NONE): New relocation.
* aarch64.cc (Target_aarch64::Scan::local): Handle R_AARCH64_NONE.
(Target_aarch64::Scan::global): Likewise.
* testsuite/Makefile.am (aarch64_reloc_none): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/aarch64_reloc_none.s: New test source file.
* testsuite/aarch64_reloc_none.sh: New test script.
Please see patch discussion:
https://www.sourceware.org/ml/binutils/2016-05/msg00322.html
2016-06-28 Sriraman Tallam <tmsriram@google.com>
* x86_64.cc (Lazy_view): New class.
(can_convert_mov_to_lea): Templatize function. Make the function
check for appropriate relocation types and use the view parameter
to get section contents.
(can_convert_callq_to_direct): New function.
(Target_x86_64<size>::Scan::global): Refactor.
(Target_x86_64<size>::Relocate::relocate): Refactor. Change any indirect
call via GOT that can be converted.
* testsuite/Makefile.am (x86_64_indirect_call_to_direct.sh): New test.
* testsuite/Makefile.in: Regenerate.
* testsuite/x86_64_indirect_call_to_direct1.s: New file.
* testsuite/x86_64_indirect_jump_to_direct1.s: New file.
bfd * elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Don't convert
R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.
gold * sparc.cc (Target_sparc::Scan::local): Don't convert R_SPARC_32
to R_SPARC_RELATIVE if class is ELFCLASS64.
(Target_sparc::Scan::global): Likewise.
ld * testsuite/ld-elf/symbolic-func.r: Allow non-zero offsets from
.text.
The fix for PR 15370 did not correctly check all patterns in a group,
but instead threw all unassigned sections into the group. This patch
fixes that.
2016-06-23 Cary Coutant <ccoutant@gmail.com>
Igor Kudrin <ikudrin@accesssoftek.com>
gold/
PR gold/15370
* script-sections.cc
(Output_section_element_input::set_section_addresses): Keep bin_count
separate from input_pattern_count.
* testsuite/script_test_12.t: Add another section .x4.
* testsuite/script_test_12i.t: Likewise.
* testsuite/script_test_12a.c: Likewise.
* testsuite/script_test_12b.c: Likewise.
Add a configure option --enable-relro to decide whether -z relro should
be enabled by default. Default to yes.
PR ld/20283
* NEWS: Mention --enable-relro.
* configure.ac: Add --enable-relro.
(DEFAULT_LD_Z_RELRO): New. Set by --enable-relro and default
to 1.
* config.in: Regenerated.
* configure: Likewise.
* options.h (General_options::relro): Default to
DEFAULT_LD_Z_RELRO.
If there is no PLT in output, return 0 for first_plt_entry_offset and
plt_entry_size.
PR gold/20245
* i386.cc (Target_i386::first_plt_entry_offset): Return 0 if
plt_ is NULL.
(Target_i386::plt_entry_size): Likewise.
(Target_x86_64<size>::first_plt_entry_offset): Likewise.
(Target_x86_64<size>::plt_entry_size): Likewise.
Includes DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags and
__RLD_MAP symbol.
2016-06-20 Vladimir Radosavljevic <Vladimir.Radosavljevic@imgtec.com>
elfcpp/
* elfcpp.h (DT_MIPS_RLD_MAP_REL): New enum constant.
gold/
* mips.cc (Target_mips::Target_mips): Initialize rld_map_.
(Target_mips::rld_map_): New data member.
(Target_mips::do_finalize_sections): Add support for
DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags,
.rld_map section, and __RLD_MAP symbol.
(Target_mips::do_dynamic_tag_custom_value): Add support for
DT_MIPS_RLD_MAP_REL dynamic tag.
* output.cc (Output_data_dynamic::get_entry_offset): New method
definition.
* output.h (Output_data_dynamic::get_entry_offset): New method
declaration.
elfcpp/
* mips.h (R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16, R_MIPS_PCLO16): New enums for
Mips32r6 and Mips64r6 relocations.
(r6_isa): New function.
gold/
* mips.cc (relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(hi16_reloc): Add support for R_MIPS_PCHI16 relocation.
(is_matching_lo16_reloc): Likewise.
(lo16_reloc): Add support for R_MIPS_PCLO16 relocation.
(Mips_output_data_plt::plt_entry_r6): New static data member for
R6 PLT entry.
(Target_mips::is_output_r6): New method.
(Target_mips::Mips_mach): Add new enum constants.
(Mips_relocate_functions::Status): Likewise.
(Mips_relocate_functions::pchi16_relocs): New static data member.
(Mips_relocate_functions::relpc21): New method.
(Mips_relocate_functions::relpc26): Likewise.
(Mips_relocate_functions::relpc18): Likewise.
(Mips_relocate_functions::relpc19): Likewise.
(Mips_relocate_functions::relpchi16): Likewise.
(Mips_relocate_functions::do_relpchi16): Likewise.
(Mips_relocate_functions::relpclo16): Likewise.
(Mips_output_data_plt::do_write): Add support for Mips r6 plt
entry.
(Target_mips::mips_32bit_flags): Add E_MIPS_ARCH_32R6 support.
(Target_mips::elf_mips_mach): Add E_MIPS_ARCH_32R6 and
E_MIPS_ARCH_64R6 support.
(Target_mips::update_abiflags_isa): Likewise.
(mips_get_size_for_reloc): Add support for relocs: R_MIPS_PCHI16,
R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3 and
R_MIPS_PC19_S2.
(Target_mips::Scan::local): Add support for relocs: R_MIPS_PCHI16
and R_MIPS_PCLO16.
(Target_mips::Scan::global): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(Target_mips::Relocate::relocate): Call functions for resolving
Mips32r6 and Mips64r6 relocations, and print error message for
STATUS_PCREL_UNALIGNED.
(Target_mips::Scan::get_reference_flags): Add support for relocs:
R_MIPS_PCHI16, R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2,
R_MIPS_PC18_S3 and R_MIPS_PC19_S2.
(Target_mips::elf_mips_mach_name): Add E_MIPS_ARCH_32R6 and
E_MIPS_ARCH_64R6 support.
The .got.plt section must be placed right after the .got section.
Otherwise, GOT offset will be wrong.
PR gold/20246
* testsuite/script_test_2.t: Add .got.plt after .got.
gold/
* mips.cc (Mips_relobj::Mips_relobj): Initialize
has_reginfo_section_.
(Mips_relobj::has_reginfo_section_): New data member.
(Mips_relobj::has_reginfo_section): New method.
(class Mips_output_section_reginfo): Change base class to
Output_section_data, and set masks of the output .reginfo section
in constructor.
(Mips_output_section_reginfo::as_mips_output_section_reginfo):
Remove.
(Mips_output_section_reginfo::set_masks): Likewise.
(Mips_output_section_reginfo::set_final_data_size): Likewise.
(Mips_output_section_reginfo::do_print_to_mapfile): New method.
(Target_mips::do_make_output_section): Remove.
(Mips_relobj::do_read_symbols): Set has_reginfo_section_ to true
if the object contains a .reginfo section.
(Target_mips::do_finalize_sections): Create a .reginfo output
section if needed.
Loïc Yhuel