Complement commit 7361da2c95 ("Add support for MIPS R6.") and fix
internal errors like:
foo.s: Assembler messages:
foo.s: Internal error!
Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028.
Please report this bug.
triggered by resolved R6 PC-relative relocations in sources containing
R6 code fragments wrapped into ISA override blocks embedded within code
otherwise assembled for an older ISA.
gas/
* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
<BFD_RELOC_LO16_PCREL>: New switch cases.
(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
Move switch cases along `BFD_RELOC_MIPS_JMP'.
<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
the resolved case.
* testsuite/gas/mips/pcrel-reloc-4.d: New test.
* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-5.d: New test.
* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Use the module level ISA setting rather than the last ISA selected with
a `.set' directive in the source file in determination as to whether to
keep PC-relative relocations and then with the original symbol referred,
for the purpose of R6 linker relaxation.
This is so that with e.g. code like this:
b foo
.set mips32r2
...
it's the command line options or any `.module' directive that decides
how to encode any relocation for `foo' rather than the presence of `.set
mips32r2'.
gas/
* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
rather than `mips_opts' for the R6 ISA check.
(mips_fix_adjustable): Likewise.
* testsuite/gas/mips/pcrel-reloc-1.d: New test.
* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-2.d: New test.
* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-3.d: New test.
* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20
reloc.
gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
instruction size.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mn10200.c (md_assemble): Likewise.
* config/tc-moxie.c (md_assemble): Likewise.
* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
exception targets. Add alpha, hppa, microblaze and rl78 to list
of exceptions.
(forward): Add microblaze to list of exceptions.
(fwdexp): Add alpha to list of exceptions.
(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
(do_930509a): Alpha sort list of exception targets. Add h8300 and
mn10200 to list of exceptions.
(align2): Expect to fail for nds32.
(cond): Add alpha and rl78 to list of exceptions.
* testsuite/gas/all/none.d: Skip for ft32 and hppa.
* testsuite/gas/all/string.d: Skip for tic4x.
* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
target does not support ELF.
* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH
tests for sh-pe and sh-rtemscoff targets.
* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
list of exceptions.
(type): Run the noifunc version for alpha-freebsd and visium.
* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
mn10200 or moxie targets.
* testsuite/gas/ft32/insn.d: Update expected disassembly.
* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
targets.
* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
mcore and rx targets.
* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
rl78 and vax.
(purge): Expect to fail on the ns32k and vax.
* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
* testsuite/gas/nds32/ls.d: Likewise.
* testsuite/gas/nds32/sys-reg.d: Likewise.
* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
* testsuite/gas/pe/section-align-3.d: Likewise.
* testsuite/gas/pe/section-exclude.d: Likewise.
* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
data has been seen.
* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
for variations in whitespace.
* testsuite/gas/tilepro/t_constants.d: Pass once all the required
data has been seen.
* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
Installs a 32-bit value without generating warnings on 64-bit
hosts.
Use the new macro to replace the .word directives.
opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
constants to match expected behaviour.
(nds32_parse_opcode): Likewise. Also for whitespace.
The extract function used for some arc_s instructions was not
implemented, and instead always returned 0. Fixed in this commit.
opcodes/ChangeLog:
* arc-opc.c (extract_rhv1): Extract value from insn.
gas/ChangeLog:
* testsuite/gas/arc/add_s.d: New file.
* testsuite/gas/arc/add_s.s: New file.
This commit adds the ldbit instruction for the NPS-400. The ldbit
instruction uses the same encoding as the ld instruction, but sets
the ZZ field to 11 (which is a reserved setting), and sets the AA
field to 1 or 2 for the x2 and x4 flags respectively.
With the exception of ldbit, this commit adds implementations of
all DPI instructions for the NPS-400. These instructions are:
- hash / hash.p[0-3]
- tr
- utf8
- e4by
- addf
Revert an inadvertent change to make RELA JALR relocations
section-relative on MIPS R6 targets made with commit 7361da2c95 ("Add
support for MIPS R6."). There is no need to make this a special case
and the comment introduced with the said change clearly indicates this
was not intended.
gas/
* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
JALR relocations on R6.
* testsuite/gas/mips/jal-svr4pic-local.d: New test.
* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
etc * texi2pod.pl: Escape curly braces, whilst searching for keyword
strong.
gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets
that are not supported.
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
constant.
* config/tc-cr16.c (check_range): Likewise.
* config/tc-nios2.c (nios2_check_overflow): Likewise.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.
gas/
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
(arm_ext_ras): Renamed from arm_ext_v8_2.
(insns): Update for arm_ext_v8_2 renaming.
(arm_extensions): Add "ras".
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
* testsuite/gas/arm/armv8-a+ras.d: New.
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
options.
include/
* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
entries.
(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
opcodes/
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
ARM_EXT_RAS in relevant entries.
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.
gas/
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
0,b,limm to the rflt instruction.
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit
AVX512 instruction. We must match another AVX512 bit.
PR gas/20140
* config/tc-i386.c (cpu_flags_match): Require another match
for AVX512VL.
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
x86-64-avx512vl-1 and x86-64-avx512vl-2.
* testsuite/gas/i386/avx512vl-1.l: New file.
* testsuite/gas/i386/avx512vl-1.s: Likewise.
* testsuite/gas/i386/avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
PR target/2006764
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
instruction if supported by the currently selected fpu variant.
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
Do not convert jump relocs against local MIPS16 or microMIPS symbols to
refer to a section symbol instead even on RELA targets, as it makes it
impossible for the linker to make a JAL to JALX conversion based on ISA
symbol annotation, breaking regular and compressed MIPS interlinking.
gas/
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
jump relocations against MIPS16 or microMIPS symbols on RELA
targets.
* testsuite/gas/mips/jalx-local.d: New test.
* testsuite/gas/mips/jalx-local-n32.d: New test.
* testsuite/gas/mips/jalx-local-n64.d: New test.
* testsuite/gas/mips/jalx-local.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-local.d: New test.
* testsuite/ld-mips-elf/jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in
"movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax".
PR gas/19600
* config/tc-i386.c (md_apply_fix): Preserve addend for
BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
* testsuite/gas/i386/addend.d: New file.
* testsuite/gas/i386/addend.s: Likewise.
* testsuite/gas/i386/x86-64-addend.d: Likewise.
* testsuite/gas/i386/x86-64-addend.s: Likewise.
* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
* testsuite/gas/i386/reloc32.d: Updated.
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation
with microMIPS J/JAL/JALS instructions, however unlike the latters its
encoded immediate argument is unusually shifted left by 2 rather than 1
in calculating the value used for the operation requested.
We already handle this exception in `mips_elf_calculate_relocation' in
LD, in a scenario where JALX is produced as a result of relaxing JAL for
the purpose of making a cross-mode jump. We also get it right in the
disassembler in `decode_micromips_operand'.
What we don't correctly do however is processing microMIPS JALX produced
by GAS from an assembly source, where a non-zero constant argument or a
symbol reference with a non-zero in-place addend has been used. In this
case the same calculation is made as for microMIPS J/JAL/JALS, causing
the wrong encoding to be produced by GAS on making an object file, and
then again by LD in the final link. The latter in particular causes the
calculation, where the addend fits in the relocatable field, to produce
different final addresses for the same source code depending on whether
REL or RELA relocations are used.
Correct these issues by special-casing microMIPS JALX in the places that
have been previously missed.
bfd/
* elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for
microMIPS JALX.
gas/
* config/tc-mips.c (append_insn): Correct the encoding of a
constant argument for microMIPS JALX.
(tc_gen_reloc): Correct the encoding of an in-place addend for
microMIPS JALX.
* testsuite/gas/mips/jalx-addend.d: New test.
* testsuite/gas/mips/jalx-addend-n32.d: New test.
* testsuite/gas/mips/jalx-addend-n64.d: New test.
* testsuite/gas/mips/jalx-imm.d: New test.
* testsuite/gas/mips/jalx-imm-n32.d: New test.
* testsuite/gas/mips/jalx-imm-n64.d: New test.
* testsuite/gas/mips/jalx-addend.s: New test source.
* testsuite/gas/mips/jalx-imm.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-addend.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
The opcode array iterator mechanism can, in some situations, result in
reading memory outside of the opcode array. When using the
iterator-next mechanism to find the next possible arc_opcode, if we find
an opcode where the name field is NULL, or the name does not match, then
the cached opcode pointer is not set to NULL. The result is that
another call to iterator-next will again increment the opcode
pointer (which might now point outside the opcode array) and attempt to
access the name field of this undefined opcode.
Fixed in this commit by clearing the cached opcode pointer.
I've added a test case, which currently shows the bug, however, this
will only expose this bug while the opcode used (dsp_fp_cmp) is the last
opcode in the table.
gas/ChangeLog:
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
cached opcode to NULL when we reach a non-matching opcode.
* testsuite/gas/arc/asm-errors-2.d: New file.
* testsuite/gas/arc/asm-errors-2.err: New file.
* testsuite/gas/arc/asm-errors-2.s: New file.
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.
This change checks that we don't access outside the limits of the
operand array.
gas/ChangeLog:
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
Commit b84bf58a accidentally extended the range of allowed negative
numbers.
* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
allowed negative range.
* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
* testsuite/gas/ppc/power9.d: Update.
PR target/20068
* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
to the pool uses O_constant.
* testsuite/gas/arm/pr20068.s: New test.
* testsuite/gas/arm/pr20068.d: Test driver.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
shared with a non M profile architecture.
(do_rn): New function.
(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
than arm_ext_v8m.
(v7m_psrs): Add ARMv8-M security extensions new special registers.
(insns): Add ARMv8-M Security Extensions instructions.
(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
arm_ext_v8m_m to decide the profile and the Thumb ISA.
* testsuite/gas/arm/archv8m-cmse.s: New file.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/any-cmse.d: Likewise.
* testsuite/gas/arm/any-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
include/
* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
for the high core bits.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
Mainline Security Extensions instructions.
(thumb_opcodes): Add entries for narrow ARMv8-M Security
Extensions instructions.
(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
instructions.
(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
special registers.
opcodes/ChangeLog:
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
gas/ChangeLog:
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
Correct a regression introduced with commit 919731affb ("Add MIPS
.module directive") causing code like:
.set mips3
dli $2, 0x9000000080000000
to fail assembly with the following error message produced:
Error: number (0x9000000080000000) larger than 32 bits
if built with `mips3' selected as the global ISA (e.g. `-march=mips3').
This is because a `.set' directive doing an ISA override does not lift
the ABI restriction on register sizes if the ISA remains unchanged.
Previously the directive always set register sizes from the ISA chosen,
which is what some code expects. Restore the old semantics then.
gas/
* config/tc-mips.c (code_option_type): New enum.
(parse_code_option): Return status indicating option type.
(s_mipsset): Update `parse_code_option' call site accordingly.
Always set register sizes from the ISA with ISA overrides.
(s_module): Update `parse_code_option' call site.
* testsuite/gas/mips/isa-override-1.d: New test.
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
* testsuite/gas/mips/isa-override-2.l: New list test.
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/isa-override-1.s: New test source.
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
* testsuite/gas/mips/isa-override-2.s: New test source.
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.
This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.
gas/
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
Maciej W. Rozycki
Graham Markall
Jose E. Marchesi
Nick Clifton
Andrew Burgess
Matthew Wahab
Peter Bergner
H.J. Lu
Chua Zheng Leong
Alan Modra
Thomas Preud'homme
Matthew Fortune
Alexander Fomin
Claudiu Zissulescu
Pitchumani Sivanupandi