Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
Just like other VCVT*{X,Y} templates do, and to allow the programmer
flexibility (might be relevant in particular when heavily macro-izing
code), the two templates should also have Broadcast set, just like their
X/Y-suffix-less counterparts. This in turn requires them to also have
* Dword set on their memory operands, to cover the logic added to
i386gen by 4a1b91eabb ("x86: Expand Broadcast to 3 bits"),
* RegXMM/RegYMM set on their source operands, to satisfy broadcast
sizing logic in gas itself.
Otherwise ATTSyntax templates wouldn't need such operand size attributes.
While extending the test cases, also add Intel syntax broadcast forms
without explicit size specifiers.
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.
This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16 #does not disable mve.
vadd.i32 q0, q1, q2
This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.
gas/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
include/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
(ARM_ANY): Redefine to not include any MVE bits.
(ARM_FEATURE_ALL): Removed.
opcodes/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
any architecture.
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).
For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
tic4x uses a number of static variables for tables that are generated
depending on the current machine (tic4x vs. tic3x). However, it is
possible to change the machine from one invocation of print_insn_tic4x
to the next. This patch throws away the old state if that happens,
and uses a relatively small known size array of register names rather
than a malloc'd table.
* tic4x-dis.c (tic4x_version): Make unsigned long.
(optab, optab_special, registernames): New file scope vars.
(tic4x_print_register): Set up registernames rather than
malloc'd registertable.
(tic4x_disassemble): Delete optable and optable_special. Use
optab and optab_special instead. Throw away old optab,
optab_special and registernames when info->mach changes.
PR 25377
gas * config/tc-z80.c: Add support for half precision, single
precision and double precision floating point values.
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
* doc/as.texi: Add new z80 command line options.
* doc/c-z80.texi: Document new z80 command line options.
* testsuite/gas/z80/ez80_pref_dis.s: New test.
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
* testsuite/gas/z80/z80.exp: Run the new test.
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
* testsuite/gas/z80/fp_zeda32.d: Likewise.
* testsuite/gas/z80/strings.d: Update expected output.
opcodes * z80-dis.c (suffix): Use .db instruction to generate double
prefix.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
(detected_jumps): New variables.
(usage): Add the new jump visualization options.
(option_values): Add new option value.
(long_options): Add the new option.
(jump_info_new, jump_info_free): New functions.
(jump_info_min_address, jump_info_max_address): Likewise.
(jump_info_end_address, jump_info_is_start_address): Likewise.
(jump_info_is_end_address, jump_info_size): Likewise.
(jump_info_unlink, jump_info_insert): Likewise.
(jump_info_add_front, jump_info_move_linked): Likewise.
(jump_info_intersect, jump_info_merge): Likewise.
(jump_info_sort, jump_info_visualize_address): Likewise.
(disassemble_jumps): New function - used to locate jumps.
(disassemble_bytes): Add ascii art generation.
(disassemble_section): Add scan to locate jumps.
(main): Parse the new visualization option.
* doc/binutils.texi: Document the new feature.
* NEWS: Mention the new feature.
opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control
flow instructions.
(print_insn_thumb16, print_insn_thumb32): Likewise.
(print_insn): Initialize the insn info.
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
ACCL/ACCH register names are only available for ARCv2 architecture,
leading to a confusion when disassembling for any other ARC
variants. This patch is changing the default names for ACCL/ACCH to
generic r58/r59.
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
reserved register name.
index_offset isn't set up for "sfsr", resulting in a random offset
being used when trying to disassemble the following.
.byte 0x3e, 0xf7, 0x07, 0x00
* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
The signed integer overflow occurred when adding one to target_count
for (i = 0; i < target_count + 1; i++)
but that's the least of the worries here. target_count was long and i
int, leading to the possibility of a loop that never ended.
So to avoid this type of vulnerability, this patch uses what I believe
to be the proper types for arguments of various wasm32 opcodes, rather
than using "long" which may change in size.
gas/
* testsuite/gas/wasm32/allinsn.d: Update expected output.
opcodes/
* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
result of wasm_read_leb128 in a uint64_t and check that bits
are not lost when copying to other locals. Use uint32_t for
most locals. Use PRId64 when printing int64_t.
Don't do that. Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long. Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.
include/
* opcode/tic4x.h (EXTR): Delete.
(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
extension using shifts. Do trim INSERTU value to specified bitfield.
opcodes/
* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
insertion.
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
and XRREG value earlier to avoid a shift with negative exponent.
* m10200-dis.c (disassemble): Similarly.
The disassembler change is such that in default mode we'd disassemble
the insns (for there not ebing any conflicts), but when AMD64 mode was
explicitly requested, we'd show them as "(bad)".
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.
opcodes/
* z8k-dis.c: Include libiberty.h
(instr_data_s): Make max_fetched unsigned.
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
Don't exceed byte_info bounds.
(output_instr): Make num_bytes unsigned.
(unpack_instr): Likewise for nibl_count and loop.
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
idx unsigned.
* z8k-opc.h: Regenerate.
gas/
* config/tc-z8k.c (md_begin): Make idx unsigned.
(get_specific): Likewise for this_index.
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to
"LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode".
These changes are necessary for GDB's atmoic sequence handler.
Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
There are probably a lot more of these still here.
cpu/
* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
bits before shifting rather than masking after shifting.
(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
(f-dsp-64-u16, f-dsp-8-s24): Likewise.
(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
opcodes/
* m32c-ibld.c: Regenerate.
PR 25344
* z80-dis.c (suffix): Don't use a local struct buffer copy.
Peek at next byte to prevent recursion on repeated prefix bytes.
Ensure uninitialised "mybuf" is not accessed.
(print_insn_z80): Don't zero n_fetch and n_used here,..
(print_insn_z80_buf): ..do it here instead.
According to the specification these permit the Q bit to control the
vector length operated on, and hence this bit should not already be set
in the opcode table entries (it rather needs setting dynamically). Note
how the test case output did also not match its input. Besides
correcting the test case also extend it to cover both forms.
PR 25224
bfd * Makefile.am: Add z80-elf target support.
* configure.ac: Likewise.
* targets.c: Likewise.
* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
* elf32-z80.c: New file.
* archures.c: Add new z80 architectures: eZ80 and Z180.
* coffcode.h: Likewise.
* cpu-z80.c: Likewise.
* bfd-in2.h: Likewise plus additional Z80 relocations.
* coff-z80.c: Add new relocations for Z80 target and local label check.
gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
for assembler code generated by SDCC. Add new relocation types. Add
z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
ld * Makefile.am: Add new target z80-elf
* configure.tgt: Likewise.
* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
* emulparams/elf32z80.sh: New file.
* emultempl/z80elf.em: Likewise.
* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/arch_r800.d: Likewise.
* testsuite/ld-z80/arch_z180.d: Likewise.
* testsuite/ld-z80/arch_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_z180.d: Likewise.
* testsuite/ld-z80/labels.s: Likewise.
* testsuite/ld-z80/relocs.s: Likewise.
* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
* testsuite/ld-z80/relocs_b_z80.d: Likewise.
* testsuite/ld-z80/relocs_f_z80.d: Likewise.
* testsuite/ld-z80/z80.exp: Likewise.
opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
Jan Beulich
Nick Clifton
Alan Modra
Christian Biesinger
H.J. Lu
Andre Vieira
Sergey Belyashov
Thomas Troeger
Claudiu Zissulescu
Shahab Vahedi