bfd * elf32-arc.c (PR_DEBUG): Delete.
Fix printing of debug information. Fix formatting of debug
statements.
(debug_arc_reloc): Handle symbols that are not from an input file.
(arc_do_relocation): Remove excessive exclamation points.
(elf_arc_relocate_section): Print an informative message if the
relocation fails, even if debugging is not enabled.
* arc-got.h: Fix formatting. Fix printing of debug information.
(new_got_entry_to_list): Use xmalloc.
* config.bfd: use the big-endian arc vector as the default vector
for big-endian arc targets.
ld * testsuite/ld-arc/arc.exp: Always run the sda-relocs test in
little endian mode.
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend. This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.
As an example assembling this program:
$ cat test.s
.text
foo:
b bar
b baz
.set bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s
produces this binary code:
$ objdump -dr test-o32.o test-n32.o
test-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
test-n32.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*+0x1230
4: 00000000 nop
8: 10000000 b c <foo+0xc>
8: R_MIPS_PC16 baz-0x4
c: 00000000 nop
$
where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word. In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.
Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise. This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.
Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function. The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.
With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:
$ objdump -dr fixed-o32.o
fixed-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000048c b 1234 <bar>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
$
Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used. Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
bfd/
* reloc.c (bfd_perform_relocation): Try the `howto' handler
first with relocations against absolute symbols.
(bfd_install_relocation): Likewise.
gas/
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/branch-absolute.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `branch-absolute-addend' and
`micromips-branch-absolute-addend', referred indirectly only.
The R_ARC_SDA32 is wrongly described as a ME relocation, fix it. Offset the
__SDATA_BEGIN__ to take advantage of the signed 9-bit field of the
load/store instructions.
include/
2016-07-08 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
ld/
2016-07-08 Claudiu Zissulescu <claziss@synopsys.com>
* emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset.
* testsuite/ld-arc/sda-relocs.dd: New file.
* testsuite/ld-arc/sda-relocs.ld: Likewise.
* testsuite/ld-arc/sda-relocs.rd: Likewise.
* testsuite/ld-arc/sda-relocs.s: Likewise.
* testsuite/ld-arc/arc.exp: Add SDA tests.
binutils/
PR binutils/20337
* objdump.c (compare_symbols): For ELF, sort same value/type
symbols according to size.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
Fix a typo (__PMSIZE was written as __PMSIZE_) and add section alignment
for DATA and BSS.
ld/ChangeLog:
* scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_.
(DATA): add ALIGN.
(BSS): add ALIGN
Before GCC 4.9, -flto is required for final LTO link. Add -flto to PR
ld/20321 test to support older versions of GCC.
* testsuite/ld-plugin/lto.exp: Add -flto to PR ld/20321 test.
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (THUMB32_MOVT): New veneer macro.
(THUMB32_MOVW): Likewise.
(elf32_arm_stub_long_branch_thumb2_only_pure): New.
(DEF_STUBS): Define long_branch_thumb2_only_pure.
(arm_stub_is_thumb): Add new veneer stub.
(arm_type_of_stub): Use new veneer.
(arm_stub_required_alignment): Add new veneer.
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* testsuite/ld-arm/farcall-thumb2-purecode.d: New test result.
* testsuite/ld-arm/farcall-thumb2-purecode.s: New test.
* testsuite/ld-arm/arm-elf.exp: Run it.
If a plugin has been loaded already, we should warn and return, instead
of adding it on the plugin list.
PR ld/20321
* plugin.c (plugin_opt_plugin): Warn and return if plugin has
been loaded already.
* testsuite/ld-plugin/lto.exp: Run PR ld/20321 test.
* testsuite/ld-plugin/pr20321.c: New file.
* scripttempl/ft32.sc (__PMSIZE_): If not defined, set to 256K.
(__RAMSIZE): If not defined, set to 64K.
(MEMORY): Set the flash region size to __PMSIZE and the ram region
size to __RAMSIZE.
2016-07-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb2_bl): New function.
(arm_type_of_stub): Declare thumb2 variable together and change type
to bfd_boolean. Use using_thumb2_bl () to determine whether
THM_MAX_FWD_BRANCH_OFFSET or THM2_MAX_FWD_BRANCH_OFFSET should be
checked for BL range.
(elf32_arm_final_link_relocate): Use using_thumb2_bl () to determine
the bit size of BL offset.
ld/
* testsuite/ld-arm/arm-elf.exp (Thumb-2 BL): Assemble for ARMv7.
(Thumb-2 BL on ARMv6-M): New testcase.
* testsuite/ld-arm/thumb2-bl.d: Do not try to match testcase filename.
* testsuite/ld-arm/thumb2-bl.s: Do not select architecture.
No need to check version if symbol is unreferenced and undefined.
bfd/
PR ld/20306
* elflink.c (elf_link_check_versioned_symbol): Return false
for unreferenced undefined symbol.
ld/testsuite/
* testsuite/ld-gc/gc.exp: Run pr20306 test.
* ld-gc/pr20306.c: New file.
* ld-gc/pr20306.d: Likewise.
bfin * elf32-bfin.c (bfin_adjust_dynamic_symbol): Fail if a COPY reloc
is needed.
ld * testsuite/ld-elf/comm-data.exp: Expect comm-data2 test to fail
for bfin.
* testsuite/ld-elf/elf.exp: Expect pr14170 and symbolic function
tests to fail for bfin.
* testsuite/ld-elf/endsym.d: Expect to fail with cr16, crx, dlx,
nds32 and visium.
* testsuite/ld-elf/var1.d: Expect to fail with d30v, dlx, ft32 and
microblaze.
* testsuite/ld-pe/pe.exp: Expect foreign symbol test to fail for
mcore-pe.
ld * testsuite/ld-elf/merge.d: Add m68hc11 to list of targets that
expect to fail this test.
* testsuite/ld-scripts/overlay-size.d: Skip the entire test for
RX.
* testsuite/ld-scripts/rgn-at10.d: No longer expect this test to
fail for the RX.
* testsuite/ld-scripts/rgn-at11.d: Likewise.
* testsuite/ld-scripts/rgn-at2.d: Likewise.
* testsuite/ld-scripts/rgn-at6.d: Likewise.
* testsuite/ld-scripts/rgn-at7.d: Likewise.
* testsuite/ld-scripts/rgn-at8.d: Likewise.
bfd * elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Don't convert
R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.
gold * sparc.cc (Target_sparc::Scan::local): Don't convert R_SPARC_32
to R_SPARC_RELATIVE if class is ELFCLASS64.
(Target_sparc::Scan::global): Likewise.
ld * testsuite/ld-elf/symbolic-func.r: Allow non-zero offsets from
.text.
PR ld/20302
* lexsup.c (set_segment_start): If resetting the start address of
a section, remember to generate a new script element as well.
* testsuite/ld-scripts/pr20302.d: New test.
* testsuite/ld-scripts/scripts.exp: Run the new test.
Add a configure option --enable-relro to decide whether -z relro should
be enabled in ELF linker by default. Default to yes for all Linux
targets, except FRV, HPPA, IA64 and MIPS, since many relro tests fail
on these targets.
PR ld/20283
* NEWS: Mention --enable-relro.
* configure.ac: Add --enable-relro.
(DEFAULT_LD_Z_RELRO): New. Set by --enable-relro.
* configure.tgt (ac_default_ld_z_relro): Default it to 1 for
some Linux targets.
* config.in: Regenerated.
* configure: Likewise.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
link_info.relro to DEFAULT_LD_Z_RELRO.
* testsuite/config/default.exp (ld_elf_shared_opt): New.
* testsuite/lib/ld-lib.exp (run_dump_test): Pass
$ld_elf_shared_opt to ld for ELF targets with shared object
support.
(run_ld_link_tests): Likewise.
As with commit ed53407eec ("MIPS/BFD: Don't stop processing on
`bfd_reloc_outofrange'") don't bail out right away and instead continue
processing on a cross-mode jump conversion error, so that any further
issues are also reported. Adjust message formatting accordingly, using
`%X' to abort processing at conclusion. Remove the full stop from the
end of the message, for consistency across error reporting.
Adjust the corresponding test case accordingly and make it trigger the
error twice.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Call
`info->callbacks->einfo' rather than `*_bfd_error_handler' and
use the `%X%H' format for the cross-mode jump conversion error
message. Remove the full stop from the end of the message.
Continue processing rather than returning failure.
ld/
* testsuite/ld-mips-elf/mode-change-error-1a.s: Trigger an error
twice rather than once.
* testsuite/ld-mips-elf/mode-change-error-1.d: Adjust
accordingly. Remove the full stop from the end of the message.
ELF linker shouldn't skip the IR object when searching the symbol table
of an archive element. If linker doesn't know if the object file is an
IR object, it should give LTO plugin a chance to get the correct symbol
table and use the IR symbol table if the input is an IR object.
bfd/
PR ld/18250
PR ld/20267
* elflink.c: Include plugin.h if BFD_SUPPORTS_PLUGINS is
defined.
(elf_link_is_defined_archive_symbol): Call
bfd_link_plugin_object_p on unknown plugin object and use the
IR symbol table if the input is an IR object.
* plugin.c (bfd_link_plugin_object_p): New function.
* plugin.h (bfd_link_plugin_object_p): New prototype.
ld/
PR ld/20267
* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
PR ld/20267.
(lto_run_tests): Likewise.
* testsuite/ld-plugin/pr20267a.c: New file.
* testsuite/ld-plugin/pr20267b.c: Likewise.
Also, don't check alignment on symbol from plugin dummy input.
bfd/
PR ld/20276
* elflink.c (elf_link_add_object_symbols): Don't check alignment
on symbol from plugin dummy input.
ld/
PR ld/20276
* plugin.c (plugin_notice): Set non_ir_ref on common symbols.
* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
PR ld/20276.
(lto_run_tests): Likewise.
* testsuite/ld-plugin/pass.out: New file.
* testsuite/ld-plugin/pr20276a.c: Likewise.
* testsuite/ld-plugin/pr20276b.c: Likewise.
2016-06-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
Tony Wang <tony.wang@arm.com>
bfd/
* elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub
sequence.
(stub_long_branch_thumb2_only): Define stub.
(arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only.
(arm_stub_long_branch_thumb2_only): Likewise.
(arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2
capable targets.
ld/
* testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile):
Assemble for ARMv6-M.
(Thumb2-Thumb2 farcall M profile): New testcase.
* testsuite/ld-arm/farcall-thumb2-thumb2-m.d: New file.
* testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to
reflect the use of Thumb-2 veneers for Thumb-2 capable targets.
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Likewise.
Since x86 elf_*_check_relocs is called after all symbols have been
resolved, there is no need to check undefined symbols for relocations
against IFUNC symbols.
bfd/
* elf32-i386.c (elf_i386_check_relocs): Don't check undefined
symbols for relocations against IFUNC symbols.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
ld/
* testsuite/ld-i386/i386.exp: Run pr19636-2e-nacl.
* testsuite/ld-i386/pr19636-2e.d: Skip for NaCl targets.
Remove .rel.plt section.
* testsuite/ld-i386/pr19636-2e-nacl.d: New file.
This patch fixes another edge case related to alignment property
records - reloc offsets adjacent to property record offsets were not
getting adjusted during relaxation.
bfd/
PR ld/20254
* elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust reloc
offsets until reloc_toaddr.
ld/
PR ld/20254
* testsuite/ld-avr/avr-prop-6.d: New test.
* testsuite/ld-avr/avr-prop-6.s: New test.
Many more places use abfd->my_archive rather than bfd_my_archive (abfd),
so let's make the code consistently use the first idiom.
bfd/
* bfd-in.h (bfd_my_archive): Delete.
* bfd-in2.h: Regenerate.
binutils/
* ar.c: Expand uses of bfd_my_archive.
* size.c: Likewise.
ld/
* ldlang.c: Expand uses of bfd_my_archive.
* ldmain.c: Likewise.
* ldmisc.c: Likewise.
* plugin.c: Likewise.
LTO plugin support in plugin_maybe_claim wants to close the IR bfd
after replacing it with the recompiled object, but can't do so for
archive elements due to various pointers that access the archive bfd.
Thin archives have the same problem. They too cannot have their
element bfds closed.
PR ld/20241
bfd/
* archive.c (open_nested_file): Set my_archive.
* bfd.c (_bfd_default_error_handler <%B>): Exclude archive file name
for thin archives.
* bfdio.c (bfd_tell): Don't adjust origin for thin archives.
(bfd_seek): Likewise.
* bfdwin.c (bfd_get_file_window): Likewise.
* cache.c (cache_bmmap): Likewise.
(bfd_cache_lookup_worker): Don't look in my_archive for thin archives.
* mach-o.c (bfd_mach_o_follow_dsym): Don't open my_archive for
thin archives.
* plugin.c (try_claim): Likewise.
* xcofflink.c (xcoff_link_add_dynamic_symbols): Use import path of
file within thin archive, not the archive.
binutils/
* bucomm.c (bfd_get_archive_filename): Return file name within thin
archive.
ld/
* ldmain.c (add_archive_element): Just print file name of file within
thin archives.
* ldmisc.c (vfinfo): Likewise.
* plugin.c (plugin_object_p): Open file within thin archives.
(plugin_maybe_claim): Expand comment.
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC
symbols if there is no base register and disallow them for PIC.
bfd/
PR ld/20244
* elf32-i386.c (elf_i386_relocate_section): Add the .got.plt
section address for R_386_GOT32/R_386_GOT32X relocations against
IFUNC symbols if there is no base register and return error for
PIC.
ld/
PR ld/20244
* testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b,
pr20244-2c and pr20244-2d.
* testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b.
* testsuite/ld-i386/pr20244-2.s: New file.
* testsuite/ld-i386/pr20244-2a.d: Likewise.
* testsuite/ld-i386/pr20244-2b.d: Likewise.
* testsuite/ld-i386/pr20244-2c.d: Likewise.
* testsuite/ld-i386/pr20244-2d.d: Likewise.
* testsuite/ld-i386/pr20244-3a.c: Likewise.
* testsuite/ld-i386/pr20244-3b.S: Likewise.
* testsuite/ld-i386/pr20244-3c.S: Likewise.
* testsuite/ld-i386/pr20244-3d.S: Likewise.
Alan Modra
Thomas Preud'homme
Nick Clifton
Maciej W. Rozycki
Claudiu Zissulescu
jamesbowman
H.J. Lu
Andre Vieria
Jan Beulich
Tristan Gingold
James Clarke
Graham Markall
Senthil Kumar Selvaraj
Cupertino Miranda