Commit Graph

2 Commits

Author SHA1 Message Date
Graham Markall
bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
Andrew Burgess
4b0c052e45 arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".

Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.

There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.

bfd/ChangeLog:

	* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-arc.c: Add 'opcode/arc.h' include.
	(struct arc_relocation_data): Add symbol_name.
	(arc_special_overflow_checks): New function.
	(arc_do_relocation): Use arc_special_overflow_checks, reindent as
	required, add an extra comment.
	(elf_arc_relocate_section): Setup symbol_name in reloc_data.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-3.d: New file.
	* testsuite/gas/arc/nps400-3.s: New file.

include/ChangeLog:

	* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
	* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.

ld/ChangeLog:

	* testsuite/ld-arc/arc.exp: New file.
	* testsuite/ld-arc/nps-1.s: New file.
	* testsuite/ld-arc/nps-1a.d: New file.
	* testsuite/ld-arc/nps-1b.d: New file.
	* testsuite/ld-arc/nps-1b.err: New file.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
	instructions.
	* arc-opc.c (insert_nps_cmem_uimm16): New function.
	(extract_nps_cmem_uimm16): New function.
	(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-04-14 17:16:46 +01:00