Pointer Authentication is a new feature in AArch64 v8.3-a. When enabled in
the compiler, function return addresses will be mangled by the kernel.
Add register description xml and wire up to aarch64_linux_read_description.
This description includes the two pauth user registers.
Nothing yet uses the feature - that is added in later patches.
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Add pauth param.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (struct target_desc): Add in pauth.
(aarch64_read_description): Add pauth param.
(aarch64_gdbarch_init): Likewise.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/Makefile: Add new files.
* features/aarch64-pauth.c: New file.
* features/aarch64-pauth.xml: New file.
gdb/doc/ChangeLog:
* gdb.texinfo: Describe pauth feature.
gdb/gdbserver/ChangeLog:
* linux-aarch64-ipa.c (get_ipa_tdesc): Add pauth param.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.c (aarch64_arch_setup): Likewise.
* linux-aarch64-tdesc-selftest.c (aarch64_tdesc_test): Likewise.
* linux-aarch64-tdesc.c (struct target_desc): Likewise.
(aarch64_linux_read_description): Likewise.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Likewise.
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
This patch adds support for Hardware Transactional Memory registers
for the powerpc linux native and core file targets, and for the
pwoerpc linux server stub.
These registers include both the HTM special-purpose registers (TFHAR,
TEXASR and TFIAR) as well as the set of registers that are
checkpointed (saved) when a transaction is initiated, which the
processor restores in the event of a transaction failure.
The set of checkpointed general-purpose registers is returned by the
linux kernel in the same format as the regular general-purpose
registers, defined in struct pt_regs. However, the architecture
specifies that only some of the registers present in pt_regs are
checkpointed (GPRs 0-31, CR, XER, LR and CTR). The kernel fills the
slots for MSR and NIP with other info. The other fields usually don't
have meaningful values. GDB doesn't define registers that are not
checkpointed in the architecture, but when generating a core file, GDB
fills the slot for the checkpointed MSR with the regular MSR. These
are usually similar, although some bits might be different, and in
some cases the checkpointed MSR will have a value of 0 in a
kernel-generated core-file. The checkpointed NIP is filled with TFHAR
by GDB in the core-file, which is what the kernel does. The other
fields are set to 0 by GDB.
Core files generated by the kernel have a note section for
checkpointed GPRs with the same size for both 32-bit and 64-bit
threads, and the values for the registers of a 32-bit thread are
squeezed in the first half, with no useful data in the second half.
GDB generates a smaller note section for 32-bit threads, but can read
both sizes.
The checkpointed XER is required to be 32-bit in the target
description documentation, even though the more recent ISAs define it
as 64-bit wide, since the high-order 32-bits are reserved, and because
in Linux there is no way to get a 64-bit checkpointed XER for 32-bit
threads. If this changes in the future, the target description
feature requirement can be relaxed to allow for a 64-bit checkpointed
XER.
Access to the checkpointed CR (condition register) can be confusing.
The architecture only specifies that CR fields 1 to 7 (the 24 least
significant bits) are checkpointed, but the kernel provides all 8
fields (32 bits). The value of field 0 is not masked by ptrace, so it
will sometimes show the result of some kernel operation, probably
treclaim., which sets this field.
The checkpointed registers are marked not to be saved and restored.
Inferior function calls during an active transaction don't work well,
and it's unclear what should be done in this case. TEXASR and TFIAR
can be altered asynchronously, during transaction failure recording,
so they are also not saved and restored. For consistency neither is
TFHAR.
Record and replay also doesn't work well when transactions are
involved. This patch doesn't address this, so the values of the HTM
SPRs will sometimes be innacurate when the record/relay target is
enabled. For instance, executing a "tbegin." alters TFHAR and TEXASR,
but these changes are not currently recorded.
Because the checkpointed registers are only available when a
transaction is active (or suspended), ptrace can return ENODATA when
gdb tries to read these registers and the inferior is not in a
transactional state. The registers are set to the unavailable state
when this happens. When gbd tries to write to one of these registers,
and it is unavailable, an error is raised.
The "fill" functions for checkpointed register sets in the server stub
are not implemented for the same reason as for the EBB register set,
since ptrace can also return ENODATA for checkpointed regsets. The
same issues with 'G' packets apply here.
Just like for the EBB registers, tracepoints will not mark the
checkpointed registers as unavailable if the inferior was not in a
transaction, so their content will also show 0 instead of
<unavailable> when inspecting trace data.
The new tests record the values of the regular registers before
stepping the inferior through a "tbegin." instruction to start a
transaction, then the checkpointed registers are checked against the
recorded pre-transactional values. New values are written to the
checkpointed registers and recorded, the inferior continues until the
transaction aborts (which is usually immediately when it is resumed),
and the regular registers are checked against the recorded values,
because the abort should have reverted the registers to these values.
Like for the EBB registers, target_store_registers will ignore the
checkpointed registers when called with -1 as the regno
argument (store all registers in one go).
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_htm_vsx32l)
(tdesc_powerpc_isa207_htm_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TM_SPRREGSET)
(PPC32_LINUX_SIZEOF_CGPRREGSET, PPC64_LINUX_SIZEOF_CGPRREGSET)
(PPC_LINUX_SIZEOF_CFPRREGSET, PPC_LINUX_SIZEOF_CVMXREGSET)
(PPC_LINUX_SIZEOF_CVSXREGSET, PPC_LINUX_SIZEOF_CPPRREGSET)
(PPC_LINUX_SIZEOF_CDSCRREGSET, PPC_LINUX_SIZEOF_CTARREGSET):
Define.
(struct ppc_linux_features) <htm>: New field.
(ppc_linux_no_features): Add initializer for htm field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_HTM, NT_PPC_TM_CGPR)
(NT_PPC_TM_CFPR, NT_PPC_TM_CVMX, NT_PPC_TM_CVSX)
(NT_PPC_TM_SPR, NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR):
Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-htm-vsx32l
and rs6000/powerpc-isa207-htm-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-htm-vsx32l.xml and
rs6000/powerpc-isa207-htm-vsx64l.xml.
* features/rs6000/power-htm-spr.xml: New file.
* features/rs6000/power-htm-core.xml: New file.
* features/rs6000/power64-htm-core.xml: New file.
* features/rs6000/power-htm-fpu.xml: New file.
* features/rs6000/power-htm-altivec.xml: New file.
* features/rs6000/power-htm-vsx.xml: New file.
* features/rs6000/power-htm-ppr.xml: New file.
* features/rs6000/power-htm-dscr.xml: New file.
* features/rs6000/power-htm-tar.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-htm-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with HTM regsets.
(store_register, store_ppc_registers): Call store_regset with HTM
regsets.
(ppc_linux_nat_target::read_description): Set htm field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-htm-vsx32l.c and
features/rs6000/powerpc-isa207-htm-vsx64l.c.
(ppc32_regmap_tm_spr, ppc32_regmap_cgpr, ppc64_le_regmap_cgpr)
(ppc64_be_regmap_cgpr, ppc32_regmap_cfpr, ppc32_le_regmap_cvmx)
(ppc32_be_regmap_cvmx, ppc32_regmap_cvsx, ppc32_regmap_cppr)
(ppc32_regmap_cdscr, ppc32_regmap_ctar): New globals.
(ppc32_linux_tm_sprregset, ppc32_linux_cgprregset)
(ppc64_be_linux_cgprregset, ppc64_le_linux_cgprregset)
(ppc32_linux_cfprregset, ppc32_le_linux_cvmxregset)
(ppc32_be_linux_cvmxregset, ppc32_linux_cvsxregset)
(ppc32_linux_cpprregset, ppc32_linux_cdscrregset)
(ppc32_linux_ctarregset): New globals.
(ppc_linux_cgprregset, ppc_linux_cvmxregset): New functions.
(ppc_linux_collect_core_cpgrregset): New function.
(ppc_linux_iterate_over_regset_sections): Call back with the htm
regsets.
(ppc_linux_core_read_description): Check if the tm spr section is
present and set htm in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_htm_vsx32l and
initialize_tdesc_powerpc_isa207_htm_vsx64l.
* ppc-linux-tdep.h (ppc_linux_cgprregset, ppc_linux_cvmxregset):
Declare.
(ppc32_linux_tm_sprregset, ppc32_linux_cfprregset)
(ppc32_linux_cvsxregset, ppc32_linux_cpprregset)
(ppc32_linux_cdscrregset, ppc32_linux_ctarregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <have_htm_spr, have_htm_core>:
New fields.
<have_htm_fpu, have_htm_altivec, have_htm_vsx>:
Likewise.
<ppc_cppr_regnum, ppc_cdscr_regnum, ppc_ctar_regnum>: Likewise.
<ppc_cdl0_regnum, ppc_cvsr0_regnum, ppc_cefpr0_regnum>: Likewise.
(enum) <PPC_TFHAR_REGNUM, PPC_TEXASR_REGNUM, PPC_TFIAR_REGNUM>:
New enum fields.
<PPC_CR0_REGNUM, PPC_CCR_REGNUM, PPC_CXER_REGNUM>: Likewise.
<PPC_CLR_REGNUM, PPC_CCTR_REGNUM, PPC_CF0_REGNUM>: Likewise.
<PPC_CFPSCR_REGNUM, PPC_CVR0_REGNUM, PPC_CVSCR_REGNUM>: Likewise.
<PPC_CVRSAVE_REGNUM, PPC_CVSR0_UPPER_REGNUM>: Likewise.
<PPC_CPPR_REGNUM, PPC_CDSCR_REGNUM>: Likewise.
<PPC_CTAR_REGNUM>: Likewise.
(PPC_IS_TMSPR_REGNUM, PPC_IS_CKPTGP_REGNUM, PPC_IS_CKPTFP_REGNUM)
(PPC_IS_CKPTVMX_REGNUM, PPC_IS_CKPTVSX_REGNUM): Define.
* rs6000-tdep.c (IS_CDFP_PSEUDOREG, IS_CVSX_PSEUDOREG)
(IS_CEFP_PSEUDOREG): Define.
(rs6000_register_name): Hide the upper halves of checkpointed VSX
registers. Return names for the checkpointed DFP, VSX, and EFP
pseudo registers.
(rs6000_pseudo_register_type): Remove initial assert and raise an
internal error in the else clause instead. Return types for the
checkpointed DFP, VSX, and EFP pseudo registers.
(dfp_pseudo_register_read, dfp_pseudo_register_write): Handle
checkpointed DFP pseudo registers.
(vsx_pseudo_register_read, vsx_pseudo_register_write): Handle
checkpointed VSX pseudo registers.
(efp_pseudo_register_read, efp_pseudo_register_write): Rename
from efpr_pseudo_register_read and
efpr_pseudo_register_write. Handle checkpointed EFP pseudo
registers.
(rs6000_pseudo_register_read, rs6000_pseudo_register_write):
Handle checkpointed DFP, VSX, and EFP registers.
(dfp_ax_pseudo_register_collect, vsx_ax_pseudo_register_collect)
(efp_ax_pseudo_register_collect): New functions.
(rs6000_ax_pseudo_register_collect): Move DFP, VSX and EFP pseudo
register logic to new functions. Handle checkpointed DFP, VSX,
and EFP pseudo registers.
(rs6000_gdbarch_init): Look for and validate the htm features.
Include checkpointed DFP, VSX and EFP pseudo-registers.
* NEWS: Mention access to PPR, DSCR, TAR, EBB/PMU registers and
HTM registers.
gdb/gdbserver/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-htm-vsx32l-ipa.o and
powerpc-isa207-htm-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-htm-vsx32l.o and
powerpc-isa207-htm-vsx64l.o to srv_regobj. Add
rs6000/power-htm-spr.xml, rs6000/power-htm-core.xml,
rs6000/power64-htm-core.xml, rs6000/power-htm-fpu.xml,
rs6000/power-htm-altivec.xml, rs6000/power-htm-vsx.xml,
rs6000/power-htm-ppr.xml, rs6000/power-htm-dscr.xml,
rs6000/power-htm-tar.xml, rs6000/powerpc-isa207-htm-vsx32l.xml,
and rs6000/powerpc-isa207-htm-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_HTM_VSX>: New enum value.
(init_registers_powerpc_isa207_htm_vsx32l)
(init_registers_powerpc_isa207_htm_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tm_sprregset, ppc_store_tm_sprregset)
(ppc_store_tm_cgprregset, ppc_store_tm_cfprregset)
(ppc_store_tm_cvrregset, ppc_store_tm_cvsxregset)
(ppc_store_tm_cpprregset, ppc_store_tm_cdscrregset)
(ppc_store_tm_ctarregset): New functions.
(ppc_regsets): Add entries for HTM regsets.
(ppc_arch_setup): Set htm in features struct when needed. Set
sizes for the HTM regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-htm-regs.c: New file.
* gdb.arch/powerpc-htm-regs.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new features
"org.gnu.gdb.power.htm.spr", "org.gnu.gdb.power.htm.core",
"org.gnu.gdb.power.htm.fpu", "org.gnu.gdb.power.htm.altivec",
"org.gnu.gdb.power.htm.vsx", "org.gnu.gdb.power.htm.ppr",
"org.gnu.gdb.power.htm.dscr", "org.gnu.gdb.power.htm.tar".
This patch adds support for the Target Address Register for powerpc
linux native and core file targets, and in the powerpc linux server
stub.
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_vsx32l)
(tdesc_powerpc_isa207_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TARREGSET): Define.
(struct ppc_linux_features) <isa207>: New field.
(ppc_linux_no_features): Add initializer for isa207 field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_ARCH_2_07, PPC_FEATURE2_TAR)
(NT_PPC_TAR): Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-vsx32l and
rs6000/powerpc-isa207-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-vsx32l.xml and
rs6000/powerpc-isa207-vsx64l.xml.
* features/rs6000/power-tar.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with the TAR regset.
(store_register, store_ppc_registers): Call store_regset with the
TAR regset.
(ppc_linux_nat_target::read_description): Set isa207 field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-vsx32l.c and
features/rs6000/powerpc-isa207-vsx64l.c.
(ppc32_regmap_tar, ppc32_linux_tarregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the tar
regset.
(ppc_linux_core_read_description): Check if the tar section is
present and set isa207 in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_vsx32l and
initialize_tdesc_powerpc_isa207_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_tarregset): Declare.
* ppc-tdep.h (gdbarch_tdep) <ppc_tar_regnum>: New field.
(enum) <PPC_TAR_REGNUM>: New enum value.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate tar
feature.
(ppc_process_record_op31): Record changes to TAR.
gdb/gdbserver/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-vsx64l-ipa.o and powerpc-isa207-vsx32l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-vsx32l.o and
powerpc-isa207-vsx64l.o to srv_regobj, add rs6000/power-tar.xml,
rs6000/powerpc-isa207-vsx32l.xml, and
rs6000/powerpc-isa207-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_VSX>: New enum value.
(init_registers_powerpc_isa207_vsx32l): Declare.
(init_registers_powerpc_isa207_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tarregset): New function.
(ppc_store_tarregset): New function.
(ppc_regsets): Add entry for the TAR regset.
(ppc_arch_setup): Set isa207 in features struct when needed. Set
size for the TAR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX.
(initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l
and init_registers_powerpc_isa207_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_vsx32l and
init_registers_powerpc_isa207_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-tar.c: New file.
* gdb.arch/powerpc-tar.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new feature
"org.gnu.gdb.power.tar".
This patch adds gdb support for the Program Priorty Register and the
Data Stream Control Register, for the powerpc linux native and core
file targets, and for the powerpc linux server stub.
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa205_ppr_dscr_vsx32l)
(tdesc_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_PPRREGSET)
(PPC_LINUX_SIZEOF_DSCRREGSET): Define.
(struct ppc_linux_features) <ppr_dscr>: New field.
(ppc_linux_no_features): Add initializer for ppr_dscr field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_DSCR, NT_PPC_PPR, NT_PPC_DSCR):
Define if not already defined.
* features/Makefile (WHICH): Add
rs6000/powerpc-isa205-ppr-dscr-vsx32l and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml.
* features/rs6000/power-dscr.xml: New file.
* features/rs6000/power-ppr.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Generate.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat: Generate.
* ppc-linux-nat.c: Include <sys/uio.h>.
(fetch_regset, store_regset, check_regset): New functions.
(fetch_register, fetch_ppc_registers): Call fetch_regset with
DSCR and PPR regsets.
(store_register, store_ppc_registers): Call store_regset with
DSCR and PPR regsets.
(ppc_linux_get_hwcap2): New function.
(ppc_linux_nat_target::read_description): Call
ppc_linux_get_hwcap2 and check_regset, set ppr_dscr field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c and
features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c.
(ppc32_regmap_ppr, ppc32_regmap_dscr, ppc32_linux_pprregset)
(ppc32_linux_dscrregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the ppr
and dscr regsets.
(ppc_linux_core_read_description): Check if the ppr and dscr
sections are present and set ppr_dscr in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l and
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_pprregset)
(ppc32_linux_dscrregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <ppc_ppr_regnum>: New field.
<ppc_dscr_regnum>: New field.
(enum) <PPC_PPR_REGNUM, PPC_DSCR_REGNUM>: New enum values.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate ppr
and dscr features.
(ppc_process_record_op31): Record changes to PPR and DSCR.
gdb/gdbserver/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa205-ppr-dscr-vsx32l-ipa.o and
powerpc-isa205-ppr-dscr-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa205-ppr-dscr-vsx32l.o and
powerpc-isa205-ppr-dscr-vsx64l.o to srv_regobj, add
rs6000/power-dscr.xml, rs6000/power-ppr.xml,
rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA205_PPR_DSCR_VSX>: New enum value.
(init_registers_powerpc_isa205_ppr_dscr_vsx32l)
(init_registers_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* linux-ppc-low.c: Include "elf/common.h" and <sys/uio.h>.
(ppc_hwcap): Add comment.
(ppc_hwcap2): New global.
(ppc_check_regset, ppc_fill_pprregset, ppc_store_pprregset)
(ppc_fill_dscrregset, ppc_store_dscrregset): New functions.
(ppc_regsets): Add entries for the DSCR and PPR regsets.
(ppc_arch_setup): Get AT_HWCAP2. Set ppr_dscr in features struct
when needed. Set sizes for the the DSCR and PPR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-ppr-dscr.c: New file.
* gdb.arch/powerpc-ppr-dscr.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new features
"org.gnu.gdb.power.ppr" and "org.gnu.gdb.power.dscr".
This patch prepares the current GDB port of the OpenRISC processor from
https://github.com/openrisc/binutils-gdb for upstream merging.
Testing has been done with a cgen sim provided in a separate patch. This
has been tested with 2 toolchains. GCC [1] 5.4.0 from the OpenRISC
project with Newlib [2] and GCC 5.4.0 with Musl [3] 1.1.4.
It supports or1knd (no delay slot target).
The default target is or1k (with delay slot).
You can change the target arch with:
(gdb) set architecture or1knd
The target architecture is assumed to be or1knd
[1] https://github.com/openrisc/or1k-gcc
[2] https://github.com/openrisc/newlib
[3] https://github.com/openrisc/musl-cross
gdb/doc/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Stefan Wallentowitz <stefan@wallentowitz.de>
Franck Jullien <franck.jullien@gmail.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* gdb.texinfo: Add OpenRISC documentation.
gdb/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Stefan Wallentowitz <stefan@wallentowitz.de>
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Franck Jullien <franck.jullien@gmail.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure.tgt: Add targets for or1k and or1knd.
* or1k-tdep.c: New file.
* or1k-tdep.h: New file.
* features/Makefile: Add or1k.xml to build.
* features/or1k.xml: New file.
* features/or1k-core.xml: New file.
* features/or1k.c: Generated.
This patch changes tic6x target descriptions to be more flexible. Rebuild
tic6x-uclinux GDBserver with my x86 g++, and the unit test passes.
gdb:
2017-11-24 Yao Qi <yao.qi@linaro.org>
* arch/tic6x.c: New file.
* arch/tic6x.h: New file.
* features/Makefile (FEATURE_XMLFILES): Add tic6x-c6xp.xml,
tic6x-core.xml and tic6x-gp.xml.
* features/tic6x-c6xp.c: Generated.
* features/tic6x-core.c: Generated.
* features/tic6x-gp.c: Generated.
* target-descriptions.c (maint_print_c_tdesc_cmd): Match
"tic6x-".
gdb/gdbserver:
2017-11-24 Yao Qi <yao.qi@linaro.org>
* configure.srv: Set $srv_regobj for tic6x-linux.
* linux-tic6x-low.c: Include "arch/tic6x.h" and "tdesc.h".
(tic6x_read_description): Move some code to tic6x_arch_setup.
(tic6x_tdesc_test): New function.
(initialize_low_arch): Call selftests::register_test.
tdesc_nios2_linux is not used at all. Remove features/nios2-linux.c,
and don't generate it anymore.
gdb:
2017-11-15 Yao Qi <yao.qi@linaro.org>
* features/Makefile (XMLTOC): Remove nios2-linux.xml.
* features/nios2-linux.c: Remove.
* nios2-linux-tdep.c (_initialize_nios2_linux_tdep): Don't call
initialize_tdesc_nios2_linux.
features/*.c are generated from *.xml files, in order to get pre-defined
target descriptions, (for native debugging, for example). However, these
pre-generated tdesc_tic6x_* are not used in GDB at all. This patch removes
features/tic6x-*.c files.
gdb:
2017-10-16 Yao Qi <yao.qi@linaro.org>
* features/Makefile (XMLTOC): Remove tic6x-*.xml.
* features/tic6x-c62x.c: Remove.
* features/tic6x-c64x-linux.c: Remove.
* features/tic6x-c64x.c: Remove.
* features/tic6x-c64xp-linux.c: Remove.
* features/tic6x-c64xp.c: Remove.
* tic6x-linux-tdep.c (_initialize_tic6x_linux_tdep): Don't call
initialize_tdesc_tic6x_*_linux functions.
* tic6x-tdep.c (_initialize_tic6x_tdep): Don't call
initialize_tdesc_tic6x_* functions.
tic6x-uclinux GDBserver uses linux target descriptions, instead of these
non-linux target descriptions. So we can remove these *.dat files.
gdb:
2017-10-16 Yao Qi <yao.qi@linaro.org>
* features/Makefile (WHICH): Remove tic6x-c64xp, tic6x-c64x
tic6x-c62x.
* regformats/tic6x-c62x.dat: Remove.
* regformats/tic6x-c64x.dat: Remove.
* regformats/tic6x-c64xp.dat: Remove.
Nowadays, we have six tic6x expedite registers, which are duplicated.
tic6x-c64xp-expedite = A15,PC
tic6x-c64x-expedite = A15,PC
tic6x-c62x-expedite = A15,PC
tic6x-c64xp-linux-expedite = A15,PC
tic6x-c64x-linux-expedite = A15,PC
tic6x-c62x-linux-expedite = A15,PC
in features/Makefile, we have
echo "expedite:$(if $($*-expedite),$($*-expedite),$($(firstword $(subst -, ,$(notdir $*)))-expedite))" \
>> $(outdir)/$*.tmp
which means for a given bar/foo-baz.xml, we'll look for either
bar/foo-baz-expedite or foo-expedite. We can define only one generic
expedite register for all different ti6cx and s390x target descriptions.
Actually, we've done that for x86 target descriptions.
Re-run 'make GDB=/path/build/gdb all' to regenerate regformats/*.dat files,
and they are not changed.
gdb:
2017-10-13 Yao Qi <yao.qi@linaro.org>
* features/Makefile: Remove tic6x-*-expedite, add tic6x-expedite.
Remove s390x-*-expedite, add s390x-expedite.
Newer Linux kernel versions offer two new register sets in support of the
z/Architecture's guarded storage facility. This patch adds XML
descriptions and the respective autogenerated .c and .dat files for
s390/s390x targets with this feature.
gdb/ChangeLog:
* features/s390-gs-linux64.xml: New file.
* features/s390-gs.xml: New file.
* features/s390-gsbc.xml: New file.
* features/s390x-gs-linux64.xml: New file.
* features/Makefile (WHICH): Add s390-gs-linux64 and
s390x-gs-linux64.
(s390-gs-linux64-expedite, s390x-gs-linux64-expedite): New macros.
(XMLTOC): Add s390-gs-linux64.xml and s390x-linux64.xml.
* features/s390-gs-linux64.c: New generated file.
* features/s390x-gs-linux64.c: New file.
* regformats/s390-gs-linux64.dat: New file.
* regformats/s390x-gs-linux64.dat: New file.
In an old commit the backslash of was missing in the rule for creating the
i386-avx-mpx-avx512-pku.dat file. No need to regenerate the files, this
was done by another commit from Yao.
2017-09-20 Walfred Tedeschi <walfred.tedeschi@intel.com>
* features/Makefile (i386-avx-mpx-avx512-pku.dat): Add backslash.
This patch changes Makefile and command "maint print c-files" so
that GDB can print c files for features instead target description.
Previously, we feed GDB a target description xml file, which generate
c files including multiple features.
With this patch, in Makefile, we wrap each feature xml file, and
create a temp target description which include only one feature.
Then, adjust the target description printer for them, and print
a c function for each given feature, so that we can use these
c functions later to create target description in a flexible way.
gdb:
2017-07-26 Yao Qi <yao.qi@linaro.org>
* features/Makefile (CFILES): Rename with TDESC_CFILES.
(FEATURE_XMLFILES): New.
(FEATURE_CFILES): New.
New rules.
(clean-cfiles): Remove generated c files.
* features/i386/32bit-avx.c: Generated.
* features/i386/32bit-avx512.c: Generated.
* features/i386/32bit-core.c: Generated.
* features/i386/32bit-linux.c: Generated.
* features/i386/32bit-mpx.c: Generated.
* features/i386/32bit-pkeys.c: Generated.
* features/i386/32bit-sse.c: Generated.
* target-descriptions.c: Include algorithm.
(tdesc_element_visitor): Add method visit_end.
(print_c_tdesc): Implement visit_end.
(print_c_tdesc:: m_filename_after_features): Move it to
protected.
(print_c_feature): New class.
(maint_print_c_tdesc_cmd): Use print_c_feature if XML file
name starts with "i386/32bit-".
Nowadays, we need two steps to print c files for xml target description,
that is, 1) read xml target description in, update the current tdesc,
2) visit the current tdesc, print the c file. It is unnecessary to
involve in current tdesc, and some validations in each gdbarch are
performed unnecessarily, which will reject some target descriptions if
they are missing some mandatory feature.
This patch adds an optional argument to "maint print c-tdesc", which
is an XML file target description, so that we can combine the two
steps above into one step, and don't have to involve in global current
tdesc.
gdb:
2017-07-26 Yao Qi <yao.qi@linaro.org>
* NEWS: Mention it.
* features/Makefile (%.c: %.xml): Pass the xml file name to
command "maint print c-tdesc".
* target-descriptions.c (maint_print_c_tdesc_cmd): Get file
name from 'arg'.
gdb/doc:
2017-07-26 Yao Qi <yao.qi@linaro.org>
* gdb.texinfo (Maintenance Commands): Document optional
argument of "maint print c-tdesc".
This patch allows examination of the registers FS_BASE and GS_BASE
for Linux Systems running on 64bit. Tests for simple read and write
of the new registers is also added with this patch.
2017-01-27 Walfred Tedeschi <walfred.tedeschi@intel.com>
Richard Henderson <rth@redhat.com>
gdb/ChangeLog:
* amd64-linux-nat.c (PTRACE_ARCH_PRCTL): New define.
(amd64_linux_fetch_inferior_registers): Add case to fetch FS_BASE
GS_BASE for older kernels.
(amd64_linux_store_inferior_registers): Add case to store FS_BASE
GS_BASE for older kernels.
* amd64-linux-tdep.c (amd64_linux_gregset_reg_offset): Add FS_BASE
and GS_BASE to the offset table.
(amd64_linux_register_reggroup_p): Add FS_BASE and GS_BASE to the
system register group.
* amd64-nat.c (amd64_native_gregset_reg_offset): Implements case
for older kernels.
* amd64-tdep.c (amd64_init_abi): Add segment registers for the
amd64 ABI.
* amd64-tdep.h (amd64_regnum): Add AMD64_FSBASE_REGNUM and
AMD64_GSBASE_REGNUM.
(AMD64_NUM_REGS): Set to AMD64_GSBASE_REGNUM + 1.
* features/Makefile (amd64-linux.dat, amd64-avx-linux.dat)
(amd64-mpx-linux.dat, amd64-avx512-linux.dat, x32-linux.dat)
(x32-avx-linux.dat, x32-avx512-linux.dat): Add
i386/64bit-segments.xml in those rules.
* features/i386/64bit-segments.xml: New file.
* features/i386/amd64-avx-mpx-linux.xml: Add 64bit-segments.xml.
* features/i386/amd64-avx-linux.xml: Add 64bit-segments.xml.
* features/i386/amd64-avx512-linux.xml: Add 64bit-segments.xml.
* features/i386/amd64-mpx-linux.xml: Add 64bit-segments.xml.
* features/i386/x32-avx512-linux.xml: Add 64bit-segments.xml.
* features/i386/x32-avx-linux.xml: Add 64bit-segments.xml.
* features/i386/amd64-linux.xml: Add 64bit-segments.xml.
* features/i386/amd64-avx-linux.c: Regenerated.
* features/i386/amd64-avx-mpx-linux.c: Regenerated.
* features/i386/amd64-avx-mpx.c: Regenerated.
* features/i386/amd64-avx512-linux.c: Regenerated.
* features/i386/amd64-linux.c: Regenerated.
* features/i386/amd64-mpx-linux.c: Regenerated.
* features/i386/i386-avx-mpx-linux.c: Regenerated.
* features/i386/i386-avx-mpx.c: Regenerated.
* features/i386/x32-avx-linux.c: Regenerated.
* features/i386/x32-avx512-linux.c: Regenerated.
* regformats/i386/amd64-avx-linux.dat: Regenerated.
* regformats/i386/amd64-avx-mpx-linux.dat: Regenerated.
* regformats/i386/amd64-avx512-linux.dat: Regenerated.
* regformats/i386/amd64-linux.dat: Regenerated.
* regformats/i386/amd64-mpx-linux.dat: Regenerated.
* regformats/i386/x32-avx-linux.dat: Regenerated.
* regformats/i386/x32-avx512-linux.dat: Regenerated.
* regformats/i386/x32-linux.dat: Regenerated.
gdb/doc/ChangeLog:
* gdb.texinfo (i386 Features): Add system segment registers
as feature.
gdb/gdbserver/ChangeLog:
* linux-x86-low.c (x86_64_regmap): Add fs_base and gs_base
to the register table.
(x86_fill_gregset): Add support for old kernels for the
fs_base and gs_base system registers.
(x86_store_gregset): Likewise.
* configure.srv (srv_i386_64bit_xmlfiles): Add 64bit-segments.xml.
gdb/testsuite/ChangeLog:
* gdb.arch/amd64-gs_base.c: New file.
* gdb.arch/amd64-gs_base.exp: New file.
Change-Id: I2e0eeb93058a2320d4d3b045082643cfe4aff963
Signed-off-by: Walfred Tedeschi <walfred.tedeschi@intel.com>
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
If I remove all regformats/*.dat files and run
make GDB=/scratch/yao/gdb/build-git/all-targets/gdb/gdb all, some
powerpc .dat files are not generated.
This patch fixes it by adding them to WHICH, so these .dat files can
be generated.
gdb:
2016-10-05 Yao Qi <yao.qi@linaro.org>
* features/Makefile (WHICH): Add
rs6000/powerpc-isa205-32l, rs6000/powerpc-isa205-64l,
rs6000/powerpc-isa205-altivec32l, rs6000/powerpc-isa205-altivec64l,
rs6000/powerpc-isa205-vsx32l and rs6000/powerpc-isa205-vsx64l.
* regformats/rs6000/powerpc-isa205-32l.dat: Regenerated.
* regformats/rs6000/powerpc-isa205-64l.dat: Likewise.
* regformats/rs6000/powerpc-isa205-altivec32l.dat: Likewise.
* regformats/rs6000/powerpc-isa205-altivec64l.dat: Likewise.
* regformats/rs6000/powerpc-isa205-vsx32l.dat: Likewise.
* regformats/rs6000/powerpc-isa205-vsx64l.dat: Likewise.
If I delete all target description c files under features/ directory,
and run make GDB=/scratch/yao/gdb/build-git/all-targets/gdb/gdb cfiles,
some s390 target description c files are not generated.
This patch adds these s390 xml files to XMLTOC, so these c files can
be generated.
gdb:
2016-10-05 Yao Qi <yao.qi@linaro.org>
* features/Makefile (XMLTOC): Add s390-tevx-linux64.xml,
s390-vx-linux64.xml, s390x-tevx-linux64.xml and
s390x-vx-linux64.xml.
Nowadays, there are a lot of duplication about
i386/{i386, amd64, x32}*-expedite in features/Makefile. However,
in features/Makefile, we have
echo "expedite:$(if $($*-expedite),$($*-expedite),$($(firstword $(subst -, ,$(notdir $*)))-expedite))" \
>> $(outdir)/$*.tmp
which means for a given bar/foo-baz.xml, we'll look for either
bar/foo-baz-expedite or foo-expedite. In x86 expedite registers, we
use the former now, but it will be much simpler if we use the latter.
This is what this patch does. This patch removes them, and defines
three generic expedite. Re-run 'make GDB=/path/build/gdb all' to
regenerate regformats/*.dat files, and they are not changed.
gdb:
2016-10-05 Yao Qi <yao.qi@linaro.org>
* features/Makefile: Remove i386/*-expedite. Add i386-expedite,
amd64-expedite, and x32-expedite.
This patch is move features/arm-*.xml to features/arm/, and it is based
on Terry's patch posted here
https://sourceware.org/ml/gdb-patches/2014-06/msg00794.html
One comment to Terry's patch is about losing "arm" prefix, and the new
patch fixes this problem.
gdb:
2016-10-05 Terry Guo <terry.guo@arm.com>
Yao Qi <yao.qi@linaro.org>
* arm-tdep.c: Adjust includes.
* features/Makefile (WHICH): Add "arm/" directory to arm
target descriptions.
(XMLTOC): Likewise.
(arm/arm-with-iwmmxt.dat): Adjust the path for
dependencies.
* features/arm-core.xml: Moved to ...
* features/arm/arm-core.xml: ... it.
* features/arm-fpa.xml: Moved to ...
* features/arm/arm-fpa.xml: ... it.
* features/arm-m-profile.xml: Moved to ...
* features/arm/arm-m-profile.xm: ... it.
* features/arm-vfpv2.xml: Moved to ...
* features/arm/arm-vfpv2.xm: ... it.
* features/arm-vfpv3.xml: Moved to ...
* features/arm/arm-vfpv3.xml: ... it.
* features/arm-with-iwmmxt.c: Moved to ...
* features/arm/arm-with-iwmmxt.c: ... it.
* features/arm-with-iwmmxt.xml: Moved to ...
* features/arm/arm-with-iwmmxt.xml: ... it.
* features/arm-with-m-fpa-layout.c: Moved to ...
* features/arm/arm-with-m-fpa-layout.c: ... it.
* features/arm-with-m-fpa-layout.xml: Moved to ...
* features/arm/arm-with-m-fpa-layout.xml: ... it.
* features/arm-with-m-vfp-d16.c: Moved to ...
* features/arm/arm-with-m-vfp-d16.c: ... it.
* features/arm-with-m-vfp-d16.xml: Moved to ...
* features/arm/arm-with-m-vfp-d16.xml: ... it.
* features/arm-with-m.c: Moved to ...
* features/arm/arm-with-m.c: ... it.
* features/arm-with-m.xml: Moved to ...
* features/arm/arm-with-m.xm: ... it.
* features/arm-with-neon.c: Moved to ...
* features/arm/arm-with-neon.c: ... it.
* features/arm-with-neon.xml: Moved to ...
* features/arm/arm-with-neon.xml: ... it.
* features/arm-with-vfpv2.c: Moved to ...
* features/arm/arm-with-vfpv2.c: ... it.
* features/arm-with-vfpv2.xml: Moved to ...
* features/arm/arm-with-vfpv2.xml: ... it.
* features/arm-with-vfpv3.c: Moved to ...
* features/arm/arm-with-vfpv3.c: ... it.
* features/arm-with-vfpv3.xml: Moved to ...
* features/arm/arm-with-vfpv3.xml: ... it.
* features/xscale-iwmmxt.xml: Moved to ...
* features/arm/xscale-iwmmxt.xml: ... it.
gdb/gdbserver:
2016-10-05 Terry Guo <terry.guo@arm.com>
Yao Qi <yao.qi@linaro.org>
* Makefile.in: Adjust the path of rules.
* configure.srv: Update the path of xml files.
* regformats/arm-with-iwmmxt.dat: Regenerated.
* regformats/arm-with-neon.dat: Likewise.
* regformats/arm-with-vfpv2.dat: Likewise.
* regformats/arm-with-vfpv3.dat Likewise.
ARC is a family of licensable processors developed by Synopsys.
This is an initial patch that doesn't yet support some of the features, that
are already available in Synopsys' fork of GDB, namely:
* longjmp support
* signal frame handling
* prologue analysis
* Linux targets support
* native Linux support
ARC cores are configurable and extensible, which means from debugger
perspective that some registers and debug capabilities are optional, therefore
it is up to the GDB stub to determine exact list of register available on
target and supply it to GDB via XML target descriptions. List of registers
that is known to GDB and is required is intentionally kept small to simplify
requirements to GDB stub and implementation of a GDB client.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add arc-tdep.o.
(HFILES_NO_SRCDIR): Add arc-tdep.h.
(ALLDEPFILES): Add arc-tdep.c.
* NEWS: Mention new ARC port.
* configure.tgt: Add ARC.
* arc-tdep.c: New file.
* arc-tdep.h: New file.
* features/Makefile (XMLTOC): Add arc-v2.xml and arc-arcompact.xml.
* features/arc-v2.xml: New file.
* features/arc-v2.c: New file (generated).
* features/arc-arcompact.xml: New file.
* features/arc-arcompact.c: New file (generated).
gdb/doc/ChangeLog:
* gdb.texinfo (Embedded Processors): Document ARC.
(Synopsys ARC): New section.
(Standard Target Features): Document ARC features.
(ARC Features): New section.
gdb/testsuite/ChangeLog:
* gdb.xml/tdesc-regs.exp: set core-regs for arc*-*-elf32.
The current MPX target descriptions assume that MPX is always combined
with AVX, however that's not correct. We can have machines with MPX
and without AVX; or machines with AVX and without MPX.
This patch adds new target descriptions for machines that support
both MPX and AVX, as duplicates of the existing MPX descriptions.
The following commit will remove AVX from the MPX-only descriptions.
2016-04-16 Walfred Tedeschi <walfred.tedeschi@intel.com>
gdb/ChangeLog:
* amd64-linux-tdep.c (features/i386/amd64-avx-mpx-linux.c):
New include.
(amd64_linux_core_read_description): Add case for
X86_XSTATE_AVX_MPX_MASK.
(_initialize_amd64_linux_tdep): Call initialize_tdesc_amd64_avx_mpx_linux.
* amd64-linux-tdep.h (tdesc_amd64_avx_mpx_linux): New definition.
* amd64-tdep.c (features/i386/amd64-avx-mpx.c): New include.
(amd64_target_description): Add case for X86_XSTATE_AVX_MPX_MASK.
(_initialize_amd64_tdep): Call initialize_tdesc_amd64_avx_mpx.
* common/x86-xstate.h (X86_XSTATE_MPX_MASK): Remove AVX bits.
(X86_XSTATE_AVX_MPX_MASK): New case.
* features/Makefile (i386/i386-avx-mpx, i386/i386-avx-mpx-linux)
(i386/amd64-avx-mpx, i386/amd64-avx-mpx-linux): New rules.
(i386/i386-avx-mpx-expedite, i386/i386-avx-mpx-linux-expedite)
(i386/amd64-avx-mpx-expedite, i386/amd64-avx-mpx-linux-expedite):
New expedites.
* i386-linux-tdep.c (features/i386/i386-avx-mpx-linux.c): New
include.
(i386_linux_core_read_description): Add case
X86_XSTATE_AVX_MPX_MASK.
(_initialize_i386_linux_tdep): Call
initialize_tdesc_i386_avx_mpx_linux.
* i386-linux-tdep.h (tdesc_i386_avx_mpx_linux): New include.
* i386-tdep.c (features/i386/i386-avx-mpx.c): New include.
(i386_target_description): Add case for X86_XSTATE_AVX_MPX_MASK.
* x86-linux-nat.c (x86_linux_read_description): Add case for
X86_XSTATE_AVX_MPX_MASK.
* features/i386/amd64-avx-mpx-linux.xml: New file.
* features/i386/i386-avx-mpx-linux.xml: New file.
* features/i386/i386-avx-mpx.xml: New file.
* features/i386/amd64-avx-mpx.xml: New file.
* features/i386/amd64-avx-mpx-linux.c: Generated.
* features/i386/amd64-avx-mpx.c: Generated.
* features/i386/i386-avx-mpx-linux.c: Generated.
* features/i386/i386-avx-mpx.c: Generated.
* regformats/i386/amd64-avx-mpx-linux.dat: Generated.
* regformats/i386/amd64-avx-mpx.dat: Generated.
* regformats/i386/i386-avx-mpx-linux.dat: Generated.
* regformats/i386/i386-avx-mpx.dat: Generated.
gdb/gdbserver/ChangeLog:
* Makefile.in (clean): Add removal for i386-avx-mpx.c,
i386-avx-mpx-linux.c, amd64-avx-mpx.c and amd64-avx-mpx-linux.c.
(i386-avx-mpx.c, i386-avx-mpx-linux.c, amd64-avx-mpx.c)
(amd64-avx-mpx-linux.c): New rules.
(amd64-avx-mpx-linux-ipa.o, i386-avx-mpx-linux-ipa.o): New rule.
* configure.srv (srv_i386_regobj): Add i386-avx-mpx.o.
(srv_i386_linux_regobj): Add i386-avx-mpx-linux.o.
(srv_amd64_regobj): Add amd64-avx-mpx.o.
(srv_amd64_linux_regobj): Add amd64-avx-mpx-linux.o.
(srv_i386_xmlfiles): Add i386/i386-avx-mpx.xml.
(srv_amd64_xmlfiles): Add i386/amd64-avx-mpx.xml.
(srv_i386_linux_xmlfiles): Add i386/i386-avx-mpx-linux.xml.
(srv_amd64_linux_xmlfiles): Add i386/amd64-avx-mpx-linux.xml.
(ipa_i386_linux_regobj): Add i386-avx-mpx-linux-ipa.o.
(ipa_amd64_linux_regobj): Add amd64-avx-mpx-linux-ipa.o.
* linux-x86-low.c (x86_linux_read_description): Add case for
X86_XSTATE_AVX_MPX_MASK.
(x86_get_ipa_tdesc_idx): Add cases for avx_mpx.
(initialize_low_arch): Call init_registers_amd64_avx_mpx_linux and
init_registers_i386_avx_mpx_linux.
* linux-i386-ipa.c (get_ipa_tdesc): Add case for avx_mpx.
(initialize_low_tracepoint): Call
init_registers_i386_avx_mpx_linux.
* linux-amd64-ipa.c (get_ipa_tdesc): Add case for avx_mpx.
(initialize_low_tracepoint): Call
init_registers_amd64_avx_mpx_linux.
* linux-x86-tdesc.h (X86_TDESC_AVX_MPX): New enum value.
(init_registers_amd64_avx_mpx_linux, tdesc_amd64_avx_mpx_linux)
(init_registers_i386_avx_mpx_linux, tdesc_i386_avx_mpx_linux): New
declarations.
The IBM z13 has new vector registers v0-v31 which are presented by the
Linux kernel as two additional register sets. This patch adds XML
descriptions and the respective autogenerated .c and .dat files for
S390 targets with this feature. Note that supported combinations
include targets with and without a transactional execution facility.
gdb/ChangeLog:
* features/s390-tevx-linux64.xml: New file.
* features/s390-vx-linux64.xml: New file.
* features/s390-vx.xml: New file.
* features/s390x-tevx-linux64.xml: New file.
* features/s390x-vx-linux64.xml: New file.
* features/Makefile (WHICH): Add s390-vx-linux64,
s390x-vx-linux64, s390-tevx-linux64, and s390x-tevx-linux64.
(s390-vx-linux64-expedite, s390-tevx-linux64-expedite)
(s390x-vx-linux64-expedite, s390x-tevx-linux64-expedite): New
macros.
* features/s390-tevx-linux64.c: New generated file.
* features/s390-vx-linux64.c: Likewise.
* features/s390x-tevx-linux64.c: Likewise.
* features/s390x-vx-linux64.c: Likewise.
* regformats/s390-tevx-linux64.dat: Likewise.
* regformats/s390-vx-linux64.dat: Likewise.
* regformats/s390x-tevx-linux64.dat: Likewise.
* regformats/s390x-vx-linux64.dat: Likewise.
gdb/doc/ChangeLog:
* gdb.texinfo (S/390 and System z Features): Describe new feature
"org.gnu.gdb.s390.vx".
Fix a typo in the expedited registers for s390-te-linux64.
gdb/ChangeLog:
* features/Makefile (s390-te-linux64-expedite): Replace
non-existant r14 and r15 by r14l and r15l, respectively.
* regformats/s390-te-linux64.dat: Regenerate.
The Microblaze PC register is called "rpc", not "pc", as can be seen
in microblaze-core.xml. Fix this, so GDBserver can find the register in
the regcache.
gdb/
2014-10-15 Ajit Agarwal <ajitkum@xilinx.com>
* features/Makefile (microblaze-expedite): Replace pc with rpc.
* regformats/microblaze-with-stack-protect.dat: Regenerate.
This makes it easier to rebuild all GDB's generated target description
C files.
It also clarifies the comments a bit. One might think we need a GDB
configured for the particular arquitecture (--target=foo). But a
build that includes support for the target description is sufficient.
(GDB rejects target descriptions that explicitly specify the
architecture, with an <architecture> element, if the architecture is
unknown.)
Tested that "make clean-cfiles" deletes all .c files under
src/gdb/features/, and that "make cfiles" generates them all without
error, and that diffing the newly generated C files against master
comes out an empty diff.
gdb/
2014-10-01 Pedro Alves <palves@redhat.com>
* features/Makefile: Update comments.
(XMLTOC): List all xml files we build C files from.
(clean-cfiles): New rule.
The only reason .dat files exist is for GBBserver to use them in its
build system.
A few .dat files are listed as targets for generation that shouldn't.
The target descriptions these files are built from aren't used by
GDBserver. They're fallback descriptions GDB itself has baked in.
Remove them from the list of .dat files to be generated, otherwise a
plain "make" under src/gdb/features/ generates new .dat files that
aren't even in the tree today.
gdb/
2014-10-01 Pedro Alves <palves@redhat.com>
* features/Makefile (WHICH): Remove arm-with-m,
arm-with-m-fpa-layout and arm-with-m-vfp-d16.
So that we can do "make clean all" to regenerate all the renerated
.dat files.
gdb/
2014-10-01 Pedro Alves <palves@redhat.com>
* features/Makefile (clean): New rule.
Prior to version MicroBlaze v8.10.a,EDK 13.1, XMD's gdbserver stub returned 57
registers in response to GDB's G request. Starting with version MicroBlaze
v8.10.a, EDK 13.1, XMD added the slr and shr register, for a count of 59
registers. This patch adds these registers to the expected G response. This patch
fixes the above problem for baremetal and also supports the backward compatibility.
ChangeLog:
2014-07-02 Ajit Agarwal <ajitkum@xilinx.com>
* microblaze-tdep.c (microblaze_register_names): Add
the rshr and rslr register names.
(microblaze_gdbarch_init): Use of tdesc_has_registers.
Use of tdesc_find_feature. Use of tdesc_data_alloc.
Use of tdesc_numbered_register. Use of
microblaze_register_g_packet_guesses. Use of
tdesc_use_registers. Use of set_gdbarch_register_type.
(microblaze_register_g_packet_guesses): New.
* microblaze-tdep.h (microblaze_reg_num): Add
field MICROBLAZE_SLR_REGNUM MICROBLAZE_SHR_REGNUM
MICROBLAZE_NUM_REGS and MICROBLAZE_NUM_CORE_REGS.
(microblaze_frame_cache): Use of MICROBLAZE_NUM_REGS.
* features/microblaze-core.xml: New file.
* features/microblaze-stack-protect.xml: New file.
* features/microblaze-with-stack-protect.c: New file.
* features/microblaze-with-stack-protect.xml: New file.
* features/microblaze.xml: New file.
* features/microblaze.c: New file.
* features/Makefile (microblaze-with-stack-protect): Add
microblaze-with-stack-protect microblaze and
microblaze-expedite.
* regformats/microblaze-with-stack-protect.dat: New file.
* regformats/microblaze.dat: New file.
* doc/gdb.texinfo (MicroBlaze Features): New.
Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
This patch adds support for the Intel(R) Advanced Vector
Extensions 512 (Intel(R) AVX-512) registers. Native and remote
debugging are covered by this patch.
Intel(R) AVX-512 is an extension to AVX to support 512-bit wide
SIMD registers in 64-bit mode (XMM0-XMM31, YMM0-YMM31, ZMM0-ZMM31).
The number of available registers in 32-bit mode is still 8
(XMM0-7, YMM0-7, ZMM0-7). The lower 256-bits of the ZMM registers
are aliased to the respective 256-bit YMM registers. The lower
128-bits are aliased to the respective 128-bit XMM registers.
There are also 8 new, dedicated mask registers (K0-K7) in both 32-bit
mode and 64-bit mode.
For more information please see
Intel(R) Developer Zone: Intel(R) AVX
http://software.intel.com/en-us/intel-isa-extensions#pid-16007-1495
Intel(R) Architecture Instruction Set Extensions Programming Reference:
http://software.intel.com/en-us/file/319433-017pdf
2014-04-24 Michael Sturm <michael.sturm@mintel.com>
Walfred Tedeschi <walfred.tedeschi@intel.com>
* amd64-linux-nat.c (amd64_linux_gregset32_reg_offset): Add
AVX512 registers.
(amd64_linux_read_description): Add code to handle AVX512 xstate
mask and return respective tdesc.
* amd64-linux-tdep.c: Include features/i386/amd64-avx512-linux.c
and features/i386/x32-avx512-linux.c.
(amd64_linux_gregset_reg_offset): Add AVX512 registers.
(amd64_linux_core_read_description): Add code to handle AVX512
xstate mask and return respective tdesc.
(_initialize_amd64_linux_tdep): Initialize AVX512 tdesc.
* amd64-linux-tdep.h (AMD64_LINUX_ORIG_RAX_REGNUM): Adjust regnum
calculation.
(AMD64_LINUX_NUM_REGS): Adjust to new number of registers.
(tdesc_amd64_avx512_linux): New prototype.
(tdesc_x32_avx512_linux): Likewise.
* amd64-tdep.c: Include features/i386/amd64-avx512.c and
features/i386/x32-avx512.c.
(amd64_ymm_avx512_names): New register names for pseudo
registers YMM16-31.
(amd64_ymmh_avx512_names): New register names for raw registers
YMMH16-31.
(amd64_k_names): New register names for K registers.
(amd64_zmmh_names): New register names for ZMM raw registers.
(amd64_zmm_names): New registers names for ZMM pseudo registers.
(amd64_xmm_avx512_names): New register names for XMM16-31
registers.
(amd64_pseudo_register_name): Add code to return AVX512 pseudo
registers.
(amd64_init_abi): Add code to intitialize AVX512 tdep variables
if feature is present.
(_initialize_amd64_tdep): Call AVX512 tdesc initializers.
* amd64-tdep.h (enum amd64_regnum): Add AVX512 registers.
(AMD64_NUM_REGS): Adjust to new number of registers.
* i386-linux-nat.c (GETXSTATEREGS_SUPPLIES): Extend range of
registers supplied via XSTATE by AVX512 registers.
(i386_linux_read_description): Add case for AVX512.
* i386-linux-tdep.c: Include i386-avx512-linux.c.
(i386_linux_gregset_reg_offset): Add AVX512 registers.
(i386_linux_core_read_description): Add case for AVX512.
(i386_linux_init_abi): Install supported register note section
for AVX512.
(_initialize_i386_linux_tdep): Add call to tdesc init function for
AVX512.
* i386-linux-tdep.h (I386_LINUX_NUM_REGS): Set number of
registers to be number of zmm7h + 1.
(tdesc_i386_avx512_linux): Add tdesc for AVX512 registers.
* i386-tdep.c: Include features/i386/i386-avx512.c.
(i386_zmm_names): Add ZMM pseudo register names array.
(i386_zmmh_names): Add ZMM raw register names array.
(i386_k_names): Add K raw register names array.
(num_lower_zmm_regs): Add constant for the number of lower ZMM
registers. AVX512 has 16 more ZMM registers than there are YMM
registers.
(i386_zmmh_regnum_p): Add function to look up register number of
ZMM raw registers.
(i386_zmm_regnum_p): Likewise for ZMM pseudo registers.
(i386_k_regnum_p): Likewise for K raw registers.
(i386_ymmh_avx512_regnum_p): Likewise for additional YMM raw
registers added by AVX512.
(i386_ymm_avx512_regnum_p): Likewise for additional YMM pseudo
registers added by AVX512.
(i386_xmm_avx512_regnum_p): Likewise for additional XMM registers
added by AVX512.
(i386_register_name): Add code to hide YMMH16-31 and ZMMH0-31.
(i386_pseudo_register_name): Add ZMM pseudo registers.
(i386_zmm_type): Construct and return vector registers type for ZMM
registers.
(i386_pseudo_register_type): Return appropriate type for YMM16-31,
ZMM0-31 pseudo registers and K registers.
(i386_pseudo_register_read_into_value): Add code to read K, ZMM
and YMM16-31 registers from register cache.
(i386_pseudo_register_write): Add code to write K, ZMM and
YMM16-31 registers.
(i386_register_reggroup_p): Add code to include/exclude AVX512
registers in/from respective register groups.
(i386_validate_tdesc_p): Handle AVX512 feature, add AVX512
registers if feature is present in xcr0.
(i386_gdbarch_init): Add code to initialize AVX512 feature
variables in tdep structure, wire in pseudo registers and call
initialize_tdesc_i386_avx512.
* i386-tdep.h (struct gdbarch_tdep): Add AVX512 related
variables.
(i386_regnum): Add AVX512 registers.
(I386_SSE_NUM_REGS): New define for number of SSE registers.
(I386_AVX_NUM_REGS): Likewise for AVX registers.
(I386_AVX512_NUM_REGS): Likewise for AVX512 registers.
(I386_MAX_REGISTER_SIZE): Change to 64 bytes, ZMM registers are
512 bits wide.
(i386_xmm_avx512_regnum_p): New prototype for register look up.
(i386_ymm_avx512_regnum_p): Likewise.
(i386_k_regnum_p): Likewise.
(i386_zmm_regnum_p): Likewise.
(i386_zmmh_regnum_p): Likewise.
* i387-tdep.c : Update year in copyright notice.
(xsave_ymm_avx512_offset): New table for YMM16-31 offsets in
XSAVE buffer.
(XSAVE_YMM_AVX512_ADDR): New macro.
(xsave_xmm_avx512_offset): New table for XMM16-31 offsets in
XSAVE buffer.
(XSAVE_XMM_AVX512_ADDR): New macro.
(xsave_avx512_k_offset): New table for K register offsets in
XSAVE buffer.
(XSAVE_AVX512_K_ADDR): New macro.
(xsave_avx512_zmm_h_offset): New table for ZMM register offsets
in XSAVE buffer.
(XSAVE_AVX512_ZMM_H_ADDR): New macro.
(i387_supply_xsave): Add code to supply AVX512 registers to XSAVE
buffer.
(i387_collect_xsave): Add code to collect AVX512 registers from
XSAVE buffer.
* i387-tdep.h (I387_NUM_XMM_AVX512_REGS): New define for number
of XMM16-31 registers.
(I387_NUM_K_REGS): New define for number of K registers.
(I387_K0_REGNUM): New define for K0 register number.
(I387_NUM_ZMMH_REGS): New define for number of ZMMH registers.
(I387_ZMM0H_REGNUM): New define for ZMM0H register number.
(I387_NUM_YMM_AVX512_REGS): New define for number of YMM16-31
registers.
(I387_YMM16H_REGNUM): New define for YMM16H register number.
(I387_XMM16_REGNUM): New define for XMM16 register number.
(I387_YMM0_REGNUM): New define for YMM0 register number.
(I387_KEND_REGNUM): New define for last K register number.
(I387_ZMMENDH_REGNUM): New define for last ZMMH register number.
(I387_YMMH_AVX512_END_REGNUM): New define for YMM31 register
number.
(I387_XMM_AVX512_END_REGNUM): New define for XMM31 register
number.
* common/i386-xstate.h: Add AVX 3.1 feature bits, mask and XSTATE
size.
* features/Makefile: Add AVX512 related files.
* features/i386/32bit-avx512.xml: New file.
* features/i386/64bit-avx512.xml: Likewise.
* features/i386/amd64-avx512-linux.c: Likewise.
* features/i386/amd64-avx512-linux.xml: Likewise.
* features/i386/amd64-avx512.c: Likewise.
* features/i386/amd64-avx512.xml: Likewise.
* features/i386/i386-avx512-linux.c: Likewise.
* features/i386/i386-avx512-linux.xml: Likewise.
* features/i386/i386-avx512.c: Likewise.
* features/i386/i386-avx512.xml: Likewise.
* features/i386/x32-avx512-linux.c: Likewise.
* features/i386/x32-avx512-linux.xml: Likewise.
* features/i386/x32-avx512.c: Likewise.
* features/i386/x32-avx512.xml: Likewise.
* regformats/i386/amd64-avx512-linux.dat: New file.
* regformats/i386/amd64-avx512.dat: Likewise.
* regformats/i386/i386-avx512-linux.dat: Likewise.
* regformats/i386/i386-avx512.dat: Likewise.
* regformats/i386/x32-avx512-linux.dat: Likewise.
* regformats/i386/x32-avx512.dat: Likewise.
* NEWS: Add note about new support for AVX512.
testsuite/
* Makefile.in (EXECUTABLES): Added i386-avx512.
* gdb.arch/i386-avx512.c: New file.
* gdb.arch/i386-avx512.exp: Likewise.
gdbserver/
* Makefile.in: Added rules to handle new files
i386-avx512.c i386-avx512-linux.c amd64-avx512.c
amd64-avx512-linux.c x32-avx512.c x32-avx512-linux.c.
* configure.srv (srv_i386_regobj): Add i386-avx512.o.
(srv_i386_linux_regobj): Add i386-avx512-linux.o.
(srv_amd64_regobj): Add amd64-avx512.o and x32-avx512.o.
(srv_amd64_linux_regobj): Add amd64-avx512-linux.o and
x32-avx512-linux.o.
(srv_i386_32bit_xmlfiles): Add i386/32bit-avx512.xml.
(srv_i386_64bit_xmlfiles): Add i386/64bit-avx512.xml.
(srv_amd64_xmlfiles): Add i386/amd64-avx512.xml and
i386/x32-avx512.xml.
(srv_i386_linux_xmlfiles): Add i386/i386-avx512-linux.xml.
(srv_amd64_linux_xmlfiles): Add i386/amd64-avx512-linux.xml and
i386/x32-avx512-linux.xml.
* i387-fp.c (num_avx512_k_registers): New constant for number
of K registers.
(num_avx512_zmmh_low_registers): New constant for number of
lower ZMM registers (0-15).
(num_avx512_zmmh_high_registers): New constant for number of
higher ZMM registers (16-31).
(num_avx512_ymmh_registers): New contant for number of higher
YMM registers (ymm16-31 added by avx521 on x86_64).
(num_avx512_xmm_registers): New constant for number of higher
XMM registers (xmm16-31 added by AVX512 on x86_64).
(struct i387_xsave): Add space for AVX512 registers.
(i387_cache_to_xsave): Change raw buffer size to 64 characters.
Add code to handle AVX512 registers.
(i387_xsave_to_cache): Add code to handle AVX512 registers.
* linux-x86-low.c (init_registers_amd64_avx512_linux): New
prototypei from generated file.
(tdesc_amd64_avx512_linux): Likewise.
(init_registers_x32_avx512_linux): Likewise.
(tdesc_x32_avx512_linux): Likewise.
(init_registers_i386_avx512_linux): Likewise.
(tdesc_i386_avx512_linux): Likewise.
(x86_64_regmap): Add AVX512 registers.
(x86_linux_read_description): Add code to handle AVX512 XSTATE
mask.
(initialize_low_arch): Add code to initialize AVX512 registers.
doc/
* gdb.texinfo (i386 Features): Add description of AVX512
registers.
Change-Id: Ifc4c08c76b85dbec18d02efdbe6182e851584438
Signed-off-by: Michael Sturm <michael.sturm@intel.com>
Alan Hayward
Joel Brobecker
Andrew Burgess
Edjunior Barbosa Machado
Franck Jullien
Yao Qi
Andreas Arnez
Walfred Tedeschi
John Baldwin
Michael Sturm
Anton Kolesov
Yan-Ting Lin
Ajit Kumar Agarwal
Pedro Alves
Michael Eager