Commit Graph

3 Commits

Author SHA1 Message Date
Stefan Kristiansson 018dc9bedf or1k: add missing l.msync, l.psync and l.psync instructions.
Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.

cpu/
	* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.

opcodes/
	* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
	* or1k-opinst.c: Regenerate.
2014-07-20 20:26:09 +03:00
Stefan Kristiansson 999b995ddc or1k: add support for l.swa/l.lwa atomic instructions
This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.

A couple of fixes to typos in nearby/related code are also snuck
into this.

cpu/
	* or1korbis.cpu (h-atomic-reserve): New hardware.
	(h-atomic-address): Likewise.
	(insn-opcode): Add opcodes for LWA and SWA.
	(atomic-reserve): New operand.
	(atomic-address): Likewise.
	(l-lwa, l-swa): New instructions.
	(l-lbs): Fix typo in comment.
	(store-insn): Clear atomic reserve on store to atomic-address.
	Fix register names in fmt field.

opcodes/
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opc.h: Likewise.
	* or1k-opinst.c: Likewise.
2014-05-08 09:02:50 +03:00
Christian Svensson 73589c9dbd Remove support for the (deprecated) openrisc and or32 configurations and replace
with support for the new or1k configuration.
2014-04-22 15:57:47 +01:00