Commit Graph

2949 Commits

Author SHA1 Message Date
Nick Clifton dd90581873 Place .shstrtab section after .symtab and .strtab, thus restoring monotonically increasing section offsets.
bfd
  * elf.c (assign_section_numbers): Assign number for the .shstrtab
  section after the symbol table and string table sections.

binutils
  * testsuite/binutils-all/readelf.s: Adjust expected ordering of
  sections.
  * testsuite/binutils-all/readelf.s-64: Likewise.

gas
  * testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected ordering
  of sections.
  * testsuite/gas/i386/x86-64-unwind.d: Likewise.
  * testsuite/gas/ia64/alias-ilp32.d: Likewise.
  * testsuite/gas/ia64/alias.d: Likewise.
  * testsuite/gas/ia64/group-1.d: Likewise.
  * testsuite/gas/ia64/group-2.d: Likewise.
  * testsuite/gas/ia64/secname-ilp32.d: Likewise.
  * testsuite/gas/ia64/secname.d: Likewise.
  * testsuite/gas/ia64/unwind-ilp32.d: Likewise.
  * testsuite/gas/ia64/unwind.d: Likewise.
  * testsuite/gas/ia64/xdata-ilp32.d: Likewise.
  * testsuite/gas/ia64/xdata.d: Likewise.
  * testsuite/gas/mmix/bspec-1.d: Likewise.
  * testsuite/gas/mmix/bspec-2.d: Likewise.
  * testsuite/gas/mmix/byte-1.d: Likewise.
  * testsuite/gas/mmix/loc-1.d: Likewise.
  * testsuite/gas/mmix/loc-2.d: Likewise.
  * testsuite/gas/mmix/loc-3.d: Likewise.
  * testsuite/gas/mmix/loc-4.d: Likewise.
  * testsuite/gas/mmix/loc-5.d: Likewise.
  * testsuite/gas/tic6x/scomm-directive-4.d: Likewise.

ld
  * testsuite/ld-alpha/tlsbin.rd: Adjust expected ordering of sections.
  * testsuite/ld-alpha/tlsbinr.rd: Likewise.
  * testsuite/ld-alpha/tlspic.rd: Likewise.
  * testsuite/ld-cris/libdso-2.d: Likewise.
  * testsuite/ld-i386/nogot1.d: Likewise.
  * testsuite/ld-i386/pr12718.d: Likewise.
  * testsuite/ld-i386/pr12921.d: Likewise.
  * testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsbin.rd: Likewise.
  * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsbin2.rd: Likewise.
  * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsbindesc.rd: Likewise.
  * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsdesc.rd: Likewise.
  * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsgdesc.rd: Likewise.
  * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
  * testsuite/ld-i386/tlsnopic.rd: Likewise.
  * testsuite/ld-i386/tlspic-nacl.rd: Likewise.
  * testsuite/ld-i386/tlspic.rd: Likewise.
  * testsuite/ld-i386/tlspic2-nacl.rd: Likewise.
  * testsuite/ld-i386/tlspic2.rd: Likewise.
  * testsuite/ld-ia64/tlsbin.rd: Likewise.
  * testsuite/ld-ia64/tlspic.rd: Likewise.
  * testsuite/ld-mips-elf/attr-gnu-4-10.d: Likewise.
  * testsuite/ld-mips-elf/attr-gnu-4-50.d: Likewise.
  * testsuite/ld-mips-elf/attr-gnu-4-60.d: Likewise.
  * testsuite/ld-mips-elf/attr-gnu-4-70.d: Likewise.
  * testsuite/ld-mmix/bspec1.d: Likewise.
  * testsuite/ld-mmix/bspec2.d: Likewise.
  * testsuite/ld-mmix/local1.d: Likewise.
  * testsuite/ld-mmix/local3.d: Likewise.
  * testsuite/ld-mmix/local5.d: Likewise.
  * testsuite/ld-mmix/local7.d: Likewise.
  * testsuite/ld-mmix/undef-3.d: Likewise.
  * testsuite/ld-powerpc/tlsexe.r: Likewise.
  * testsuite/ld-powerpc/tlsexe32.r: Likewise.
  * testsuite/ld-powerpc/tlsexetoc.r: Likewise.
  * testsuite/ld-powerpc/tlsso.r: Likewise.
  * testsuite/ld-powerpc/tlsso32.r: Likewise.
  * testsuite/ld-powerpc/tlstocso.r: Likewise.
  * testsuite/ld-s390/tlsbin.rd: Likewise.
  * testsuite/ld-s390/tlsbin_64.rd: Likewise.
  * testsuite/ld-s390/tlspic.rd: Likewise.
  * testsuite/ld-s390/tlspic_64.rd: Likewise.
  * testsuite/ld-sh/sh64/crange1.rd: Likewise.
  * testsuite/ld-sh/sh64/crange2.rd: Likewise.
  * testsuite/ld-sh/sh64/crange3-cmpct.rd: Likewise.
  * testsuite/ld-sh/sh64/crange3-media.rd: Likewise.
  * testsuite/ld-sh/sh64/crange3.rd: Likewise.
  * testsuite/ld-sh/sh64/crangerel1.rd: Likewise.
  * testsuite/ld-sh/sh64/crangerel2.rd: Likewise.
  * testsuite/ld-sh/tlsbin-2.d: Likewise.
  * testsuite/ld-sh/tlspic-2.d: Likewise.
  * testsuite/ld-sparc/gotop32.rd: Likewise.
  * testsuite/ld-sparc/gotop64.rd: Likewise.
  * testsuite/ld-sparc/tlssunbin32.rd: Likewise.
  * testsuite/ld-sparc/tlssunbin64.rd: Likewise.
  * testsuite/ld-sparc/tlssunnopic32.rd: Likewise.
  * testsuite/ld-sparc/tlssunnopic64.rd: Likewise.
  * testsuite/ld-sparc/tlssunpic32.rd: Likewise.
  * testsuite/ld-sparc/tlssunpic64.rd: Likewise.
  * testsuite/ld-tic6x/common.d: Likewise.
  * testsuite/ld-tic6x/shlib-1.rd: Likewise.
  * testsuite/ld-tic6x/shlib-1b.rd: Likewise.
  * testsuite/ld-tic6x/shlib-1r.rd: Likewise.
  * testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
  * testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
  * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
  * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
  * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
  * testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
  * testsuite/ld-tic6x/static-app-1.rd: Likewise.
  * testsuite/ld-tic6x/static-app-1b.rd: Likewise.
  * testsuite/ld-tic6x/static-app-1r.rd: Likewise.
  * testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
  * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
  * testsuite/ld-x86-64/ilp32-4.d: Likewise.
  * testsuite/ld-x86-64/nogot1.d: Likewise.
  * testsuite/ld-x86-64/pr12718.d: Likewise.
  * testsuite/ld-x86-64/pr12921.d: Likewise.
  * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
  * testsuite/ld-x86-64/split-by-file.rd: Likewise.
  * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlsbin.rd: Likewise.
  * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlsbin2.rd: Likewise.
  * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
  * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlsdesc.rd: Likewise.
  * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlsgdesc.rd: Likewise.
  * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlspic.rd: Likewise.
  * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise.
  * testsuite/ld-x86-64/tlspic2.rd: Likewise.
  * testsuite/ld-xtensa/tlsbin.rd: Likewise.
  * testsuite/ld-xtensa/tlspic.rd: Likewise.
2016-08-19 09:16:30 +01:00
Richard Sandiford dbd8770c86 [AArch64] Reject -0.0 as an 8-bit FP immediate
parse_aarch64_imm_float was accepting -0.0 even though that's not
a valid immediate for any instruction.  The FPIMM0 caller rejected
it, but the FPIMM one would silently treat it as -2.0.

This patch rejects -0.0 and adds testcases to illegal.[sd].

Before the patch, the final error emitted for illegal.s was:

        Error: cannot do 16-byte relocation

which was matched by:

        [^:]*:569: Error: .*

The error was reported against the last line of the file rather than
the instruction that required the reloc.  Adding more instructions
meant that the line number also changed.

Reporting against the wrong line isn't good from a QoI perspective
but isn't what I'm trying to fix here.  Until it's fixed, I thought
it would be better to adjust the match to be against an end-of-file
comment rather than against whatever the last instruction happens to be.

gas/
	* config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0.
	* testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l:
	Add tests for -0.0.  Add an end-of-file comment.
2016-08-11 09:14:45 +01:00
Nick Clifton b126985ec3 Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.
PR gas/20429
	* config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16
	registers are pushed.
	(do_vfp_nsyn_pop): Check that no more than 16 registers are
	popped.
	* testsuite/gas/arm/pr20429.s: New test.
	* testsuite/gas/arm/pr20429.d: New test driver.
	* testsuite/gas/arm/pr20429.1: Expected error output.
2016-08-05 11:26:13 +01:00
Nick Clifton 7ea12e5c3a Fix the generation of alignment frags in code sections for AArch64.
PR gas/20364
	* config/tc-aarch64.c (s_ltorg): Change the mapping state after
	aligning the frag.
	(aarch64_init): Treat rs_align frags in code sections as
	containing code, not data.
	* testsuite/gas/aarch64/pr20364.s: New test.
	* testsuite/gas/aarch64/pr20364.d: New test driver.
2016-08-05 10:37:57 +01:00
Jose E. Marchesi c88960d081 gas: avoid spurious failures in non-ELF targets in the SPARC testsuite.
Many of the existing sparc tests fail in non-ELF targets (coff and
a.out) due to spurious differences in the expected results:

- Unlike ELF, a.out text sections are aligned to 2**3 and padded
  accordingly.  The padding instruction is a `nop' (01 00 00 00).

- Likewise, coff text sections are also aligned to 2**3 and padded
  accordingly.  However, the padding instruction in these targets is an
  `illtrap 0' (00 00 00 00).

- Unlike ELF, a.out and coff binaries don't contain hardware
  capabilities bits that could be used by BFD to determine the opcodes
  architecture corresponding to the instructions encoded in the
  objects (v9, v9a, v9b, v9c, etc).  Consequently, in both a.out and
  coff tests we would need to pass proper `-m sparc:vXXX' options when
  invoking objdump before comparing results.

In order to fix these issues, the most obvious solution would be to have
three variants of .d files per impacted test.  For example, for save.d
we would have: save-elf.d, save-aout.d and save-coff.d.  Using the
`#source' directive, a single save.s file would provide the input for
all of them.  However, this approach has the following problems:

- The #target and #notarget .d directives are very limited: they use
  globs instead of regular expressions, and thus it is not possible (or
  too messy) to use them to discriminate between elf, coff and a.out
  sparc targets.

- It adds little or no value to have variants of all these tests for all
  the target types, and it would be a burden to maintain them.  Actually
  the features tested in the spuriously failing tests (relatively modern
  sparc instructions, registers and asis) are not really found in
  running coff or a.out sparc systems.

This patch changes sparc.exp so it will run these tests only in
ELF-targets, using the more standard `is_elf_format' from
binutils-common.exp instead of the ad-hoc (and less convenient, as it
must be called before _every_ single elf-only test) sparc_elf_setup.

Incidentally, the patch also fixes the #name entry for save-args.d.

Tested in sparc*-*-linux-gnu, sparc-aout and sparc-coff targets.

gas/ChangeLog:

2016-07-27  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
	ELF targets.
	Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
	pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
	ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
	sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
	targets.
	(sparc_elf_setup): Delete.
	* testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
	test's #name entry.
2016-07-29 00:17:04 -07:00
Maciej W. Rozycki 7bd374a44d MIPS/GAS: Implement microMIPS branch/jump compaction
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.

Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous.  This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has.  Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.

Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form.  For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction.  A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.

Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well.  We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded.  Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.

For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.

	gas/
	* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
	(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
	(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
	(get_append_method): Also return APPEND_ADD_COMPACT for
	microMIPS instructions.
	(find_altered_mips16_opcode): Exclude macros from matching.
	Factor code out...
	(find_altered_opcode): ... to this new function.
	(find_altered_micromips_opcode): New function.
	(frag_branch_delay_slot_size): Likewise.
	(append_insn): Handle microMIPS branch/jump compaction.
	(macro_start): Likewise.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(md_convert_frag): Likewise.
	* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
	for delay slot filling.
	* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
	delay slot filling.
	* testsuite/gas/mips/micromips-size-1.s: Likewise.
	* testsuite/gas/mips/micromips.l: Adjust line numbers.
	* testsuite/gas/mips/micromips-warn.l: Likewise.
	* testsuite/gas/mips/micromips-size-1.l: Likewise.
	* testsuite/gas/mips/micromips.d: Adjust padding.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips-insn32.d: Likewise.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips@beq.d: Update patterns for
	branch/jump compaction.
	* testsuite/gas/mips/micromips@bge.d: Likewise.
	* testsuite/gas/mips/micromips@bgeu.d: Likewise.
	* testsuite/gas/mips/micromips@blt.d: Likewise.
	* testsuite/gas/mips/micromips@bltu.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
	* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
	* testsuite/gas/mips/micromips@relax.d: Likewise.
	* testsuite/gas/mips/micromips@relax-at.d: Likewise.
	* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
	* testsuite/gas/mips/branch-extern-2.d: Likewise.
	* testsuite/gas/mips/branch-extern-4.d: Likewise.
	* testsuite/gas/mips/branch-section-2.d: Likewise.
	* testsuite/gas/mips/branch-section-4.d: Likewise.
	* testsuite/gas/mips/branch-weak-2.d: Likewise.
	* testsuite/gas/mips/branch-weak-5.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips-compact.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.

	ld/
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
	patterns for branch compaction.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
	Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
	"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
	"j".
2016-07-27 17:38:31 +01:00
Graham Markall db18dbabad Begin implementing ARC NPS-400 Accelerator instructions
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
        * arc-dis.c: Add new globals addrtypenames,
        addrtypenames_max, and addtypeunknown.
        (get_addrtype): New function.
        (print_insn_arc): Print colons and address types when
        required.
        * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
        define insert and extract functions for all address types.
        (arc_operands): Add operands for colon and all address
        types.
        * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
        * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
        insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
        * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
        * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
        insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.

include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
        ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
        ARC_NUM_ADDRTYPES.
        * opcode/arc.h: Add BMU to insn_class_t enum.
        * opcode/arc.h: Add PMU to insn_class_t enum.

gas     * config/tc-arc.c: Add new global arc_addrtype_hash.
        Define O_colon and O_addrtype.
        (debug_exp): Add O_colon and O_addrtype.
        (tokenize_arguments): Handle colon and address type
        tokens.
        (declare_addrtype): New function.
        (md_begin): Initialise arc_addrtype_hash.
        (arc_parse_name): Add lookup of address types.
	(assemble_insn): Handle colons and address types by
        ignoring them.
        * testsuite/gas/arc/nps400-8.s: New file.
        * testsuite/gas/arc/nps400-8.d: New file.
        * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
        * testsuite/gas/arc/nps400-8.d: Add expected PMU
        instruction output.
2016-07-27 15:57:18 +01:00
Maciej W. Rozycki 8484fb7587 MIPS/GAS: Respect the `insn32' mode in branch relaxation
Complement:

commit 833794fc12
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date:   Tue Jun 25 18:02:34 2013 +0000

<https://sourceware.org/ml/binutils/2013-06/msg00104.html>, ("microMIPS
insn32 mode support"), and fix an issue with microMIPS branch relaxation
producing 16-bit instructions in the `insn32' mode.  Use equivalent
32-bit instruction sequences.

	gas/
	* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag.
	(RELAX_MICROMIPS_INSN32): New macro.
	(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
	(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32)
	(RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16)
	(RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32)
	(RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32):
	Shift bits.
	(append_insn): Record `mips_opts.insn32' with relaxed microMIPS
	branches.
	(relaxed_micromips_32bit_branch_length): Handle the `insn32'
	mode.
	(md_convert_frag): Likewise.
	* testsuite/gas/mips/micromips-branch-relax.s: Add `insn32'
	conditionals.
	* testsuite/gas/mips/micromips-branch-relax.l: Update line
	numbers accordingly.
	* testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise.
	* testsuite/gas/mips/micromips-branch-relax-insn32.d: New test.
	* testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New
	test.
	* testsuite/gas/mips/micromips-branch-relax-insn32.l: New
	stderr output.
	* testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New
	stderr output.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-26 20:00:49 +01:00
Claudiu Zissulescu 37fd5ef3ec Add support to the ARC disassembler for selecting instruction classes.
gas	* testsuite/gas/arc/dsp.d: New file.
	* testsuite/gas/arc/dsp.s: Likewise.
	* testsuite/gas/arc/fpu.d: Likewise.
	* testsuite/gas/arc/fpu.s: Likewise.
	* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
	* testsuite/gas/arc/ext3op.d: Likewise.
	* testsuite/gas/arc/tdpfp.d: Likewise.
	* testsuite/gas/arc/tfpuda.d: Likewise.

opcodes	* arc-dis.c (skipclass): New structure.
	(decodelist): New variable.
	(is_compatible_p): New function.
	(new_element): Likewise.
	(skip_class_p): Likewise.
	(find_format_from_table): Use skip_class_p function.
	(find_format): Decode first the extension instructions.
	(print_insn_arc): Select either ARCEM or ARCHS based on elf
	e_flags.
	(parse_option): New function.
	(parse_disassembler_options): Likewise.
	(print_arc_disassembler_options): Likewise.
	(print_insn_arc): Use parse_disassembler_options function.  Proper
	select ARCv2 cpu variant.
	* disassemble.c (disassembler_usage): Add ARC disassembler
	options.

binutils* doc/binutils.texi (objdump): Add ARC disassembler options.
	* testsuite/binutils-all/arc/dsp.s: New file.
	* testsuite/binutils-all/arc/objdump.exp: Likewise.

include	* dis-asm.h: Declare print_arc_disassembler_options.
2016-07-20 17:08:07 +01:00
Maciej W. Rozycki a6ebf6169a MIPS: Convert cross-mode BAL to JALX
Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX,
similarly to how JAL instructions are converted.

	bfd/
	* elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode
	BAL to JALX.
	(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a
	corresponding error message.

	gas/
	* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
	Adjust comments for BAL to JALX linker conversion.
	(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
	* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
	expected.
	* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
	* testsuite/gas/mips/branch-local-4.d: New test.
	* testsuite/gas/mips/branch-local-n32-4.d: New test.
	* testsuite/gas/mips/branch-local-n64-4.d: New test.
	* testsuite/gas/mips/branch-addend.d: New test.
	* testsuite/gas/mips/branch-addend-n32.d: New test.
	* testsuite/gas/mips/branch-addend-n64.d: New test.
	* testsuite/gas/mips/branch-local-4.s: New test source.
	* testsuite/gas/mips/branch-addend.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/unaligned-branch-2.d: Update error
	messages expected.
	* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise.
	* testsuite/ld-mips-elf/bal-jalx-addend.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-local.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-pic.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-3.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
	* testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test
	source.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test
	source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19 16:22:53 +01:00
Maciej W. Rozycki 9d862524f6 MIPS: Verify the ISA mode and alignment of branch and jump targets
Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code.  Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.

Also make jump target's alignment verification consistent with that for
branches.

This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only.  These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).

Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes.  It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.

References:

[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
    Compatibility", p. 533

[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
    Compatibility", p. 623

	bfd/
	* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
	R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
	(branch_reloc_p): New function.
	(mips_elf_calculate_relocation): Handle ISA mode determination
	for relocations against section symbols, against absolute
	symbols and absolute relocations.  Also set `*cross_mode_jump_p'
	for branches.
	<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
	checks for weak undefined symbols.  Also check target alignment
	within the same ISA mode.
	<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
	in the alignment check.
	<R_MICROMIPS_PC7_S1>: Add an alignment check.
	<R_MICROMIPS_PC10_S1>: Likewise.
	<R_MICROMIPS_PC16_S1>: Likewise.
	(mips_elf_perform_relocation): Report a failure for unsupported
	same-mode JALX instructions and cross-mode branches.
	(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
	error messages for jumps to misaligned addresses.

	gas/
	* config/tc-mips.c (mips_force_relocation): Also retain branch
	relocations against MIPS16 and microMIPS symbols.
	(fix_bad_cross_mode_jump_p): New function.
	(fix_bad_same_mode_jalx_p): Likewise.
	(fix_bad_misaligned_jump_p): Likewise.
	(fix_bad_cross_mode_branch_p): Likewise.
	(fix_bad_misaligned_branch_p): Likewise.
	(fix_validate_branch): Likewise.
	(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
	<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
	etc.  Verify the ISA mode and alignment of the jump target.
	<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
	with a call to `fix_validate_branch'.
	<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
	<BFD_RELOC_16_PCREL_S2>: Likewise.
	<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
	<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
	Verify the ISA mode and alignment of the branch target.
	(md_convert_frag): Verify the ISA mode and alignment of resolved
	MIPS16 branch targets.
	* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
	branch targets with `.insn'.
	* testsuite/gas/mips/branch-misc-5.s: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
	accordingly.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-relax.s: Annotate
	non-instruction branch target with `.insn'.
	* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
	with external symbols.
	* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips.d: Likewise.
	* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
	targets with `.insn'.
	* testsuite/gas/mips/mips16.d: Update accordingly.
	* testsuite/gas/mips/mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
	branch target with `.insn'.
	* testsuite/gas/mips/relax-swap3.s: Likewise.
	* testsuite/gas/mips/branch-local-2.l: New list test.
	* testsuite/gas/mips/branch-local-3.l: New list test.
	* testsuite/gas/mips/branch-local-n32-2.l: New list test.
	* testsuite/gas/mips/branch-local-n32-3.l: New list test.
	* testsuite/gas/mips/branch-local-n64-2.l: New list test.
	* testsuite/gas/mips/branch-local-n64-3.l: New list test.
	* testsuite/gas/mips/unaligned-jump-1.l: New list test.
	* testsuite/gas/mips/unaligned-jump-2.l: New list test.
	* testsuite/gas/mips/unaligned-jump-3.d: New test.
	* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
	* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
	* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
	* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
	test.
	* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
	test.
	* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
	* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
	* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
	test.
	* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
	test.
	* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
	* testsuite/gas/mips/branch-local-2.s: New test source.
	* testsuite/gas/mips/branch-local-3.s: New test source.
	* testsuite/gas/mips/branch-local-n32-2.s: New test source.
	* testsuite/gas/mips/branch-local-n32-3.s: New test source.
	* testsuite/gas/mips/branch-local-n64-2.s: New test source.
	* testsuite/gas/mips/branch-local-n64-3.s: New test source.
	* testsuite/gas/mips/unaligned-jump-1.s: New test source.
	* testsuite/gas/mips/unaligned-jump-2.s: New test source.
	* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
	* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
	* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-1.s: New test source.
	* testsuite/gas/mips/unaligned-branch-2.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
	* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
	expected.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
	Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
	Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
	* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
	microMIPS BAL and MIPS16 instructions.
	* testsuite/ld-mips-elf/undefweak-overflow.d: Update
	accordingly.
	* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19 14:46:30 +01:00
Maciej W. Rozycki b416ba9b50 MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbols
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead.  Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:

$ cat test.s
	.text
	.globl	foo
	.ent	foo
foo:
	b	bar
	.end	foo

	.set	bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$

With the original reference retained the source can now be assembled and
linked successfully:

$ as -EB -32 -o test.o test.s
$ objdump -dr test.o

test.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	1000ffff 	b	0 <foo>
			0: R_MIPS_PC16	bar
   4:	00000000 	nop
	...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test

test:     file format elf32-tradbigmips

Disassembly of section .text:

12340000 <foo>:
12340000:	1000159d 	b	12345678 <bar>
12340004:	00000000 	nop
	...
$

For simplicity always retain the original symbol reference, even if it
would indeed fit.

Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references.  This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.

Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.

Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.

	gas/
	* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
	(mips_force_relocation_abs): New prototype.
	* config/tc-mips.c (mips_force_relocation_abs): New function.
	* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/branch-absolute-addend.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
	test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips-elf.exp: Run
	`branch-absolute-addend', `mips16-branch-absolute',
	`mips16-branch-absolute-addend' and
	`micromips-branch-absolute-addend'.
2016-07-14 20:11:03 +01:00
Maciej W. Rozycki 96e9ba5fbb MIPS/GAS: Keep the ISA bit in the addend of branch relocations
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets.  It has been
there since microMIPS support has been added, with:

commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Sun Jul 24 14:20:15 2011 +0000

<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:

$ cat test.s
	.text
	.set	mips16
foo:
	b	bar

	.set	bar, 0x1235
	.align	4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o

test.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	f000 1000 	b	4 <foo+0x4>
			0: R_MIPS16_PC16_S1	*ABS*+0x1230
	...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$

This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.

Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:

$ objdump -dr fixed.o

fixed.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	f000 1000 	b	4 <foo+0x4>
			0: R_MIPS16_PC16_S1	*ABS*+0x1231
	...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$

Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.

	gas/
	* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
	<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
	<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
	addend calculated.
	* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
	in `bar', export `foo'.
	* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
	accordingly.
	* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
	Likewise.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
	test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
	from `mips16-branch-absolute' and
	`mips16-branch-absolute-addend', referred indirectly only.
2016-07-14 20:08:59 +01:00
Maciej W. Rozycki 0c11728627 BFD: Let targets handle relocations against absolute symbols
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend.  This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.

As an example assembling this program:

$ cat test.s
	.text
foo:
	b	bar
	b	baz

	.set	bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s

produces this binary code:

$ objdump -dr test-o32.o test-n32.o

test-o32.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	10000000 	b	4 <foo+0x4>
			0: R_MIPS_PC16	*ABS*
   4:	00000000 	nop
   8:	1000ffff 	b	8 <foo+0x8>
			8: R_MIPS_PC16	baz
   c:	00000000 	nop

test-n32.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	10000000 	b	4 <foo+0x4>
			0: R_MIPS_PC16	*ABS*+0x1230
   4:	00000000 	nop
   8:	10000000 	b	c <foo+0xc>
			8: R_MIPS_PC16	baz-0x4
   c:	00000000 	nop
$

where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word.  In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.

Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise.  This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.

Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function.  The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.

With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:

$ objdump -dr fixed-o32.o

fixed-o32.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	1000048c 	b	1234 <bar>
			0: R_MIPS_PC16	*ABS*
   4:	00000000 	nop
   8:	1000ffff 	b	8 <foo+0x8>
			8: R_MIPS_PC16	baz
   c:	00000000 	nop
$

Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used.  Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.

	bfd/
	* reloc.c (bfd_perform_relocation): Try the `howto' handler
	first with relocations against absolute symbols.
	(bfd_install_relocation): Likewise.

	gas/
	* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
	* testsuite/gas/mips/branch-absolute.d: New test.
	* testsuite/gas/mips/branch-absolute-n32.d: New test.
	* testsuite/gas/mips/branch-absolute-n64.d: New test.
	* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
	* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
	test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
	test.
	* testsuite/gas/mips/micromips-branch-absolute.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
	test.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
	test.
	* testsuite/gas/mips/branch-absolute.s: New test source.
	* testsuite/gas/mips/branch-absolute-addend.s: New test source.
	* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
	source.
	* testsuite/gas/mips/micromips-branch-absolute.s: New test
	source.
	* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
	test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/branch-absolute.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
	New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
	New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
	from `branch-absolute-addend' and
	`micromips-branch-absolute-addend', referred indirectly only.
2016-07-14 20:06:37 +01:00
Maciej W. Rozycki 92281a5b06 MIPS/opcodes: Address issues with NAL disassembly
Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c95 ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e ("Add in a JALRC
alias and fix the NAL instruction.").  As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.

The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':

$ cat test.s
	.text
foo:
	nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o

nal.o:     file format elf32-tradbigmips

Disassembly of section .text:
00000000 <foo> 04100000 	0x4100000
	...
$

This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.

Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code.  Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people.  This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code.  Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.

Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.

Add a suitable test case to the GAS test suite.  While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
	annotation from the "nal" entry and reorder it beyond "bltzal".

	gas/
	* testsuite/gas/mips/nal-1.d: New test.
	* testsuite/gas/mips/mipsr6@nal-1.d: New test.
	* testsuite/gas/mips/nal-2.d: New test.
	* testsuite/gas/mips/mipsr6@nal-2.d: New test.
	* testsuite/gas/mips/nal.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-13 17:42:43 +01:00
Jose E. Marchesi 6e7ced37e7 opcodes,gas: support for the ldtxa SPARC instructions.
This patch adds support for the LDTXA instructions, along with the
corresponding ASIs.  Tests for GAS are included.

opcodes/ChangeLog:

2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (ldtxa): New macro.
	(sparc_opcodes): Use the macro defined above to add entries for
	the LDTXA instructions.
	(asi_table): Add the ASI_TWINX_* asis used in the LDTXA
	instruction.

gas/ChangeLog:

2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/sparc/ldtxa.s: New file.
	* testsuite/gas/sparc/ldtxa.d: Likewise.
	* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
2016-07-13 16:05:40 +02:00
Jan Beulich 33d0ab9548 x86: fix register check in check_qword_reg()
A missing 'r' (or wrong 'e') register prefix needs to be complained
about if the template allows for a 64-bit register, not a 32-bit one.
I assume this was a copy-and-paste type of mistake
(from check_long_reg()).
2016-07-05 11:14:51 +02:00
Maciej W. Rozycki fcedb9f3ca MIPS/GAS/testsuite: Remove remnants of a.out/ECOFF support
Complement:

commit 16e5e222b6
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Sat Jun 22 16:57:42 2013 +0000

<https://sourceware.org/ml/binutils/2013-06/msg00195.html>, ("Make
gas/mips/mips.exp ELF-only"), and remove the remaining stale ECOFF test
dumps and pieces of a.out/ECOFF support in relocation match patterns.

	gas/
	* testsuite/gas/mips/ecoff@ld.d: Remove test.
	* testsuite/gas/mips/ecoff@ld-forward.d: Remove test.
	* testsuite/gas/mips/ecoff@ld-zero-3.d: Remove test.
	* testsuite/gas/mips/ecoff@sd.d: Remove test.
	* testsuite/gas/mips/ecoff@sd-forward.d: Remove test.
	* testsuite/gas/mips/beq.d: Remove a.out and ECOFF support from
	reloc patterns.
	* testsuite/gas/mips/mipsr6@beq.d: Likewise.
	* testsuite/gas/mips/bge.d: Likewise.
	* testsuite/gas/mips/mipsr6@bge.d: Likewise.
	* testsuite/gas/mips/bgeu.d: Likewise.
	* testsuite/gas/mips/mipsr6@bgeu.d: Likewise.
	* testsuite/gas/mips/blt.d: Likewise.
	* testsuite/gas/mips/mipsr6@blt.d: Likewise.
	* testsuite/gas/mips/bltu.d: Likewise.
	* testsuite/gas/mips/mipsr6@bltu.d: Likewise.
	* testsuite/gas/mips/branch-likely.d: Likewise.
	* testsuite/gas/mips/la.d: Likewise.
	* testsuite/gas/mips/lb.d: Likewise.
	* testsuite/gas/mips/lifloat.d: Likewise.
	* testsuite/gas/mips/sb.d: Likewise.
	* testsuite/gas/mips/uld.d: Likewise.
	* testsuite/gas/mips/ulh.d: Likewise.
	* testsuite/gas/mips/ulw.d: Likewise.
	* testsuite/gas/mips/usd.d: Likewise.
	* testsuite/gas/mips/ush.d: Likewise.
	* testsuite/gas/mips/usw.d: Likewise.
2016-07-02 23:41:31 +01:00
Maciej W. Rozycki 00437d3b6f MIPS/GAS/testsuite: Split `branch-misc-2' tests into two
Move `branch-misc-2' tests for non locally-defined-global symbols into
separate files.  These tests have been introduced with:

commit 6f171daac9
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Thu Dec 12 04:40:22 2002 +0000

<https://sourceware.org/ml/binutils/2002-11/msg00631.html>, ("mips:
branches to external labels are broken"), and:

commit d17b874b6c
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Wed Mar 12 23:07:22 2003 +0000

<https://sourceware.org/ml/binutils/2003-03/msg00136.html>, ("On
resolving the MIPS gas branch reloc issue"), while the test case served
a different purpose.  With the original intent of the test case brought
back with:

commit bad36eacda
Author: Daniel Jacobowitz <drow@false.org>
Date:   Wed Nov 23 14:04:18 2005 +0000

<https://sourceware.org/ml/binutils/2005-11/msg00324.html>,
("R_MIPS_PC16, again"), these stand in the way for linker testing.

	gas/
	* testsuite/gas/mips/branch-misc-2.s: Move non
	locally-defined-global symbol tests...
	* testsuite/gas/mips/branch-misc-5.s: ... to this new test.
	* testsuite/gas/mips/branch-misc-2.d: Update accordingly.
	* testsuite/gas/mips/branch-misc-2-64.d: Likewise.
	* testsuite/gas/mips/branch-misc-2pic.d: Likewise.
	* testsuite/gas/mips/branch-misc-2pic-64.d: Likewise.
	* testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise.
	* testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-2.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
	* testsuite/gas/mips/branch-misc-5.d: New test.
	* testsuite/gas/mips/branch-misc-5pic.d: New test.
	* testsuite/gas/mips/branch-misc-5-64.d: New test.
	* testsuite/gas/mips/branch-misc-5pic-64.d: New test.
	* testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test.
	* testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-5.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-5pic.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-02 23:10:10 +01:00
Maciej W. Rozycki f26c9c2eaf MIPS/GAS/testsuite: Reenable disabled external BEQ tests
Complement:

commit bad36eacda
Author: Daniel Jacobowitz <drow@false.org>
Date:   Wed Nov 23 14:04:18 2005 +0000

<https://sourceware.org/ml/binutils/2005-11/msg00324.html>,
("R_MIPS_PC16, again"), and reenable external BEQ tests, the remaining
subset missed from the set of branch tests previously disabled with:

commit 6f171daac9
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Thu Dec 12 04:40:22 2002 +0000

<https://sourceware.org/ml/binutils/2002-11/msg00631.html>, ("mips:
branches to external labels are broken").

	gas/
	* testsuite/gas/mips/beq.s: Uncomment branches to undefined
	symbols.
	* testsuite/gas/mips/beq.d: Update accordingly.
	* testsuite/gas/mips/mipsr6@beq.d: Likewise.
	* testsuite/gas/mips/micromips@beq.d: Likewise.
2016-07-02 22:38:06 +01:00
Maciej W. Rozycki d7f20d660a MIPS/GAS/testsuite: Restrict 64-bit `branch-mips' tests to NewABI targets
... removing numerous `mips-sgi-irix5' failures.

	gas/
	* testsuite/gas/mips/mips.exp: Restrict 64-bit `branch-mips'
	tests to NewABI targets.
2016-07-02 22:15:43 +01:00
Maciej W. Rozycki e51af1571f MIPS/GAS/testsuite: Group `branch-misc' tests together
gas/
	* testsuite/gas/mips/mips.exp: Group `branch-misc' tests
	together.
2016-07-02 22:11:36 +01:00
Szabolcs Nagy 93d8990cba [AArch64] Fix +nofp16 handling
Feature flag handling was not perfect, +nofp16 disabled fp
instructions too.

New feature flag macros were added to check features with multiple
bits set (matters for FP_F16 and SIMD_F16 opcode feature tests).
The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should
use one of the AARCH64_CPU_HAS_* macros.  AARCH64_CPU_HAS_FEATURE
now checks all feature bits.

The aarch64_features table now contains the dependencies as
a separate field (so when the feature is enabled all dependencies
are enabled and when it is disabled everything that depends on it
is disabled).

Note that armv8-a+foo+nofoo is not equivalent to armv8-a if
+foo turns on dependent features that nofoo does not turn off.

gas/
	* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
	require field.
	(aarch64_features): Initialize require fields.
	(aarch64_parse_features): Handle dependencies.
	(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
	(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
	* testsuite/gas/aarch64/illegal-nofp16.s: New.
	* testsuite/gas/aarch64/illegal-nofp16.l: New.
	* testsuite/gas/aarch64/illegal-nofp16.d: New.

include/
	* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
	(AARCH64_CPU_HAS_ANY_FEATURES): New.
	(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
	(AARCH64_OPCODE_HAS_FEATURE): Remove.
2016-07-01 16:50:59 +01:00
Jan Beulich 248feb2f9e x86-64/MPX: relax no-RIP-relative-addressing testcase
... for COFF targets.
2016-07-01 11:17:30 +02:00
Jan Beulich 8178be5b0c x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
Additionally warn about scaling factors other than 1 for the latter
two, as those get ignored by the hardware.
2016-07-01 09:07:15 +02:00
Jan Beulich 327e8c421b x86/MPX: fix address size handling
While address overrides are ignored in 64-bit mode (and hence shouldn't
really result in an error, but upon v1 converting this to a warning I
was told otherwise), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt. (The
added test case at once also checks that bndc{l,n,u} won't accept
16-bit register operands.)
2016-07-01 09:06:16 +02:00
Jan Beulich 83b16ac694 x86/Intel: don't accept bogus instructions
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
2016-07-01 09:03:02 +02:00
Jan Beulich c07315e0c6 x86: allow suffix-less movzw and 64-bit movzb
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
2016-07-01 09:01:41 +02:00
Jan Beulich 8325cc6398 x86/Intel: fix operand checking for MOVSD
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
2016-07-01 08:56:13 +02:00
Matthew Fortune 99e7978bd2 MIPS16/GAS: Fix delay slot filling across frags
Fix an assertion failure like:

test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.

triggered by assembling MIPS16 code like:

hello:
	addiu	$4, $4, 4
	jr	$31

with the generation of a listing file enabled, e.g.:

$ as -mips16 -O2 -aln=test.lst

The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag.  It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.

This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.

This effectively complements:

commit 464ab0e55a
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date:   Mon Aug 6 20:33:00 2012 +0000

<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.

The assertion itself was introduced with:

commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Wed Mar 9 09:17:02 2005 +0000

<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.

	gas/
	* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
	case MIPS16 handling.
	* testsuite/gas/mips/branch-swap-3.d: New test.
	* testsuite/gas/mips/branch-swap-4.d: New test.
	* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
	* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
	* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
	* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
	* testsuite/gas/mips/branch-swap-3.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30 15:11:23 +01:00
Maciej W. Rozycki 93a24ba79b PR gas/20312: Do not pad sections to alignment on failed assembly
Correct a regression from commit 85024cd8bc ("Run write_object_file
after errors") causing unsuccessful assembly, which may be due to any
reason, such as supplying a valid source like this:

	.text
	.byte	0
	.err

to terminate with an assertion failure like:

test.s: Assembler messages:
test.s:3: Error: .err encountered
../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg
../as-new: Please report this bug.

on targets whose default text section alignment is above 0, typically
RISC machines.

This is due to an attempt to set last text section's frag alignment to
0, requested from `subsegs_finish_section' where `frag_align_code
(alignment, 0)' is called with `alignment' set to 0 rather than the
section alignment if `had_errors' has returned true.  The call to
`subsegs_finish_section' is made from `subsegs_finish' from
`write_object_file' at unsuccessful completion, which previously wasn't
made.

Always set last section's frag alignment from the section alignment
then, forcing no section padding instead if completing unsuccessfully,
so that in that case alignment padding is still suppressed from any
listing generated, fixing assertion failures for these targets:

alpha-linuxecoff  -FAIL: all pr20312
arm-aout  -FAIL: all pr20312
mips-freebsd  -FAIL: all pr20312
mips-img-linux  -FAIL: all pr20312
mips-linux  -FAIL: all pr20312
mips-mti-linux  -FAIL: all pr20312
mips-netbsd  -FAIL: all pr20312
mips-sgi-irix5  -FAIL: all pr20312
mips-sgi-irix6  -FAIL: all pr20312
mips-vxworks  -FAIL: all pr20312
mips64-freebsd  -FAIL: all pr20312
mips64-img-linux  -FAIL: all pr20312
mips64-linux  -FAIL: all pr20312
mips64-mti-linux  -FAIL: all pr20312
mips64-openbsd  -FAIL: all pr20312
mips64el-freebsd  -FAIL: all pr20312
mips64el-img-linux  -FAIL: all pr20312
mips64el-linux  -FAIL: all pr20312
mips64el-mti-linux  -FAIL: all pr20312
mips64el-openbsd  -FAIL: all pr20312
mipsel-freebsd  -FAIL: all pr20312
mipsel-img-linux  -FAIL: all pr20312
mipsel-linux  -FAIL: all pr20312
mipsel-mti-linux  -FAIL: all pr20312
mipsel-netbsd  -FAIL: all pr20312
mipsel-vxworks  -FAIL: all pr20312
mipsisa32-linux  -FAIL: all pr20312
mipsisa32el-linux  -FAIL: all pr20312
mipsisa64-linux  -FAIL: all pr20312
mipsisa64el-linux  -FAIL: all pr20312
sh-pe  -FAIL: all pr20312
sparc-aout  -FAIL: all pr20312

	gas/
	PR gas/20312
	* write.c (subsegs_finish_section): Force no section padding to
	alignment on failed assembly, always set last frag's alignment
	from section.
	* testsuite/gas/all/pr20312.l: New list test.
	* testsuite/gas/all/pr20312.s: New test source.
	* testsuite/gas/all/gas.exp: Run the new test
2016-06-30 15:11:23 +01:00
Matthew Wahab 534dbe460e [ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.
GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a
when assembling NEON instructions. The patch corrects this, making
-march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions
introduced with ARMv8.1-A.

include/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
	of enabled FPU features.

gas/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* testsuite/gas/arm/armv8_2+rdma.d: New.
2016-06-30 10:46:51 +01:00
Maciej W. Rozycki eb9bb5b4ec Use `supports_gnu_unique' with the `unique_symbol' and `type' tests
Complement commit a43942db49 ("LD/ELF: Unify STB_GNU_UNIQUE handling")
and use `supports_gnu_unique' with the `unique_symbol' and `type' tests,
fixing failures like:

.../binutils/testsuite/binutils-all/unique.s: Assembler messages:
.../binutils/testsuite/binutils-all/unique.s:2: Error: symbol type "gnu_unique_object" is supported only by GNU targets

ERROR: .../binutils/testsuite/binutils-all/unique.s: assembly failed
UNRESOLVED: ar unique symbol in archive
.../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o
Executing on host: .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o   (timeout = 300)
.../binutils/ar: tmpdir/unique.o: No such file or directory

FAIL: ar unique symbol in archive

and:

.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg

../as-new: Please report this bug.

.../gas/testsuite/../../binutils/readelf -s dump.o | grep "1 *\[FIONTCU\]" > dump.out
Executing on host: sh -c {.../gas/testsuite/../../binutils/readelf -s dump.o >readelf.out 2>gas.stderr}  /dev/null  (timeout = 300)
readelf: Error: dump.o: Failed to read file's magic number
FAIL: elf type list

on MIPS/FreeBSD targets:

mips-freebsd  -FAIL: ar unique symbol in archive
mips-freebsd  -FAIL: elf type list
mips64-freebsd  -FAIL: ar unique symbol in archive
mips64-freebsd  -FAIL: elf type list
mips64el-freebsd  -FAIL: ar unique symbol in archive
mips64el-freebsd  -FAIL: elf type list
mipsel-freebsd  -FAIL: ar unique symbol in archive
mipsel-freebsd  -FAIL: elf type list

	binutils/
	* testsuite/binutils-all/ar.exp: Use `supports_gnu_unique' with
	the `unique_symbol' test.

	gas/
	* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
	`type' test.
2016-06-28 13:54:00 +01:00
Alan Modra d48796b505 Fix new testcase for hppa64
Anything in first column is a label on hppa64.

	PR gas/20247
	* testsuite/gas/elf/section11.s: Don't start directives in first column.
2016-06-28 19:09:11 +09:30
Richard Sandiford dab26bf4e7 [AArch64] Make register indices be full 64-bit values
aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked.  This meant large invalid indices could be silently
truncated to smaller valid indices.

The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index.  I went for the latter for two
reasons:

      - Doing the range checking in operand_general_constraint_met_p
        seems structurally cleaner than doing it while parsing.

      - The bitfields didn't really buy us anything.  The imm field
        of the union is already 128 bits, so we can use a full int64_t
        index without growing the structure.

The patch also adds missing range checks for the elements in a register
list index.

include/
	* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.

opcodes/
	* aarch64-opc.c (operand_general_constraint_met_p): Check the
	range of ldst_elemlist operands.
	(print_register_list): Use PRIi64 to print the index.
	(aarch64_print_operand): Likewise.

gas/
	* testsuite/gas/aarch64/diagnostic.s,
	testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
2016-06-28 09:21:04 +01:00
Maciej W. Rozycki c9775dde32 MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.

	include/
	* elf/mips.h (R_MIPS16_PC16_S1): New relocation.

	bfd/
	* elf32-mips.c (elf_mips16_howto_table_rel): Add
	R_MIPS16_PC16_S1.
	(mips16_reloc_map): Likewise.
	* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
	(mips16_elf64_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
	(elf_mips16_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfxx-mips.c (mips16_branch_reloc_p): New function.
	(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
	(b_reloc_p): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	gas/
	* config/tc-mips.c (mips16_reloc_p): Handle
	BFD_RELOC_MIPS16_16_PCREL_S1.
	(b_reloc_p): Likewise.
	(limited_pcrel_reloc_p): Likewise.
	(md_pcrel_from): Likewise.
	(md_apply_fix): Likewise.
	(tc_gen_reloc): Likewise.
	(md_convert_frag): Likewise.
	(mips_fix_adjustable): Update comment.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
	* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
	implicit instruction padding, avoid MIPS16 JR->JRC conversion.
	* testsuite/gas/mips/branch-weak-6.d: New test.
	* testsuite/gas/mips/branch-weak-7.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 01:29:56 +01:00
Vineet Gupta 45a54ee577 Make the kernel dwarf stack unwinder work for ARC targets.
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
	cfi_add_CFA_def_cfa to generate default CFA with offset
	* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
2016-06-27 16:50:29 +01:00
Nick Clifton 2edb36e77f Add command line option to stop the assembler from padding the end of sections to their alignment boundary.
PR gas/20247
	* as.h (do_not_pad_sections_to_alignment): New global variable.
	* as.c (show_usage): Add --no-pad-sections.
	(parse_args): Likewise.
	* write.c (size_seg): Skip padding the end of the section if
	requested from the command line.
	(SUB_SEGMENT_ALIGN): Likewise.
	* doc/as.texinfo: Document the new option.
	* NEWS: Mention the new feature.
	* testsuite/gas/elf/section11.s: New test.
	* testsuite/gas/elf/section11.d: New test driver.
	* testsuite/gas/elf/elf.exp: Run the new test.
2016-06-27 13:51:06 +01:00
Maciej W. Rozycki 88a7ef1689 MIPS16/GAS: Restore unsupported relocation diagnostics
Correct a MIPS16 relocation handling regression in GAS introduced with:

commit 177b4a6ad0
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Mon Mar 18 18:56:18 2002 +0000

discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>,
which removed a preparatory call to `mips16_extended_frag' previously
made from `md_estimate_size_before_relax'.  As a result the function is
never called with its `sec' parameter non-NULL and consequently all the
unsupported relocation checks within are dead and never trigger, causing
any unhandled relocations to silently resolve to 0.  Unfortunately there
was no sufficient test suite coverage back then to catch this.

Remove all dead code then, and all the associated comments.  Update the
remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass
the relocation section as the `sec' parameter and use it to mark frags
which require an external relocation, as extended.  Finally handle any
outstanding MIPS16 relocations in `md_convert_frag' and report an error
since we don't support any except with percent operators.

	gas/
	* config/tc-mips.c (append_insn): Use any `O_symbol' expression
	unchanged with relaxed MIPS16 instructions.
	(mips16_extended_frag): Adjust accordingly.  Return 1 right
	away if a relocation will be required for the symbol requested.
	Remove dead first relaxation pass code.
	(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
	(md_convert_frag): Adjust symbol value calculation.  Raise an
	error if a relocation is required for the symbol requested.
	* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
	add error output.
	* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
	* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
	* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
	* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
	* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-25 00:54:59 +01:00
Maciej W. Rozycki 0e9c5a5c99 MIPS/GAS: Keep the original microMIPS symbol reference in branch relocs
Keep original microMIPS symbols in references from branch relocations so
that the ISA bit is retained and can be verified for validity in static
link.  No need to update WRT MIPS16 symbols because we keep them all
anyway for other reasons.

	gas/
	* config/tc-mips.c (b_reloc_p): New function.
	(mips_fix_adjustable): Also keep the original microMIPS symbol
	referred from branch relocations.
	* testsuite/gas/mips/branch-local-1.d: New test.
	* testsuite/gas/mips/branch-local-n32-1.d: New test.
	* testsuite/gas/mips/branch-local-n64-1.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
	relocations.
	* testsuite/gas/mips/branch-local-1.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new cases.
2016-06-23 12:23:32 +01:00
Peter Bergner 6fd3a02da5 Add support for yet some more new ISA 3.0 instructions.
opcodes/
	* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
	(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
	mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
	xor3>: New mnemonics.
	<setb>: Change to a VX form instruction.
	(insert_sh6): Add support for rldixor.
	(extract_sh6): Likewise.

gas/
	* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
	mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
	setbool, xor3>: New tests.
	* testsuite/gas/ppc/power9.s: Likewise.
2016-06-22 17:55:17 -05:00
Maciej W. Rozycki 41947d9e38 MIPS/GAS: Handle resolved R6 PC-relative relocations
Complement commit 7361da2c95 ("Add support for MIPS R6.") and fix
internal errors like:

foo.s: Assembler messages:
foo.s: Internal error!
Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028.
Please report this bug.

triggered by resolved R6 PC-relative relocations in sources containing
R6 code fragments wrapped into ISA override blocks embedded within code
otherwise assembled for an older ISA.

	gas/
	* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
	<BFD_RELOC_LO16_PCREL>: New switch cases.
	(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
	Move switch cases along `BFD_RELOC_MIPS_JMP'.
	<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
	<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
	the resolved case.
	* testsuite/gas/mips/pcrel-reloc-4.d: New test.
	* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-5.d: New test.
	* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
	* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
	* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21 23:00:20 +01:00
Maciej W. Rozycki 912815f079 MIPS/GAS: Use the module level ISA setting for R6 relaxation
Use the module level ISA setting rather than the last ISA selected with
a `.set' directive in the source file in determination as to whether to
keep PC-relative relocations and then with the original symbol referred,
for the purpose of R6 linker relaxation.

This is so that with e.g. code like this:

	b	foo
	.set	mips32r2
	...

it's the command line options or any `.module' directive that decides
how to encode any relocation for `foo' rather than the presence of `.set
mips32r2'.

	gas/
	* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
	rather than `mips_opts' for the R6 ISA check.
	(mips_fix_adjustable): Likewise.
	* testsuite/gas/mips/pcrel-reloc-1.d: New test.
	* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-2.d: New test.
	* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-3.d: New test.
	* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21 18:05:18 +01:00
Graham Markall bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
Maciej W. Rozycki ff03d62a82 MIPS/GAS/testsuite: Uniquely identify MIPS64r6 tests
gas/
	* testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.
	* testsuite/gas/mips/r6-64-n64.d: Likewise.
2016-06-20 23:43:24 +01:00
Jose E. Marchesi 96074adc6a opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.

It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.

Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (rdasr): New macro.
	(wrasr): Likewise.
	(rdpr): Likewise.
	(wrpr): Likewise.
	(rdhpr): Likewise.
	(wrhpr): Likewise.
	(sparc_opcodes): Use the macros above to fix and expand the
	definition of read/write instructions from/to
	asr/privileged/hyperprivileged instructions.
	* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
	%hva_mask_nz.  Prefer softint_set and softint_clear over
	set_softint and clear_softint.
	(print_insn_sparc): Support %ver in Rd.

gas/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
	%hmcddfr and %hva_mask_nz.
	(sparc_ip): New handling of asr/privileged/hyperprivileged
	registers, adapted to the new form of the sparc opcodes table.
	* testsuite/gas/sparc/rdasr.s: New file.
	* testsuite/gas/sparc/rdasr.d: Likewise.
	* testsuite/gas/sparc/wrasr.s: Likewise.
	* testsuite/gas/sparc/wrasr.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
	wrasr tests.
	* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
	registers require it.
	* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
	registers and write instruction modalities.
	* testsuite/gas/sparc/wrpr.d: Likewise.
	* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
	registers.
	* testsuite/gas/sparc/rdhpr.d: Likewise.
	* testsuite/gas/sparc/wrhpr.s: Likewise.
	* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 02:15:43 -07:00
Jose E. Marchesi 7a10c22feb opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.

It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
	architecture according to the hardware capabilities they require.
	(sparc_priv_regs): New table.
	(sparc_hpriv_regs): Likewise.
	(sparc_asr_regs): Likewise.
	(v9anotv9m): Define.

gas/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): adjust the GAS
	architectures to use the right opcode architecture.
	(sparc_md_end): Handle v9{c,d,e,v,m}.
	(sparc_ip): Fix some comments.
	* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
	instruction, which is v9d.
	* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
	instruction from the test, as %mwait is not readable.
	* testsuite/gas/sparc/mwait.d: Likewise.
	* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
	mismatch architecture errors.
	* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 02:14:18 -07:00
Nick Clifton 3ee6e4fbec Fix simple gas testsuite failures.
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20
	reloc.

gas	* config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
	instruction size.
	* config/tc-mcore.c (md_assemble): Likewise.
	* config/tc-mn10200.c (md_assemble): Likewise.
	* config/tc-moxie.c (md_assemble): Likewise.
	* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
	* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
	exception targets.  Add alpha, hppa, microblaze and rl78 to list
	of exceptions.
	(forward): Add microblaze to list of exceptions.
	(fwdexp): Add alpha to list of exceptions.
	(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
	(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
	(do_930509a): Alpha sort list of exception targets.  Add h8300 and
	mn10200 to list of exceptions.
	(align2): Expect to fail for nds32.
	(cond): Add alpha and rl78 to list of exceptions.
	* testsuite/gas/all/none.d: Skip for ft32 and hppa.
	* testsuite/gas/all/string.d: Skip for tic4x.
	* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
	target does not support ELF.
	* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
	* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
	* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets.  Skip SH
	tests for sh-pe and sh-rtemscoff targets.
	* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
	list of exceptions.
	(type): Run the noifunc version for alpha-freebsd and visium.
	* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
	mn10200 or moxie targets.
	* testsuite/gas/ft32/insn.d: Update expected disassembly.
	* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
	targets.
	* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
	mcore and rx targets.
	* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
	rl78 and vax.
	(purge): Expect to fail on the ns32k and vax.
	* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
	* testsuite/gas/nds32/ls.d: Likewise.
	* testsuite/gas/nds32/sys-reg.d: Likewise.
	* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
	* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
	* testsuite/gas/pe/section-align-3.d: Likewise.
	* testsuite/gas/pe/section-exclude.d: Likewise.
	* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
	data has been seen.
	* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
	for variations in whitespace.
	* testsuite/gas/tilepro/t_constants.d: Pass once all the required
	data has been seen.
	* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
	Installs a 32-bit value without generating warnings on 64-bit
	hosts.
	Use the new macro to replace the .word directives.

opcodes	* nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
	constants to match expected behaviour.
	(nds32_parse_opcode): Likewise.  Also for whitespace.
2016-06-15 16:25:34 +01:00
Andrew Burgess 02f3be19f6 opcodes/arc: Fix extract for some add_s instructions
The extract function used for some arc_s instructions was not
implemented, and instead always returned 0.  Fixed in this commit.

opcodes/ChangeLog:

	* arc-opc.c (extract_rhv1): Extract value from insn.

gas/ChangeLog:

	* testsuite/gas/arc/add_s.d: New file.
	* testsuite/gas/arc/add_s.s: New file.
2016-06-15 09:01:48 +01:00
Graham Markall 28215275a6 [ARC] Add ldbit for nps
This commit adds the ldbit instruction for the NPS-400. The ldbit
instruction uses the same encoding as the ld instruction, but sets
the ZZ field to 11 (which is a reserved setting), and sets the AA
field to 1 or 2 for the x2 and x4 flags respectively.
2016-06-14 16:21:44 +01:00