'info registers' for MIPS throws an error and when it first encounters
an unavailable register. This does not match other architectures
which annotate unavailable registers and continue to print out the
values of subsequent registers. Replace the error by displaying an
aligned "<unavailable>". This string is truncated to "<unavl>" when
displaying a 32-bit register.
gdb/ChangeLog:
* mips-tdep.c (print_gp_register_row): Don't error for unavailable
registers.
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
mips_eabi_push_dummy_call is storing the address of a struct in a
buffer that must have the same of the confisued/set ABI register size.
Add a define for the maximum ABI size and use it to size the local
buffer. Also rename the 'regsize' local to 'abi_regsize' for clarity.
Tested that --enable-targets=all still builds.
gdb/ChangeLog:
2017-06-12 Pedro Alves <palves@redhat.com>
Alan Hayward <alan.hayward@arm.com>
* mips-tdep.c (MAX_MIPS_ABI_REGSIZE): New.
(mips_eabi_push_dummy_call): Rename local 'regsize' to
'abi_regsize'. Rename local array 'valbuf' to 'ref_valbuf', and
use MAX_MIPS_ABI_REGSIZE instead of MAX_REGISTER_SIZE to size it.
Assert that abi_regsize bytes fit in 'ref_valbuf'.
One line was using printf_filtered instead of fprintf_filtered
to the requested file.
gdb/ChangeLog:
* mips-tdep.c (print_gp_register_row): Replace printf_filtered
with fprintf_filtered.
This patch addes class gdb_disassembler, and refactor
code to use it. The gdb_disassembler object is saved
in disassember_info.application_data. However,
disassember_info.application_data is already used by
gdb for arm, mips spu, and scm-disasm. In arm and mips,
.application_data is gdbarch, but we can still get gdbarch
from gdb_disassember.
The use of application_data in spu is a little bit
complicated. It creates its own disassemble_info, and
save spu_dis_asm_data in .application_data. This will
overwrite the pointer to gdb_disassembler, so we need
to find another place to save spu_dis_asm_data. I
extend disassemble_info, and put "id" there.
gdb:
2017-01-26 Pedro Alves <palves@redhat.com>
Yao Qi <yao.qi@linaro.org>
* arm-tdep.c: Include "disasm.h".
(gdb_print_insn_arm): Update code to get gdbarch.
* disasm.c (dis_asm_read_memory): Change it to
gdb_disassembler::dis_asm_read_memory.
(dis_asm_memory_error): Likewise.
(dis_asm_print_address): Likewise.
(gdb_pretty_print_insn): Change it to
gdb_disassembler::pretty_print_insn.
(dump_insns): Add one argument gdb_disassemlber. All
callers updated.
(do_mixed_source_and_assembly_deprecated): Likewise.
(do_mixed_source_and_assembly): Likewise.
(do_assembly_only): Likewise.
(gdb_disassembler::gdb_disassembler): New.
(gdb_disassembler::print_insn): New.
* disasm.h (class gdb_disassembler): New.
(gdb_pretty_print_insn): Remove declaration.
(gdb_disassemble_info): Likewise.
* guile/scm-disasm.c (class gdbscm_disassembler): New.
(gdbscm_disasm_read_memory_worker): Update.
(gdbscm_disasm_read_memory): Update.
(gdbscm_disasm_memory_error): Remove.
(gdbscm_disasm_print_address): Remove.
(gdbscm_disassembler::gdbscm_disassembler): New.
(gdbscm_print_insn_from_port): Update.
* mips-tdep.c: Include disasm.h.
(gdb_print_insn_mips): Update code to get gdbarch.
* record-btrace.c (btrace_insn_history): Update.
* spu-tdep.c: Include disasm.h.
(struct spu_dis_asm_data): Remove.
(struct spu_dis_asm_info): New.
(spu_dis_asm_print_address): Use spu_dis_asm_info to get
SPU id.
(gdb_print_insn_spu): Cast disassemble_info to
spu_dis_asm_info.
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
Both of them are used in conversion. We can remove them since the
conversion is done.
There are many architectures only have one breakpoint instruction,
so their gdbarch methods breakpoint_kind_from_pc and
sw_breakpoint_from_kind look very similar. Instead of macro, we
use template "template <size_t, const gdb_byte *> struct bp_manipulation"
for these architectures. In order to use template, I also change
breakpoint instruction of type "static const gdb_byte[]" to
"constexpr gdb_byte[]", and rename them to ARCH_break_insn.
gdb:
2016-11-03 Yao Qi <yao.qi@linaro.org>
Pedro Alves <palves@redhat.com>
* aarch64-tdep.c (aarch64_default_breakpoint): Change it to
constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(aarch64_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* alpha-tdep.c (break_insn): Rename to alpha_break_insn.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(alpha_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* arc-tdep.c (arc_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* arch-utils.h (GDBARCH_BREAKPOINT_MANIPULATION): Remove.
(struct bp_manipulation): New.
(SET_GDBARCH_BREAKPOINT_MANIPULATION): Remove.
(struct bp_manipulation_endian): New.
(BP_MANIPULATION): New.
(BP_MANIPULATION_ENDIAN): New.
* arm-tdep.c (arm_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* avr-tdep.c (avr_break_insn): Change it constexpr.
(avr_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* bfin-tdep.c (bfin_gdbarch_init): Likewise.
* cris-tdep.c (cris_gdbarch_init): Likewise.
* frv-tdep.c (breakpoint): Rename it to frv_break_insn, and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(frv_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* ft32-tdep.c (breakpoint): Rename it to ft32_break_insn and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(ft32_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* h8300-tdep.c (breakpoint): Rename it to h8300_break_insn.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(h8300_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* hppa-tdep.c (breakpoint): Rename it to h8300_break_insn.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(hppa_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* i386-tdep.c (break_insn): Rename it to i386_break_insn.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(i386_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* iq2000-tdep.c (iq2000_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* lm32-tdep.c (breakpoint): Rename it to lm32_break_insn and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(lm32_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* m32c-tdep.c (break_insn): Rename it to m32c_break_insn and change
its type to constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(m32c_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* m32r-tdep.c (m32r_gdbarch_init): Likewise.
* m68hc11-tdep.c (breakpoint): Rename it to m68hc11_break_insn and
change its type to constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(m68hc11_gdbarch_init): Don't use SET_GDBARCH_BREAKPOINT_MANIPULATION.
* m68k-tdep.c (break_insn): Rename it to m68k_break_insn and change
its type to constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(m68k_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* m88k-tdep.c (break_insn): Rename it to m88k_break_insn and change
its type to constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(m88k_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* mep-tdep.c (breakpoint): Rename it to mep_break_insn and change
its type to constexpr. Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(mep_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* microblaze-tdep.c (break_insn): Rename it to
microblaze_break_insn and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(microblaze_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* mn10300-tdep.c (breakpoint): Rename it to mn10300_break_insn and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(mn10300_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* moxie-tdep.c (breakpoint): Rename it to moxie_break_insn and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(moxie_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* msp430-tdep.c (breakpoint): Rename it to msp430_break_insn
and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(msp430_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* mt-tdep.c (mt_gdbarch_init): Likewise.
* nds32-tdep.c (break_insn): Rename it to nds32_break_insn
and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(nds32_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* nios2-tdep.c (nios2_gdbarch_init): Likewise.
* rl78-tdep.c (breakpoint): Rename it to rl78_break_ins
and change its type to rl78_break_insn. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(rl78_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* rs6000-tdep.c (big_breakpoint): Change its type to
constexpr.
(little_breakpoint): Likewise.
Don't use GDBARCH_BREAKPOINT_MANIPULATION_ENDIAN.
(rs6000_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* rx-tdep.c (breakpoint): Rename it to rx_break_insn and
change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(rx_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* s390-linux-tdep.c (breakpoint): Rename it to s390_break_insn
and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION
(s390_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* score-tdep.c (score_gdbarch_init): Likewise.
* sh-tdep.c (sh_gdbarch_init): Likewise.
* sh64-tdep.c (sh64_gdbarch_init): Likewise.
* sparc-tdep.c (break_insn): Rename it to sparc_break_insn
and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(sparc32_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* spu-tdep.c (breakpoint): Rename it to spu_break_insn and change
its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(spu_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* tic6x-tdep.c (tic6x_gdbarch_init): Likewise.
* tilegx-tdep.c (breakpoint): Rename it to tilegx_break_insn
and change its type to constexpr. Don't use
GDBARCH_BREAKPOINT_MANIPULATION.
(tilegx_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* v850-tdep.c (v850_gdbarch_init): Likewise.
* vax-tdep.c (break_insn): Rename it to vax_break_insn and
change its type to constexpr.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(vax_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* xstormy16-tdep.c (breakpoint): Rename it to
xstormy16_break_insn and change its type to constexpr.
Don't use GDBARCH_BREAKPOINT_MANIPULATION.
(xstormy16_gdbarch_init): Don't use
SET_GDBARCH_BREAKPOINT_MANIPULATION.
* xtensa-tdep.c (xtensa_gdbarch_init): Likewise.
This patch adds two gdbarch methods breakpoint_kind_from_pc and
sw_breakpoint_from_kind, and uses target_info.placed_size as "kind"
of the breakpoint. This patch updates the usages of
target_info.placed_size.
The "kind" of a breakpoint is determined by gdbarch rather than
target, so we have gdbarch method breakpoint_kind_from_pc, and we
should set target_info.placed_size out of each implementation of
target to_insert_breakpoint. In this way, each target doesn't have
to set target_info.placed_size any more.
This patch also sets target_info.placed_address before
target_insert_breakpoint too, so that target to_insert_breakpoint
can use it, see record_full_insert_breakpoint.
Before we call target_insert_breakpoint, we set
target_info.placed_address and target_info.placed_size like this,
CORE_ADDR addr = bl->target_info.reqstd_address;
bl->target_info.placed_size = gdbarch_breakpoint_kind_from_pc (bl->gdbarch, &addr);
bl->target_info.placed_address = addr;
return target_insert_breakpoint (bl->gdbarch, &bl->target_info);
target_insert_breakpoint may fail, but it doesn't matter to the "kind"
and "placed_address" of a breakpoint. They should be determined by
gdbarch.
gdb:
2016-11-03 Yao Qi <yao.qi@linaro.org>
* arch-utils.h (GDBARCH_BREAKPOINT_MANIPULATION): Define
breakpoint_kind_from_pc and sw_breakpoint_from_kind.
(GDBARCH_BREAKPOINT_MANIPULATION_ENDIAN): Likewise.
(SET_GDBARCH_BREAKPOINT_MANIPULATION): Call
set_gdbarch_breakpoint_kind_from_pc and
set_gdbarch_sw_breakpoint_from_kind.
* arm-tdep.c: Add comments.
* bfin-tdep.c: Likewise.
* breakpoint.c (breakpoint_kind): New function.
(insert_bp_location): Set target_info.placed_size and
target_info.placed_address.
(bkpt_insert_location): Likewise.
* cris-tdep.c: Add comments.
* gdbarch.sh (breakpoint_kind_from_pc): New.
(sw_breakpoint_from_kind): New.
* gdbarch.c, gdbarch.h: Regenerated.
* ia64-tdep.c (ia64_memory_insert_breakpoint): Don't set
bp_tgt->placed_size.
(ia64_memory_remove_breakpoint): Don't assert
bp_tgt->placed_size.
(ia64_breakpoint_kind_from_pc): New function.
(ia64_gdbarch_init): Install ia64_breakpoint_kind_from_pc.
* m32r-tdep.c (m32r_memory_insert_breakpoint): Don't set
bp_tgt->placed_size.
* mem-break.c (default_memory_insert_breakpoint): Don't set
bp_tgt->placed_size. Call gdbarch_sw_breakpoint_from_kind.
(default_memory_remove_breakpoint): Call
gdbarch_sw_breakpoint_from_kind.
(memory_validate_breakpoint): Don't check bp_tgt->placed_size.
* mips-tdep.c: Add comments.
* mt-tdep.c: Likewise.
* nios2-tdep.c: Likewise.
* record-full.c (record_full_insert_breakpoint): Don't call
gdbarch_breakpoint_from_pc. Don't set bp_tgt->placed_address
and bp_tgt->placed_size.
* remote.c (remote_insert_breakpoint): Don't call
gdbarch_remote_breakpoint_from_pc. Use bp_tgt->placed_size.
Don't set bp_tgt->placed_address and bp_tgt->placed_size.
(remote_insert_hw_breakpoint): Likewise.
* score-tdep.c: Likewise.
* sh-tdep.c: Likewise.
* tic6x-tdep.c: Likewise.
* v850-tdep.c: Likewise.
* xtensa-tdep.c: Likewise.
This patch adds an enum mips_breakpoint_kind to avoid using magic
numbers as much as possible.
gdb:
2016-11-03 Yao Qi <yao.qi@linaro.org>
* mips-tdep.c (mips_breakpoint_kind): New enum.
(mips_breakpoint_from_pc): Use it.
(mips_remote_breakpoint_from_pc): Likewise.
Complement commit f7c382926d ("Remove support for "target m32rsdi" and
"target mips/pmon/ddb/rockhopper/lsi"") and remove dead MIPS target code
which used to support these legacy remote targets.
gdb/
* mips-tdep.c (mips_r3041_reg_names): Remove.
(mips_breakpoint_from_pc): Remove IDT and PMON breakpoint
encodings.
Fix a regression from commit f8b73d13b7 ("Target-described register
support for MIPS"),
<https://sourceware.org/ml/gdb-patches/2007-05/msg00340.html>,
<https://sourceware.org/ml/gdb-patches/2007-06/msg00256.html>, which
caused Floating Point Control Registers (FCRs) to be shown as 64-bit
with 64-bit targets.
This came from the legacy register format where all raw registers
matched the width of the architecture regardless of their actual size.
The correct size was then set in `mips_register_type' for cooked
registers presented to the user, which in the case of FCRs meant the
cooked size was always forced to 32 bits, reflecting their actual
hardware size, even though the raw format carried them in 64-bit
quantities on 64-bit targets. The upper 32 bits carried in the raw FCR
format have always been don't-cares, not actually retrieved from
hardware and never written back.
With the introduction of XML register descriptions the layout of
previously defined raw registers has been preserved, so as to keep
existing register handling code unchanged and make it easier for GDB and
`gdbserver' to interact with each other whether neither, either or both
parties talking over RSP support XML register descriptions. For the
XML-described case however `mips_register_type' is not used in raw to
cooked register conversion, so any special cases coded there are not
taken into account.
Instead a new function, `mips_pseudo_register_type', has been introduced
to handle size conversion, however lacking the special case for FCRs for
the Linux and the now defunct IRIX target. The correct size has been
maintained for embedded targets however, due to the bundling of FCRs
with the embedded registers under the `rawnum >= MIPS_EMBED_FP0_REGNUM +
32' condition.
Add the missing case to `mips_pseudo_register_type' then, referring to
the FCR indices explicitly, and observing that between
`MIPS_EMBED_FP0_REGNUM + 32' and `MIPS_FIRST_EMBED_REGNUM' there is an
unused register slot whose contents are ignored so with the removal of
embedded FCRs from under that condition we don't have to care about it
and we can refer to the embedded registers starting from
MIPS_FIRST_EMBED_REGNUM instead.
Add a test case too so that we have means to check automatically that
the correct user-visible size of FCRs is maintained.
gdb/
* mips-tdep.c (mips_pseudo_register_type): Make FCRs always
32-bit.
gdb/testsuite/
* gdb.arch/mips-fcr.exp: New test.
* gdb.arch/mips-fcr.c: Source for the new test.
Rearrange comments throughout `mips_pseudo_register_type', placing them
ahead the condtionals they apply to consistently.
gdb/
* mips-tdep.c (mips_pseudo_register_type): Rearrange comments
throughout.
Set the number of registers for non-XML-described Linux targets to 90,
reverting a change made here with the addition of DSP register support:
commit 1faeff088b
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Thu Mar 1 22:19:48 2012 +0000
and fixing a regression introduced for legacy `gdbserver' targets
causing a "Remote 'g' packet reply is too long" error message where the
amount of register data received with a `g' packet (90) exceeds the
maximum number of registers expected (79).
Update the setting for XML-described targets, reflecting the actual
number of registers which have been assigned numbers, matching the:
gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
requirement in `mips_linux_init_abi'.
gdb/
* mips-tdep.c (mips_gdbarch_init): For GDB_OSABI_LINUX set
`num_regs' to 90 rather than 79. Where a target description is
present adjust the setting appropriately.
This removes support for:
| target | source |
|-------------------+-----------------------|
| target m32rsdi | gdb/remote-m32r-sdi.c |
| target mips | gdb/remote-mips.c |
| target pmon | gdb/remote-mips.c |
| target ddb | gdb/remote-mips.c |
| target rockhopper | gdb/remote-mips.c |
| target lsi | gdb/remote-mips.c |
That is:
- Remote M32R debugging over SDI.
- Debugging boards using the MIPS remote debugging protocol
over a serial line, PMON, and a few variants.
These are the last non-"target remote" remote targets in the tree, if
you don't count "target sim".
Refs:
https://sourceware.org/ml/gdb/2016-03/msg00004.htmlhttps://sourceware.org/ml/gdb-patches/2016-03/msg00580.html
gdb/ChangeLog:
2016-03-31 Pedro Alves <palves@redhat.com>
* NEWS: Mention that support for "target m32rsdi", "target mips",
"target pmon", "target ddb", "target rockhopper", and "target lsi"
was removed.
* Makefile.in (ALL_TARGET_OBS): Remove remote-m32r-sdi.o and
remote-mips.o.
(ALLDEPFILES): Remove remote-m32r-sdi.c and remote-mips.c.
* configure.tgt: Remove all references to remote-m32r-sdi.o and
remote-mips.o.
* mips-tdep.c (deprecated_mips_set_processor_regs_hack): Delete
function.
* mips-tdep.h (deprecated_mips_set_processor_regs_hack): Delete
declaration.
* remote-m32r-sdi.c, remote-mips.c: Delete files.
* symfile.c (generic_load, generic_load): Remove comments.
gdb/doc/ChangeLog:
2016-03-31 Pedro Alves <palves@redhat.com>
* gdb.texinfo (M32R/SDI): Delete node.
(MIPS Embedded): Remove references to the MIPS remote debugging
protocol, PMON and variants, and the associated commands.
Fix this GDB crash:
$ gdb -ex "set architecture mips:10000"
Segmentation fault (core dumped)
Backtrace:
Program received signal SIGSEGV, Segmentation fault.
0x0000000000495b1b in mips_gdbarch_init (info=..., arches=0x0) at /home/pedro/gdb/mygit/cxx-convertion/src/gdb/mips-tdep.c:8436
8436 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
(top-gdb) bt
#0 0x0000000000495b1b in mips_gdbarch_init (info=..., arches=0x0) at .../src/gdb/mips-tdep.c:8436
#1 0x00000000007348a6 in gdbarch_find_by_info (info=...) at .../src/gdb/gdbarch.c:5155
#2 0x000000000073563c in gdbarch_update_p (info=...) at .../src/gdb/arch-utils.c:522
#3 0x0000000000735585 in set_architecture (ignore_args=0x0, from_tty=1, c=0x26bc870) at .../src/gdb/arch-utils.c:496
#4 0x00000000005f29fd in do_sfunc (c=0x26bc870, args=0x0, from_tty=1) at .../src/gdb/cli/cli-decode.c:121
#5 0x00000000005fd3f3 in do_set_command (arg=0x7fffffffdcdd "mips:10000", from_tty=1, c=0x26bc870) at .../src/gdb/cli/cli-setshow.c:455
#6 0x0000000000836157 in execute_command (p=0x7fffffffdcdd "mips:10000", from_tty=1) at .../src/gdb/top.c:460
#7 0x000000000071abfb in catch_command_errors (command=0x835f6b <execute_command>, arg=0x7fffffffdccc "set architecture mips:10000", from_tty=1)
at .../src/gdb/main.c:368
#8 0x000000000071bf4f in captured_main (data=0x7fffffffd750) at .../src/gdb/main.c:1132
#9 0x0000000000716737 in catch_errors (func=0x71af44 <captured_main>, func_args=0x7fffffffd750, errstring=0x106b9a1 "", mask=RETURN_MASK_ALL)
at .../src/gdb/exceptions.c:240
#10 0x000000000071bfe6 in gdb_main (args=0x7fffffffd750) at .../src/gdb/main.c:1164
#11 0x000000000040a6ad in main (argc=4, argv=0x7fffffffd858) at .../src/gdb/gdb.c:32
(top-gdb)
We already check whether info.abfd is NULL before all other
bfd_get_flavour calls in the same function. Just this one case was
missing.
(This was exposed by a WIP test that tries all "set architecture ARCH"
values.)
gdb/ChangeLog:
2016-03-07 Pedro Alves <palves@redhat.com>
* mips-tdep.c (mips_gdbarch_init): Check whether info.abfd is NULL
before calling bfd_get_flavour.
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.
This complements commit a6c7053929 ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
Major Opcode Field", p. 578
gas/
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
gdb/
* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
instruction support.
(micromips_next_pc): Likewise.
(micromips_scan_prologue): Likewise.
(micromips_deal_with_atomic_sequence): Likewise.
(micromips_stack_frame_destroyed_p): Likewise.
(mips_breakpoint_from_pc): Likewise.
opcodes/
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
instruction support.
Fix a bug in `micromips_insn_at_pc_has_delay_slot' in instruction size
determination via `mips_insn_size'. In the microMIPS case the latter
function expects a lone 16-bit instruction word containing the major
opcode regardless of whether the opcode requires another 16-bit word to
follow, to form a complete 32-bit instruction. Code however passes the
16-bit word previously retrieved shifted left by 16 bits. Consequently
`mips_insn_size', which examines the low 16-bit only, always sees 0.
By pure coincidence a major opcode of 0 denotes a 32-bit instruction in
the microMIPS instruction set, so the size of 4 is always returned here,
and the following 16-bit word is then merged in the low 16 bits of the
instruction previously shifted by 16 bits. The resulting 32-bit value
is then passed to `micromips_instruction_has_delay_slot' for delay slot
presence determination. This function in turn first examines the high
16 bits of the instruction word received and ignores the low 16 bits for
16-bit instructions.
Consequently the only effect of this bug is an extraneous memory read
issued to retrieve a subsequent 16-bit word where a 16-bit instruction
is being examined. Which in turn may fail if the instruction is located
right at the end of a readable memory area, in which case the lack of a
delay slot will be reported to the caller, which may be incorrect.
This code is used in breakpoint maintenance, for delay slot avoidance,
so the bug would only trigger for the unlikely case of someone placing
a breakpoint in a delay slot of an instruction which is at the end of
readable memory. Which explains why the bug remained unnoticed so long.
gdb/
* mips-tdep.c (micromips_insn_at_pc_has_delay_slot): Pass
unshifted 16-bit microMIPS instruction word to `mips_insn_size'.
Complement commit d09f2c3f [target_read_memory&co: no longer return
target_xfer_status] and apply the same change made to the big-endian leg
of the function to the little-endian leg as well.
gdb/
* mips-tdep.c (mips_breakpoint_from_pc): Rename local `status'
to `err' in the little-endian leg.
Years ago, these functions used to return errno/EIO. Later, through a
series of changes that intended to remove native/remote differences,
they ended up returning a target_xfer_status in disguise.
Unlike target_xfer_partial&co, the point of target_read_memory&co is
to either fully succeed or fail. On error, they always return
TARGET_XFER_E_IO. So there's no real point in casting the return of
target_read_memory to a target_xfer_status to pass it to memory_error.
Instead, it results in clearer code to simply decouple
target_read_memory&co's return from target_xfer_status.
This fixes build errors like this in C++ mode:
../../src/gdb/corefile.c: In function ‘void read_stack(CORE_ADDR, gdb_byte*, ssize_t)’:
../../src/gdb/corefile.c:276:34: error: invalid conversion from ‘int’ to ‘target_xfer_status’ [-fpermissive]
memory_error (status, memaddr);
^
../../src/gdb/corefile.c:216:1: error: initializing argument 1 of ‘void memory_error(target_xfer_status, CORE_ADDR)’ [-fpermissive]
gdb/ChangeLog:
2015-10-27 Pedro Alves <palves@redhat.com>
* alpha-tdep.c (alpha_read_insn): Always pass TARGET_XFER_E_IO to
memory_error. Rename local 'status' to 'res'.
* c-lang.c (c_get_string): Always pass TARGET_XFER_E_IO to
memory_error.
* corefile.c (read_stack, read_code, write_memory): Always pass
TARGET_XFER_E_IO to memory_error.
* disasm.c (dis_asm_memory_error): Always pass TARGET_XFER_E_IO to
memory_error. Rename parameter 'status' to 'err'.
(dump_insns): Rename local 'status' to 'err'.
* mips-tdep.c (mips_fetch_instruction): Rename parameter 'statusp'
to 'errp'. Rename local 'status' to 'err'. Always pass
TARGET_XFER_E_IO to memory_error.
(mips_breakpoint_from_pc): Rename local 'status' to 'err'.
* target.c (target_read_memory, target_read_raw_memory)
(target_read_stack, target_read_code, target_write_memory)
(target_write_raw_memory): Return -1 on error instead of
TARGET_XFER_E_IO.
* valprint.c (val_print_string): Rename local 'errcode' to 'err'.
Always pass TARGET_XFER_E_IO to memory_error. Update comment.
As reported by Ulrich here:
https://sourceware.org/ml/gdb-patches/2015-09/msg00604.html
The system compiler (gcc 4.1) in Centos 5 doesn't like that we cast to a
pointer to a type that doesn't exist. I see no real value in using this
kind iof construct over just using void *. So this patch changes the
tdep_info field to void * and removes the casts. Even in C++, we
should not need an explicit cast when assigning to a void *.
gdb/ChangeLog:
* gdbarch.sh (struct gdbarch_info): Change tdep_info's type to void *.
* gdbarch.h: Regenerate.
* i386-tdep.c (i386_gdbarch_init): Remove cast to
struct gdbarch_tdep_info *.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* ppc-linux-tdep (ppu2spu_sniffer): Likewise.
* rs6000-tdep.c (rs6000_gdbarch_init): Likewise.
* spu-multiarch.c (spu_gdbarch): Likewise.
We concluded that gdbarch_in_function_epilogue_p is misnamed, since it
returns true if the given PC is one instruction after the one that
destroyed the stack (which isn't necessarily inside an epilogue),
therefore it should be renamed to stack_frame_destroyed_p.
I also took the liberty of renaming the arch-specific implementations to
*_stack_frame_destroyed_p as well for consistency.
gdb:
2015-05-26 Martin Galvan <martin.galvan@tallertechnologies.com>
* amd64-tdep.c: Replace in_function_epilogue_p with
stack_frame_destroyed_p throughout.
* arch-utils.c: Ditto.
* arch-utils.h: Ditto.
* arm-tdep.c: Ditto.
* breakpoint.c: Ditto.
* gdbarch.sh: Ditto.
* hppa-tdep.c: Ditto.
* i386-tdep.c: Ditto.
* mips-tdep.c: Ditto.
* nios2-tdep.c: Ditto.
* rs6000-tdep.c: Ditto.
* s390-linux-tdep.c: Ditto.
* score-tdep.c: Ditto.
* sh-tdep.c: Ditto.
* sparc-tdep.c: Ditto.
* sparc-tdep.h: Ditto.
* sparc64-tdep.c: Ditto.
* spu-tdep.c: Ditto.
* tic6x-tdep.c: Ditto.
* tilegx-tdep.c: Ditto.
* xstormy16-tdep.c: Ditto.
* gdbarch.c, gdbarch.h: Re-generated.
This commit introduces a new inline common function "startswith"
which takes two string arguments and returns nonzero if the first
string starts with the second. It also updates the 295 places
where this logic was written out longhand to use the new function.
gdb/ChangeLog:
* common/common-utils.h (startswith): New inline function.
All places where this logic was used updated to use the above.
Make the extracted stack offset signed in the standard MIPS prologue
scanner, to simplify handling and make sure register offsets are correct
in all cases, especially where $fp equals the virtual frame pointer (old
GCC frames) and therefore offsets to save slots are negative.
* mips-tdep.c (mips32_scan_prologue): Make the extracted stack
offset signed.
This patch is the V2. V1 can be found in
https://sourceware.org/ml/gdb-patches/2012-05/msg00938.html
V2 is to address Joel's comment
<https://sourceware.org/ml/gdb-patches/2012-06/msg00289.html> about
keeping dumping floating point registers. Additionally, command
'info float' prints bits on nan2008 and abs2008.
------------------------------------------------------------------
The change below provides a MIPS-specific handler for the:
(gdb) info float
command. It provides information about the FPU type available (if any),
the FPU register width, and decodes the CP1 Floating Point Control and
Status Register (FCSR):
(gdb) print /x $fsr
$1 = 0xff83ffff
(gdb) info float
fpu type: double-precision
reg size: 32 bits
cond : 0 1 2 3 4 5 6 7
cause : inexact uflow oflow div0 inval unimp
mask : inexact uflow oflow div0 inval
flags : inexact uflow oflow div0 inval
rounding: -inf
flush : zero
One point to note about CP1.FCSR are the non-standard Flush-to-Nearest
and Flush-Override bits. They are not a part of the MIPS architecture and
take two positions reserved for an implementation-dependent use in the
architecture. They are present in all the FPU implementations made by
MIPS Technologies since the spin-off from SGI.
I haven't been able to track down a single other MIPS FPU implementation
that would make any use of these bits and they are required to be
hardwired to zero by the architecture specification if unimplemented.
Therefore I think it makes sense to report them in the current way.
GDB has no guaranteed access to the CP0 Processor Identification (PRId)
register to validate this feature properly and the ID information stored
in the CP1 Floating Point Implementation Register (FIR) is from my
experience not reliable enough (there's no Company ID available there for
once unlike in CP0.PRId and Processor ID is not guaranteed to be unique).
As a side note we should probably dump CP1.FIR information as well, as
there's useful stuff indicating some FPU features there. That's material
for another change however.
gdb/
2014-12-18 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips-tdep.c (print_fpu_flags): New function.
(mips_print_float_info): Likewise.
(mips_gdbarch_init): Install mips_print_float_info as gdbarch
print_float_info routine.
gdb/testsuite/
2014-12-18 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* gdb.base/float.exp: Handle the new output from "info float" on
MIPS targets.
* mips-tdep.h (MSYMBOL_TARGET_FLAG_MIPS16): New macro.
(MSYMBOL_TARGET_FLAG_MICROMIPS): Likewise.
* mips-tdep.c (mips_elf_make_msymbol_special): Use the new
macros.
(msymbol_is_mips, msymbol_is_mips16, msymbol_is_micromips):
Likewise.
1. Background information
The MIPS architecture, as originally designed and implemented in
mid-1980s has a uniform instruction word size that is 4 bytes, naturally
aligned. As such all MIPS instructions are located at addresses that
have their bits #1 and #0 set to zeroes, and any attempt to execute an
instruction from an address that has any of the two bits set to one
causes an address error exception. This may for example happen when a
jump-register instruction is executed whose register value used as the
jump target has any of these bits set.
Then in mid 1990s LSI sought a way to improve code density for their
TinyRISC family of MIPS cores and invented an alternatively encoded
instruction set in a joint effort with MIPS Technologies (then a
subsidiary of SGI). The new instruction set has been named the MIPS16
ASE (Application-Specific Extension) and uses a variable instruction
word size, which is 2 bytes (as the name of the ASE suggests) for most,
but there are a couple of exceptions that take 4 bytes, and then most of
the 2-byte instructions can be treated with a 2-byte extension prefix to
expand the range of the immediate operands used.
As a result instructions are no longer 4-byte aligned, instead they are
aligned to a multiple of 2. That left the bit #0 still unused for code
references, be it for the standard MIPS (i.e. as originally invented) or
for the MIPS16 instruction set, and based on that observation a clever
trick was invented that on one hand allowed the processor to be
seamlessly switched between the two instruction sets at any time at the
run time while on the other avoided the introduction of any special
control register to do that.
So it is the bit #0 of the instruction address that was chosen as the
selector and named the ISA bit. Any instruction executed at an even
address is interpreted as a standard MIPS instruction (the address still
has to have its bit #1 clear), any instruction executed at an odd
address is interpreted as a MIPS16 instruction.
To switch between modes ordinary jump instructions are used, such as
used for function calls and returns, specifically the bit #0 of the
source register used in jump-register instructions selects the execution
(ISA) mode for the following piece of code to be interpreted in.
Additionally new jump-immediate instructions were added that flipped the
ISA bit to select the opposite mode upon execution. They were
considered necessary to avoid the need to make register jumps in all
cases as the original jump-immediate instructions provided no way to
change the bit #0 at all.
This was all important for cases where standard MIPS and MIPS16 code had
to be mixed, either for compatibility with the existing binary code base
or to access resources not reachable from MIPS16 code (the MIPS16
instruction set only provides access to general-purpose registers, and
not for example floating-point unit registers or privileged coprocessor
0 registers) -- pieces of code in the opposite mode can be executed as
ordinary subroutine calls.
A similar approach has been more recently adopted for the MIPS16
replacement instruction set defined as the so called microMIPS ASE.
This is another instruction set encoding introduced to the MIPS
architecture. Just like the MIPS16 ASE, the microMIPS instruction set
uses a variable-length encoding, where each instruction takes a multiple
of 2 bytes. The ISA bit has been reused and for microMIPS-capable
processors selects between the standard MIPS and the microMIPS mode
instead.
2. Statement of the problem
To put it shortly, MIPS16 and microMIPS code pointers used by GDB are
different to these observed at the run time. This results in the same
expressions being evaluated producing different results in GDB and in
the program being debugged. Obviously it's the results obtained at the
run time that are correct (they define how the program behaves) and
therefore by definition the results obtained in GDB are incorrect.
A bit longer description will record that obviously at the run time the
ISA bit has to be set correctly (refer to background information above
if unsure why so) or the program will not run as expected. This is
recorded in all the executable file structures used at the run time: the
dynamic symbol table (but not always the static one!), the GOT, and
obviously in all the addresses embedded in code or data of the program
itself, calculated by applying the appropriate relocations at the static
link time.
While a program is being processed by GDB, the ISA bit is stripped off
from any code addresses, presumably to make them the same as the
respective raw memory byte address used by the processor to access the
instruction in the instruction fetch access cycle. This stripping is
actually performed outside GDB proper, in BFD, specifically
_bfd_mips_elf_symbol_processing (elfxx-mips.c, see the piece of code at
the very bottom of that function, starting with an: "If this is an
odd-valued function symbol, assume it's a MIPS16 or microMIPS one."
comment).
This function is also responsible for symbol table dumps made by
`objdump' too, so you'll never see the ISA bit reported there by that
tool, you need to use `readelf'.
This is however unlike what is ever done at the run time, the ISA bit
once present is never stripped off, for example a cast like this:
(short *) main
will not strip the ISA bit off and if the resulting pointer is intended
to be used to access instructions as data, for example for software
instruction decoding (like for fault recovery or emulation in a signal
handler) or for self-modifying code then the bit still has to be
stripped off by an explicit AND operation.
This is probably best illustrated with a simple real program example.
Let's consider the following simple program:
$ cat foobar.c
int __attribute__ ((mips16)) foo (void)
{
return 1;
}
int __attribute__ ((mips16)) bar (void)
{
return 2;
}
int __attribute__ ((nomips16)) foo32 (void)
{
return 3;
}
int (*foo32p) (void) = foo32;
int (*foop) (void) = foo;
int fooi = (int) foo;
int
main (void)
{
return foop ();
}
$
This is plain C with no odd tricks, except from the instruction mode
attributes. They are not necessary to trigger this problem, I just put
them here so that the program can be contained in a single source file
and to make it obvious which function is MIPS16 code and which is not.
Let's try it with Linux, so that everyone can repeat this experiment:
$ mips-linux-gnu-gcc -mips16 -g -O2 -o foobar foobar.c
$
Let's have a look at some interesting symbols:
$ mips-linux-gnu-readelf -s foobar | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 7 entries:
Symbol table '.symtab' contains 95 entries:
55: 00000000 0 FILE LOCAL DEFAULT ABS foobar.c
66: 0040068c 4 FUNC GLOBAL DEFAULT [MIPS16] 12 bar
68: 00410848 4 OBJECT GLOBAL DEFAULT 21 foo32p
70: 00410844 4 OBJECT GLOBAL DEFAULT 21 foop
78: 00400684 8 FUNC GLOBAL DEFAULT 12 foo32
80: 00400680 4 FUNC GLOBAL DEFAULT [MIPS16] 12 foo
88: 00410840 4 OBJECT GLOBAL DEFAULT 21 fooi
$
Hmm, no sight of the ISA bit, but notice how foo and bar (but not
foo32!) have been marked as MIPS16 functions (ELF symbol structure's
`st_other' field is used for that).
So let's try to run and poke at this program with GDB. I'll be using a
native system for simplicity (I'll be using ellipses here and there to
remove unrelated clutter):
$ ./foobar
$ echo $?
1
$
So far, so good.
$ gdb ./foobar
[...]
(gdb) break main
Breakpoint 1 at 0x400490: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb)
Yay, it worked! OK, so let's poke at it:
(gdb) print main
$1 = {int (void)} 0x400490 <main>
(gdb) print foo32
$2 = {int (void)} 0x400684 <foo32>
(gdb) print foo32p
$3 = (int (*)(void)) 0x400684 <foo32>
(gdb) print bar
$4 = {int (void)} 0x40068c <bar>
(gdb) print foo
$5 = {int (void)} 0x400680 <foo>
(gdb) print foop
$6 = (int (*)(void)) 0x400681 <foo>
(gdb)
A-ha! Here's the difference and finally the ISA bit!
(gdb) print /x fooi
$7 = 0x400681
(gdb) p/x $pc
p/x $pc
$8 = 0x400491
(gdb)
And here as well...
(gdb) advance foo
foo () at foobar.c:4
4 }
(gdb) disassemble
Dump of assembler code for function foo:
0x00400680 <+0>: jr ra
0x00400682 <+2>: li v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0 foo () at foobar.c:4
main () at foobar.c:24
24 }
Value returned is $9 = 1
(gdb) continue
Continuing.
[Inferior 1 (process 14103) exited with code 01]
(gdb)
So let's be a bit inquisitive...
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb)
Actually we do not like to run foo here at all. Let's run bar instead!
(gdb) set foop = bar
(gdb) print foop
$10 = (int (*)(void)) 0x40068c <bar>
(gdb)
Hmm, no ISA bit. Is it going to work?
(gdb) advance bar
bar () at foobar.c:9
9 }
(gdb) p/x $pc
$11 = 0x40068c
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068c <+0>: jr ra
0x0040068e <+2>: li v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0 bar () at foobar.c:9
Program received signal SIGILL, Illegal instruction.
bar () at foobar.c:9
9 }
(gdb)
Oops!
(gdb) p/x $pc
$12 = 0x40068c
(gdb)
We're still there!
(gdb) continue
Continuing.
Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)
So let's try something else:
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) set foop = foo
(gdb) advance foo
foo () at foobar.c:4
4 }
(gdb) disassemble
Dump of assembler code for function foo:
=> 0x00400680 <+0>: jr ra
0x00400682 <+2>: li v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0 foo () at foobar.c:4
Program received signal SIGILL, Illegal instruction.
foo () at foobar.c:4
4 }
(gdb) continue
Continuing.
Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)
The same problem!
(gdb) run
Starting program:
/net/build2-lucid-cs/scratch/macro/mips-linux-fsf-gcc/isa-bit/foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) set foop = foo32
(gdb) advance foo32
foo32 () at foobar.c:14
14 }
(gdb) disassemble
Dump of assembler code for function foo32:
=> 0x00400684 <+0>: jr ra
0x00400688 <+4>: li v0,3
End of assembler dump.
(gdb) finish
Run till exit from #0 foo32 () at foobar.c:14
main () at foobar.c:24
24 }
Value returned is $14 = 3
(gdb) continue
Continuing.
[Inferior 1 (process 14113) exited with code 03]
(gdb)
That did work though, so it's the ISA bit only!
(gdb) quit
Enough!
That's the tip of the iceberg only though. So let's rebuild the
executable with some dynamic symbols:
$ mips-linux-gnu-gcc -mips16 -Wl,--export-dynamic -g -O2 -o foobar-dyn foobar.c
$ mips-linux-gnu-readelf -s foobar-dyn | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 32 entries:
6: 004009cd 4 FUNC GLOBAL DEFAULT 12 bar
8: 00410b88 4 OBJECT GLOBAL DEFAULT 21 foo32p
9: 00410b84 4 OBJECT GLOBAL DEFAULT 21 foop
15: 004009c4 8 FUNC GLOBAL DEFAULT 12 foo32
17: 004009c1 4 FUNC GLOBAL DEFAULT 12 foo
25: 00410b80 4 OBJECT GLOBAL DEFAULT 21 fooi
Symbol table '.symtab' contains 95 entries:
55: 00000000 0 FILE LOCAL DEFAULT ABS foobar.c
69: 004009cd 4 FUNC GLOBAL DEFAULT 12 bar
71: 00410b88 4 OBJECT GLOBAL DEFAULT 21 foo32p
72: 00410b84 4 OBJECT GLOBAL DEFAULT 21 foop
79: 004009c4 8 FUNC GLOBAL DEFAULT 12 foo32
81: 004009c1 4 FUNC GLOBAL DEFAULT 12 foo
89: 00410b80 4 OBJECT GLOBAL DEFAULT 21 fooi
$
OK, now the ISA bit is there for a change, but the MIPS16 `st_other'
attribute gone, hmm... What does `objdump' do then:
$ mips-linux-gnu-objdump -Tt foobar-dyn | egrep 'SYMBOL|foo|bar'
foobar-dyn: file format elf32-tradbigmips
SYMBOL TABLE:
00000000 l df *ABS* 00000000 foobar.c
004009cc g F .text 00000004 0xf0 bar
00410b88 g O .data 00000004 foo32p
00410b84 g O .data 00000004 foop
004009c4 g F .text 00000008 foo32
004009c0 g F .text 00000004 0xf0 foo
00410b80 g O .data 00000004 fooi
DYNAMIC SYMBOL TABLE:
004009cc g DF .text 00000004 Base 0xf0 bar
00410b88 g DO .data 00000004 Base foo32p
00410b84 g DO .data 00000004 Base foop
004009c4 g DF .text 00000008 Base foo32
004009c0 g DF .text 00000004 Base 0xf0 foo
00410b80 g DO .data 00000004 Base fooi
$
Hmm, the attribute (0xf0, printed raw) is back, and the ISA bit gone
again.
Let's have a look at some DWARF-2 records GDB uses (I'll be stripping
off a lot here for brevity) -- debug info:
$ mips-linux-gnu-readelf -wi foobar
Contents of the .debug_info section:
[...]
Compilation Unit @ offset 0x88:
Length: 0xbb (32-bit)
Version: 4
Abbrev Offset: 62
Pointer Size: 4
<0><93>: Abbrev Number: 1 (DW_TAG_compile_unit)
<94> DW_AT_producer : (indirect string, offset: 0x19e): GNU C 4.8.0 20120513 (experimental) -meb -mips16 -march=mips32r2 -mhard-float -mllsc -mplt -mno-synci -mno-shared -mabi=32 -g -O2
<98> DW_AT_language : 1 (ANSI C)
<99> DW_AT_name : (indirect string, offset: 0x190): foobar.c
<9d> DW_AT_comp_dir : (indirect string, offset: 0x225): [...]
<a1> DW_AT_ranges : 0x0
<a5> DW_AT_low_pc : 0x0
<a9> DW_AT_stmt_list : 0x27
<1><ad>: Abbrev Number: 2 (DW_TAG_subprogram)
<ae> DW_AT_external : 1
<ae> DW_AT_name : foo
<b2> DW_AT_decl_file : 1
<b3> DW_AT_decl_line : 1
<b4> DW_AT_prototyped : 1
<b4> DW_AT_type : <0xc2>
<b8> DW_AT_low_pc : 0x400680
<bc> DW_AT_high_pc : 0x400684
<c0> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<c2> DW_AT_GNU_all_call_sites: 1
<1><c2>: Abbrev Number: 3 (DW_TAG_base_type)
<c3> DW_AT_byte_size : 4
<c4> DW_AT_encoding : 5 (signed)
<c5> DW_AT_name : int
<1><c9>: Abbrev Number: 4 (DW_TAG_subprogram)
<ca> DW_AT_external : 1
<ca> DW_AT_name : (indirect string, offset: 0x18a): foo32
<ce> DW_AT_decl_file : 1
<cf> DW_AT_decl_line : 11
<d0> DW_AT_prototyped : 1
<d0> DW_AT_type : <0xc2>
<d4> DW_AT_low_pc : 0x400684
<d8> DW_AT_high_pc : 0x40068c
<dc> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<de> DW_AT_GNU_all_call_sites: 1
<1><de>: Abbrev Number: 2 (DW_TAG_subprogram)
<df> DW_AT_external : 1
<df> DW_AT_name : bar
<e3> DW_AT_decl_file : 1
<e4> DW_AT_decl_line : 6
<e5> DW_AT_prototyped : 1
<e5> DW_AT_type : <0xc2>
<e9> DW_AT_low_pc : 0x40068c
<ed> DW_AT_high_pc : 0x400690
<f1> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<f3> DW_AT_GNU_all_call_sites: 1
<1><f3>: Abbrev Number: 5 (DW_TAG_subprogram)
<f4> DW_AT_external : 1
<f4> DW_AT_name : (indirect string, offset: 0x199): main
<f8> DW_AT_decl_file : 1
<f9> DW_AT_decl_line : 21
<fa> DW_AT_prototyped : 1
<fa> DW_AT_type : <0xc2>
<fe> DW_AT_low_pc : 0x400490
<102> DW_AT_high_pc : 0x4004a4
<106> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<108> DW_AT_GNU_all_tail_call_sites: 1
[...]
$
-- no sign of the ISA bit anywhere -- frame info:
$ mips-linux-gnu-readelf -wf foobar
[...]
Contents of the .debug_frame section:
00000000 0000000c ffffffff CIE
Version: 1
Augmentation: ""
Code alignment factor: 1
Data alignment factor: -4
Return address column: 31
DW_CFA_def_cfa_register: r29
DW_CFA_nop
00000010 0000000c 00000000 FDE cie=00000000 pc=00400680..00400684
00000020 0000000c 00000000 FDE cie=00000000 pc=00400684..0040068c
00000030 0000000c 00000000 FDE cie=00000000 pc=0040068c..00400690
00000040 00000018 00000000 FDE cie=00000000 pc=00400490..004004a4
DW_CFA_advance_loc: 6 to 00400496
DW_CFA_def_cfa_offset: 32
DW_CFA_offset: r31 at cfa-4
DW_CFA_advance_loc: 6 to 0040049c
DW_CFA_restore: r31
DW_CFA_def_cfa_offset: 0
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop
[...]
$
-- no sign of the ISA bit anywhere -- range info (GDB doesn't use arange):
$ mips-linux-gnu-readelf -wR foobar
Contents of the .debug_ranges section:
Offset Begin End
00000000 00400680 00400690
00000000 00400490 004004a4
00000000 <End of list>
$
-- no sign of the ISA bit anywhere -- line info:
$ mips-linux-gnu-readelf -wl foobar
Raw dump of debug contents of section .debug_line:
[...]
Offset: 0x27
Length: 78
DWARF Version: 2
Prologue Length: 31
Minimum Instruction Length: 1
Initial value of 'is_stmt': 1
Line Base: -5
Line Range: 14
Opcode Base: 13
Opcodes:
Opcode 1 has 0 args
Opcode 2 has 1 args
Opcode 3 has 1 args
Opcode 4 has 1 args
Opcode 5 has 1 args
Opcode 6 has 0 args
Opcode 7 has 0 args
Opcode 8 has 0 args
Opcode 9 has 1 args
Opcode 10 has 0 args
Opcode 11 has 0 args
Opcode 12 has 1 args
The Directory Table is empty.
The File Name Table:
Entry Dir Time Size Name
1 0 0 0 foobar.c
Line Number Statements:
Extended opcode 2: set Address to 0x400681
Special opcode 6: advance Address by 0 to 0x400681 and Line by 1 to 2
Special opcode 7: advance Address by 0 to 0x400681 and Line by 2 to 4
Special opcode 55: advance Address by 3 to 0x400684 and Line by 8 to 12
Special opcode 7: advance Address by 0 to 0x400684 and Line by 2 to 14
Advance Line by -7 to 7
Special opcode 131: advance Address by 9 to 0x40068d and Line by 0 to 7
Special opcode 7: advance Address by 0 to 0x40068d and Line by 2 to 9
Advance PC by 3 to 0x400690
Extended opcode 1: End of Sequence
Extended opcode 2: set Address to 0x400491
Advance Line by 21 to 22
Copy
Special opcode 6: advance Address by 0 to 0x400491 and Line by 1 to 23
Special opcode 60: advance Address by 4 to 0x400495 and Line by -1 to 22
Special opcode 34: advance Address by 2 to 0x400497 and Line by 1 to 23
Special opcode 62: advance Address by 4 to 0x40049b and Line by 1 to 24
Special opcode 32: advance Address by 2 to 0x40049d and Line by -1 to 23
Special opcode 6: advance Address by 0 to 0x40049d and Line by 1 to 24
Advance PC by 7 to 0x4004a4
Extended opcode 1: End of Sequence
[...]
-- a-ha, the ISA bit is there! However it's not always right for some
reason, I don't have a small test case to show it, but here's an excerpt
from MIPS16 libc, a prologue of a function:
00019630 <__libc_init_first>:
19630: e8a0 jrc ra
19632: 6500 nop
00019634 <_init>:
19634: f000 6a11 li v0,17
19638: f7d8 0b08 la v1,15e00 <_DYNAMIC+0x15c54>
1963c: f400 3240 sll v0,16
19640: e269 addu v0,v1
19642: 659a move gp,v0
19644: 64f6 save 48,ra,s0-s1
19646: 671c move s0,gp
19648: d204 sw v0,16(sp)
1964a: f352 984c lw v0,-27828(s0)
1964e: 6724 move s1,a0
and the corresponding DWARF-2 line info:
Line Number Statements:
Extended opcode 2: set Address to 0x19631
Advance Line by 44 to 45
Copy
Special opcode 8: advance Address by 0 to 0x19631 and Line by 3 to 48
Special opcode 66: advance Address by 4 to 0x19635 and Line by 5 to 53
Advance PC by constant 17 to 0x19646
Special opcode 25: advance Address by 1 to 0x19647 and Line by 6 to 59
Advance Line by -6 to 53
Special opcode 33: advance Address by 2 to 0x19649 and Line by 0 to 53
Special opcode 39: advance Address by 2 to 0x1964b and Line by 6 to 59
Advance Line by -6 to 53
Special opcode 61: advance Address by 4 to 0x1964f and Line by 0 to 53
-- see that "Advance PC by constant 17" there? It clears the ISA bit,
however code at 0x19646 is not standard MIPS code at all. For some
reason the constant is always 17, I've never seen DW_LNS_const_add_pc
used with any other value -- is that a binutils bug or what?
3. Solution:
I think we should retain the value of the ISA bit in code references,
that is effectively treat them as cookies as they indeed are (although
trivially calculated) rather than raw memory byte addresses.
In a perfect world both the static symbol table and the respective
DWARF-2 records should be fixed to include the ISA bit in all the cases.
I think however that this is infeasible.
All the uses of `_bfd_mips_elf_symbol_processing' can not necessarily be
tracked down. This function is used by `elf_slurp_symbol_table' that in
turn is used by `bfd_canonicalize_symtab' and
`bfd_canonicalize_dynamic_symtab', which are public interfaces.
Similarly DWARF-2 records are used outside GDB, one notable if a bit
questionable is the exception unwinder (libgcc/unwind-dw2.c) -- I have
identified at least bits in `execute_cfa_program' and
`uw_frame_state_for', both around the calls to `_Unwind_IsSignalFrame',
that would need an update as they effectively flip the ISA bit freely;
see also the comment about MASK_RETURN_ADDR in gcc/config/mips/mips.h.
But there may be more places. Any change in how DWARF-2 records are
produced would require an update there and would cause compatibility
problems with libgcc.a binaries already distributed; given that this is
a static library a complex change involving function renames would
likely be required.
I propose therefore to accept the existing inconsistencies and deal with
them entirely within GDB. I have figured out that the ISA bit lost in
various places can still be recovered as long as we have symbol
information -- that'll have the `st_other' attribute correctly set to
one of standard MIPS/MIPS16/microMIPS encoding.
Here's the resulting change. It adds a couple of new `gdbarch' hooks,
one to update symbol information with the ISA bit lost in
`_bfd_mips_elf_symbol_processing', and two other ones to adjust DWARF-2
records as they're processed. The ISA bit is set in each address
handled according to information retrieved from the symbol table for the
symbol spanning the address if any; limits are adjusted based on the
address they point to related to the respective base address.
Additionally minimal symbol information has to be adjusted accordingly
in its gdbarch hook.
With these changes in place some complications with ISA bit juggling in
the PC that never fully worked can be removed from the MIPS backend.
Conversely, the generic dynamic linker event special breakpoint symbol
handler has to be updated to call the minimal symbol gdbarch hook to
record that the symbol is a MIPS16 or microMIPS address if applicable or
the breakpoint will be set at the wrong address and either fail to work
or cause SIGTRAPs (this is because the symbol is handled early on and
bypasses regular symbol processing).
4. Results obtained
The change fixes the example above -- to repeat only the crucial steps:
(gdb) break main
Breakpoint 1 at 0x400491: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) print foo
$1 = {int (void)} 0x400681 <foo>
(gdb) set foop = bar
(gdb) advance bar
bar () at foobar.c:9
9 }
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068d <+0>: jr ra
0x0040068f <+2>: li v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0 bar () at foobar.c:9
main () at foobar.c:24
24 }
Value returned is $2 = 2
(gdb) continue
Continuing.
[Inferior 1 (process 14128) exited with code 02]
(gdb)
-- excellent!
The change removes about 90 failures per MIPS16 multilib in mips-sde-elf
testing too, results for MIPS16 are now similar to that for standard
MIPS; microMIPS results are a bit worse because of host-I/O problems in
QEMU used instead of MIPSsim for microMIPS testing only:
=== gdb Summary ===
# of expected passes 14299
# of unexpected failures 187
# of expected failures 56
# of known failures 58
# of unresolved testcases 11
# of untested testcases 52
# of unsupported tests 174
MIPS16:
=== gdb Summary ===
# of expected passes 14298
# of unexpected failures 187
# of unexpected successes 2
# of expected failures 54
# of known failures 58
# of unresolved testcases 12
# of untested testcases 52
# of unsupported tests 174
microMIPS:
=== gdb Summary ===
# of expected passes 14149
# of unexpected failures 201
# of unexpected successes 2
# of expected failures 54
# of known failures 58
# of unresolved testcases 7
# of untested testcases 53
# of unsupported tests 175
2014-12-12 Maciej W. Rozycki <macro@codesourcery.com>
Maciej W. Rozycki <macro@mips.com>
Pedro Alves <pedro@codesourcery.com>
gdb/
* gdbarch.sh (elf_make_msymbol_special): Change type to `F',
remove `predefault' and `invalid_p' initializers.
(make_symbol_special): New architecture method.
(adjust_dwarf2_addr, adjust_dwarf2_line): Likewise.
(objfile, symbol): New declarations.
* arch-utils.h (default_elf_make_msymbol_special): Remove
prototype.
(default_make_symbol_special): New prototype.
(default_adjust_dwarf2_addr): Likewise.
(default_adjust_dwarf2_line): Likewise.
* mips-tdep.h (mips_unmake_compact_addr): New prototype.
* arch-utils.c (default_elf_make_msymbol_special): Remove
function.
(default_make_symbol_special): New function.
(default_adjust_dwarf2_addr): Likewise.
(default_adjust_dwarf2_line): Likewise.
* dwarf2-frame.c (decode_frame_entry_1): Call
`gdbarch_adjust_dwarf2_addr'.
* dwarf2loc.c (dwarf2_find_location_expression): Likewise.
* dwarf2read.c (create_addrmap_from_index): Likewise.
(process_psymtab_comp_unit_reader): Likewise.
(add_partial_symbol): Likewise.
(add_partial_subprogram): Likewise.
(process_full_comp_unit): Likewise.
(read_file_scope): Likewise.
(read_func_scope): Likewise. Call `gdbarch_make_symbol_special'.
(read_lexical_block_scope): Call `gdbarch_adjust_dwarf2_addr'.
(read_call_site_scope): Likewise.
(dwarf2_ranges_read): Likewise.
(dwarf2_record_block_ranges): Likewise.
(read_attribute_value): Likewise.
(dwarf_decode_lines_1): Call `gdbarch_adjust_dwarf2_line'.
(new_symbol_full): Call `gdbarch_adjust_dwarf2_addr'.
* elfread.c (elf_symtab_read): Don't call
`gdbarch_elf_make_msymbol_special' if unset.
* mips-linux-tdep.c (micromips_linux_sigframe_validate): Strip
the ISA bit from the PC.
* mips-tdep.c (mips_unmake_compact_addr): New function.
(mips_elf_make_msymbol_special): Set the ISA bit in the symbol's
address appropriately.
(mips_make_symbol_special): New function.
(mips_pc_is_mips): Set the ISA bit before symbol lookup.
(mips_pc_is_mips16): Likewise.
(mips_pc_is_micromips): Likewise.
(mips_pc_isa): Likewise.
(mips_adjust_dwarf2_addr): New function.
(mips_adjust_dwarf2_line): Likewise.
(mips_read_pc, mips_unwind_pc): Keep the ISA bit.
(mips_addr_bits_remove): Likewise.
(mips_skip_trampoline_code): Likewise.
(mips_write_pc): Don't set the ISA bit.
(mips_eabi_push_dummy_call): Likewise.
(mips_o64_push_dummy_call): Likewise.
(mips_gdbarch_init): Install `mips_make_symbol_special',
`mips_adjust_dwarf2_addr' and `mips_adjust_dwarf2_line' gdbarch
handlers.
* solib.c (gdb_bfd_lookup_symbol_from_symtab): Get
target-specific symbol address adjustments.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
2014-12-12 Maciej W. Rozycki <macro@codesourcery.com>
gdb/testsuite/
* gdb.base/func-ptrs.c: New file.
* gdb.base/func-ptrs.exp: New file.
A helper function called `add_offset_16' is used by
`extended_mips16_next_pc' to calculate branch destinations. Weirdly
enough the helper does not do what the name suggests and rather than
doing its work for a 16-bit immediate branch offset it makes its
calculations on a 26-bit immediate target used by JAL and JALX
instructions. Furthermore the JAL/JALX calculation is only needed once
by `extended_mips16_next_pc' while a 16-bit branch offset calculation
is made inline several times across `extended_mips16_next_pc'.
This change therefore replaces the contents of `add_offset_16' with the
16-bit branch offset calculation and updates `extended_mips16_next_pc'
accordingly.
* mips-tdep.c (add_offset_16): Rewrite to implement what the
name implies.
(extended_mips16_next_pc): Update accordingly.
This change addresses a regression in gdb.dwarf2/dw2-skip-prologue.exp
across MIPS16 multilibs:
(gdb) file .../gdb.dwarf2/dw2-skip-prologue
Reading symbols from .../gdb.d/gdb.dwarf2/dw2-skip-prologue...done.
(gdb) delete breakpoints
(gdb) info breakpoints
No breakpoints or watchpoints.
(gdb) break main
warning: Breakpoint address adjusted from 0x00400725 to 0x00400721.
Breakpoint 1 at 0x400721
(gdb) set remotetimeout 5
(gdb) kill
The program is not being run.
(gdb)
[...]
target remote ...:2345
Reading symbols from .../mips16/lib/ld.so.1...done.
warning: Breakpoint address adjusted from 0x00400725 to 0x00400721.
warning: Breakpoint address adjusted from 0x00400725 to 0x00400721.
0x2aaa8e81 in __start () from .../mips16/lib/ld.so.1
(gdb) continue
Continuing.
warning: Breakpoint address adjusted from 0x00400725 to 0x00400721.
warning: Breakpoint 1 address previously adjusted from 0x00400725 to
0x00400721.
Breakpoint 1, 0x00400721 in main ()
(gdb) break func
Breakpoint 2 at 0x4006a1: func. (2 locations)
(gdb) continue
Continuing.
warning: GDB can't find the start of the function at 0x4006dd.
GDB is unable to find the start of the function at 0x4006dd
and thus can't determine the size of that function's stack frame.
This means that GDB may be unable to access that stack frame, or
the frames below it.
This problem is most likely caused by an invalid program counter or
stack pointer.
However, if you think GDB should simply search farther back
from 0x4006dd for code which looks like the beginning of a
function, you can increase the range of the search using the `set
heuristic-fence-post' command.
Program received signal SIGBUS, Bus error.
0x0040072b in main ()
(gdb) FAIL: gdb.dwarf2/dw2-skip-prologue.exp: continue to breakpoint: func
-- notice the breakpoint adjustment messages that are already a bad
sign. These happen when a breakpoint is requested in a branch delay
slot and are not supposed to happen unless explicitly requested with an
address pointing to a branch delay slot instruction. No symbol or line
debug information is supposed to direct GDB to place a breakpoint in a
delay slot.
Here's how `main' looks like:
00400718 <main>:
400718: 64f5 save 40,ra,s0-s1
40071a: 1a00 01a8 jal 4006a0 <func>
40071e: 0104 addiu s1,sp,16
400720: 1a00 01b7 jal 4006dc <func+0x3c>
400724: 6702 move s0,v0
400726: e049 addu v0,s0,v0
400728: 65b9 move sp,s1
40072a: 6473 restore 24,ra,s0-s1
40072c: e8a0 jrc ra
40072e: 6500 nop
-- so 0x400725 is the MIPS16 instruction address of the first MOVE
instruction seen above, in a delay slot of the preceding JAL instruction
indeed. This test case arranges for `main' to have no debug information
so it is one of the heuristic prologue scanners, `mips16_scan_prologue'
specifically in this case, that is responsible for finding the right
location for the breakpoint to place.
In this case the prologue really ends with the ADDIU instruction,
reordered into the delay slot of the first JAL instruction. Of course
we can't place the breakpoint for `main' after it as by doing so we'll
let `func' to be called before hitting this breakpoint. So the
breakpoint has to go at the JAL instruction instead, or 0x40071b.
To make a general case out of it we must never consider any jump or
branch instruction to be a part of a function's prologue. In the
presence of a jump or branch at the beginning of a function the furthest
instruction examined for the purpose of constructing frame information
can be one in the delay slot of that jump or branch if present, and
otherwise -- that is when the jump or branch is compact and has no delay
slot -- the instruction immediately preceding the jump or branch.
This change implements that approach across prologue scanners for the
three instruction ISAs. In implementing it I have factored out code
from the existing `*_instruction_has_delay_slot' handlers to be shared
and a side effect for the microMIPS implementation is it now always
fetches the second 16-bit halfword of 32-bit instructions even if it
eventually is not going to be needed. I think it's an acceptable
tradeoff for the purpose of code sharing.
To make things more consistent I also carried logic from
`micromips_scan_prologue' over to the other two scanners to accept (and
ignore) a single non-prologue non-control transfer instruction reordered
by the compiler into the prologue. While doing this I simplified the
exit path from the scan loop such that `end_prologue_addr' is set only
once. This made some concerns expressed in comments no longer
applicable, although even before they were not valid.
I have not fixed the logic around `load_immediate_bytes' in
`mips32_scan_prologue' though, it remains broken, although I took care
not to break it more. An approach similar to one taken for handling
larger stack adjustments in `micromips_scan_prologue' will have to be
eventually implemented here.
For regression testing I used my usual choice of the mips-linux-gnu
target and the following multilibs:
-EB
-EB -msoft-float
-EB -mips16
-EB -mips16 -msoft-float
-EB -mmicromips
-EB -mmicromips -msoft-float
-EB -mabi=n32
-EB -mabi=n32 -msoft-float
-EB -mabi=64
-EB -mabi=64 -msoft-float
and the -EL variants of same.
That removed gdb.dwarf2/dw2-skip-prologue.exp failures across MIPS16
multilibs, the test log now shows:
(gdb) file .../gdb.dwarf2/dw2-skip-prologue
Reading symbols from .../gdb.d/gdb.dwarf2/dw2-skip-prologue...done.
(gdb) delete breakpoints
(gdb) info breakpoints
No breakpoints or watchpoints.
(gdb) break main
Breakpoint 1 at 0x40071b
(gdb) set remotetimeout 5
(gdb) kill
The program is not being run.
(gdb)
[...]
target remote ...:2345
Reading symbols from .../mips16/lib/ld.so.1...done.
0x2aaa8e81 in __start () from .../mips16/lib/ld.so.1
(gdb) continue
Continuing.
Breakpoint 1, 0x0040071b in main ()
(gdb) break func
Breakpoint 2 at 0x4006a1: func. (2 locations)
(gdb) continue
Continuing.
Breakpoint 2, func (param=0) at main.c:5
5 This program is free software; you can redistribute it and/or modify
(gdb) PASS: gdb.dwarf2/dw2-skip-prologue.exp: continue to breakpoint: func
-- so things look like intended.
That also did regress, again across MIPS16 multilibs, another test case,
gdb.base/step-symless.exp:
(gdb) file .../gdb.d/gdb.base/step-symless
Reading symbols from .../gdb.base/step-symless...done.
(gdb) delete breakpoints
(gdb) info breakpoints
No breakpoints or watchpoints.
(gdb) break main
Breakpoint 1 at 0x4006d3
(gdb) set remotetimeout 5
(gdb) kill
The program is not being run.
(gdb)
[...]
target remote ...:2345
Reading symbols from .../mips16/lib/ld.so.1...done.
0x2aaa8e81 in __start () from .../mips16/lib/ld.so.1
(gdb) continue
Continuing.
Breakpoint 1, 0x004006d3 in main ()
(gdb) break symful
Breakpoint 2 at 0x4006a5
(gdb) step
Single stepping until exit from function main,
which has no line number information.
warning: GDB can't find the start of the function at 0x4006b9.
GDB is unable to find the start of the function at 0x4006b9
and thus can't determine the size of that function's stack frame.
This means that GDB may be unable to access that stack frame, or
the frames below it.
This problem is most likely caused by an invalid program counter or
stack pointer.
However, if you think GDB should simply search farther back
from 0x4006b9 for code which looks like the beginning of a
function, you can increase the range of the search using the `set
heuristic-fence-post' command.
0x004006b9 in ?? ()
(gdb) FAIL: gdb.base/step-symless.exp: step
-- but that is actually a good sign. Here `main', again, has no debug
information and code involved looks like:
004006a0 <symful>:
4006a0: 6491 save 8,s1
4006a2: 673d move s1,sp
4006a4: b204 lw v0,4006b4 <symful+0x14>
4006a6: 9a40 lw v0,0(v0)
4006a8: 4261 addiu v1,v0,1
4006aa: b203 lw v0,4006b4 <symful+0x14>
4006ac: da60 sw v1,0(v0)
4006ae: 65b9 move sp,s1
4006b0: 6411 restore 8,s1
4006b2: e8a0 jrc ra
4006b4: 0041 addiu s0,sp,260
4006b6: 0860 la s0,400834 <__libc_start_main@mips16plt+0x54>
4006b8: 6491 save 8,s1
4006ba: 673d move s1,sp
4006bc: b204 lw v0,4006cc <symful+0x2c>
4006be: 9a40 lw v0,0(v0)
4006c0: 4261 addiu v1,v0,1
4006c2: b203 lw v0,4006cc <symful+0x2c>
4006c4: da60 sw v1,0(v0)
4006c6: 65b9 move sp,s1
4006c8: 6411 restore 8,s1
4006ca: e8a0 jrc ra
4006cc: 0041 addiu s0,sp,260
4006ce: 0860 la s0,40084c <__libc_start_main@mips16plt+0x6c>
004006d0 <main>:
4006d0: 64d4 save 32,ra,s1
4006d2: 1a00 01ae jal 4006b8 <symful+0x18>
4006d6: 0104 addiu s1,sp,16
4006d8: 1a00 01a8 jal 4006a0 <symful>
4006dc: 6500 nop
4006de: 6740 move v0,zero
4006e0: 65b9 move sp,s1
4006e2: 6452 restore 16,ra,s1
4006e4: e8a0 jrc ra
4006e6: 6500 nop
4006e8: 6500 nop
4006ea: 6500 nop
4006ec: 6500 nop
4006ee: 6500 nop
-- and the original log:
(gdb) file .../gdb.base/step-symless
Reading symbols from .../gdb.base/step-symless...done.
(gdb) delete breakpoints
(gdb) info breakpoints
No breakpoints or watchpoints.
(gdb) break main
warning: Breakpoint address adjusted from 0x004006dd to 0x004006d9.
Breakpoint 1 at 0x4006d9
(gdb) set remotetimeout 5
(gdb) kill
The program is not being run.
(gdb)
[...]
target remote ...:2345
Reading symbols from .../mips16/lib/ld.so.1...done.
warning: Breakpoint address adjusted from 0x004006dd to 0x004006d9.
warning: Breakpoint address adjusted from 0x004006dd to 0x004006d9.
0x2aaa8e81 in __start () from .../mips16/lib/ld.so.1
(gdb) continue
Continuing.
warning: Breakpoint address adjusted from 0x004006dd to 0x004006d9.
warning: Breakpoint 1 address previously adjusted from 0x004006dd to
0x004006d9.
Breakpoint 1, 0x004006d9 in main ()
(gdb) break symful
Breakpoint 2 at 0x4006a5
(gdb) step
Single stepping until exit from function main,
which has no line number information.
Breakpoint 2, 0x004006a5 in symful ()
(gdb) PASS: gdb.base/step-symless.exp: step
So the breakpoint at `main' was actually set at an instruction after the
call to `symful+0x18' aka `symless' and the test only passed because
single-stepping through `symless' wasn't actually done at all. With
this change in place this test fails for MIPS16 multilibs consistently
with all the other multilibs where it already failed in this manner
previously.
* mips-tdep.c (mips16_instruction_is_compact_branch): New
function.
(micromips_instruction_is_compact_branch): Likewise.
(mips16_scan_prologue): Terminate scanning upon seeing a branch
or a compact jump, reaching a jump delay slot, or seeing a
second non-prologue instruction.
(micromips_scan_prologue): Also terminate scanning upon seeing a
compact branch or jump, or reaching a branch or jump delay slot.
(mips32_scan_prologue): Terminate scanning upon reaching a branch
or jump delay slot, or seeing a second non-prologue instruction.
(mips32_instruction_has_delay_slot): Retain instruction
examination code only, update arguments accordingly and move
instruction fetch pieces to...
(mips32_insn_at_pc_has_delay_slot): ... this new function.
(micromips_instruction_has_delay_slot): Likewise and to...
(micromips_insn_at_pc_has_delay_slot): ... this new function.
(mips16_instruction_has_delay_slot): Likewise and to...
(mips16_insn_at_pc_has_delay_slot): ... this new function.
(mips_single_step_through_delay): Update accordingly.
(mips_adjust_breakpoint_address): Likewise.
This change addresses `micromips_instruction_has_delay_slot' and
`mips16_instruction_has_delay_slot' that both incorrectly interpret
their MUSTBE32 argument. Their callers assume that when the flag is
clear these functions will return 1 when any non-compact jump or branch
instruction is present at ADDR, while in fact they will only return 1
for 16-bit such instructions only. This change makes the implementation
match the expectations.
* mips-tdep.c (micromips_instruction_has_delay_slot): When
!mustbe32 also return 1 for 32-bit instructions.
(mips16_instruction_has_delay_slot): Likewise. Add an
explanatory comment.
John Baldwin