The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold them
as far as possible. Further folding is possible, but needs other prereq
work done first.
They aren't really useful (anymore?): The conflicting operand size check
isn't applicable to any insn validly using respective memory operand
sizes (and if they're used wrongly, another error would result), and the
logic in process_suffix() can be easily changed to work without them.
While re-structuring conditionals in process_suffix() also drop the
CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode
table.
Neither touches any XMM register, so the check is pointless. It is imo
even questionable whether in SSE2AVX mode the two should be converted to
their AVX counterparts.
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
xcoff (32-bit) objdump accepted but ignored -M options unless
-mpowerpc was also given. This patch fixes that, leaving the default
as -Mpwr for xcoff. I've also enabled more tests for xcoff targets.
binutils/
* configure.ac: Add objdump_private_desc_xcoff for rs6000.
* configure: Regenerate.
gas/
* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
* testsuite/gas/ppc/machine.d: Don't run for PE targets.
opcodes/
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
bfd_arch_rs6000.
* disassemble.h (print_insn_rs6000): Delete.
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
(print_insn_rs6000): Delete.
Among the macros to manipulate an arm_feature_set structure is the
ARM_FEATURE_COPY which copy the value of a feature set into another.
This can be achieved with a simple assignement which most of the
existing code does. This patch removes the last 2 uses of that macro and
remove the macro altogether.
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
include/
* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
opcodes/
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
macro by assignements.
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
gcc8 complains wrongly about the buffer not being large enough, at
least at -Og optimization.
* crx-dis.c (getregliststring): Allocate a large enough buffer
to silence false positive gcc8 warning.
Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible. Note that this differs from the rex
prefix which generates REX prefix unconditionally.
gas/
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
opcodes/
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
The `M' and `m' MIPS16 operand codes are functionally the same, denoting
a 7-bit register list that is encoded the same way for both SAVE and
RESTORE. Use `m' for both instructions then, making `M' available for a
different use.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
(mips16_opcodes): Replace `M' with `m' for "restore".
include/
* opcode/mips.h: Remove `M' operand code.
Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is
not set in the disassembler entry mask. This commit fixes that.
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
opcodes/
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../bfd/wasm-module.c: In function 'wasm_scan_name_function_section':
.../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_register_section':
.../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position':
.../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
and:
cc1: warnings being treated as errors
.../opcodes/wasm32-dis.c: In function 'print_insn_wasm32':
.../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [wasm32-dis.lo] Error 1
which for versions of GCC before 4.8 prevent support for the WebAssembly
target from being built. See also GCC PR c/53066.
bfd/
* wasm-module.c (wasm_scan_name_function_section): Rename
`index' local variable to `idx'.
opcodes/
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
variable to `function_index'.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
gas/
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
opcodes/
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
Just like their packed counterparts the memory operand is always 16
bytes wide, and the Disp8 scaling is the same for all of them. (As a
side note: I'm also surprised by there being AVX512VL variants of
these as well as the AVX512_4VNNIW ones - the SDM doesn't define any
such.)
Adjust the test cases also for the packed forms to actually live up to
their promise of testing correct Disp8 encoding.
gas/
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
opcodes/
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.
OK? If so, please commit on my behalf as I don't have commit rights
over here.
Thanks, James
---
opcodes/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
gas/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
CSDB is a new instruction which Arm has defined. It has the same encoding as
HINT #0x14 and is available at all architecture levels.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB.
For historical reason, we allow movd/vmovd with 64-bit register and
memeory operands. But for vmovd, we failed to handle 64-bit memeory
operand. This has been gone unnoticed since AT&T syntax always treats
memory operand as 32-bit memory. This patch properly encodes vmovd
with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit
operands since GCC has
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_DI:
/* Handle broken assemblers that require movd instead of movq. */
if (!HAVE_AS_IX86_INTERUNIT_MOVQ
&& (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't
generate AVX512 vmovd with 64-bit operand.
gas/
PR gas/22681
* testsuite/gas/i386/i386.exp: Run x86-64-movd and
x86-64-movd-intel.
* testsuite/gas/i386/x86-64-movd-intel.d: New file.
* testsuite/gas/i386/x86-64-movd.d: Likewise.
* testsuite/gas/i386/x86-64-movd.s: Likewise.
opcodes/
PR gas/22681
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
Remove AVX512 vmovd with 64-bit operands.
* i386-tbl.h: Regenerated.
Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM
and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update
i386-init.h though, as it mistakenly wasn't updated by the original
commit.
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:
v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.
Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.
gas/
PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
include/
PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
opcodes/
PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.
Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.
With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.
gas/
PR gas/22529
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
* gas/testsuite/gas/aarch64/pr22529.s: New.
* gas/testsuite/gas/aarch64/pr22529.d: New.
* gas/testsuite/gas/aarch64/pr22529.l: New.
include/
PR gas/22529
* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.
opcodes/
PR gas/22529
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
They are relevant only when multiple operands permit registers:
operand_type_register_match() returns true if either operand is not a
register one. IOW
grep -i CheckRegSize i386-opc.tbl | grep -Ev "(Reg[8136]|Acc).*,.*(Reg|Acc)"
should produce no output.
opcodes * disassemble.c: Enable disassembler_needs_relocs for PRU.
gas * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM
relocation.
* testsuite/gas/pru/extern.d: New test driver.
When checking mapping symbols backwardly, the section which defines the symbol
is not considerted. This patch fixes this by moving the section checking code
into get_sym_code_type () function which is shared by forward and backword
mapping symbol searching.
opcodes/
2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
Renlin Li <renlin.li@arm.com>
* aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
(get_sym_code_type): Here.
binutils/
2017-12-11 Renlin Li <renlin.li@arm.com>
* testsuite/binutils-all/aarch64/objdump.d: New.
* testsuite/binutils-all/aarch64/objdump.s: New.
BaseIndex implies - with the exception of string instructions the
optional presence of a displacement. This is almost completely uniform
for all instructions (the sole exception being MPX ones, which don't
allow 16-bit addressing and hence Disp16), so there's no point in
explicitly stating this in the main opcode table. Drop those explict
specifications in favor of adding logic to i386-gen, shrinking the
table size quite a bit and hence making it more readable.
The opcodes/i386-tbl.h changes are due to a few cases where pointless
Disp* still hadn't been removed from their insns.
bfd/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
binutils/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gas/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gold/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gprof/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
ld/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
opcodes/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.
Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.
For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a
into a new flag order to distinguish them from the rest of the already existing optional
FP16 instructions in Armv8.2-a.
The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on
Armv8.4-a.
gas/
* config/tc-aarch64.c (fp16fml): New.
* doc/c-aarch64.texi (fp16fml): New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml.
* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml.
include/
* opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New.
(AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default.
opcodes/
* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
and AARCH64_FEATURE_F16.
The crypto options depend on SIMD and FP, the documentation states so but the dependency is not there the code.
We have mostly gotten away with this due to the default flags
for the architectures (e.g. Armv8.2-a implies +simd) but this
discrepancy needs to be addressed.
gas/
2017-11-16 Tamar Christina <tamar.christina@arm.com>
* opcodes/aarch64-tbl.h
(aarch64_feature_crypto): Add ARCH64_FEATURE_SIMD and AARCH64_FEATURE_FP.
(aarch64_feature_crypto_v8_2, aarch64_feature_sm4): Likewise.
(aarch64_feature_sha3): Likewise.
While commits 9889cbb14e ("Check invalid mask registers") and
abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a
bit into the right direction, this wasn't quite enough:
- VEX.vvvv has its high bit ignored
- EVEX.vvvv has its high bit ignored together with EVEX.v'
- the high bits of {,E}VEX.vvvv should not be prematurely zapped, to
allow proper checking of them when the fields has to hold al ones
- when the high bits of an immediate specify a register, bit 7 is
ignored
VEX.W may be legitimately set (and is then ignored by the CPU) for
non-64-bit code. Don't print 64-bit register names in such a case, by
utilizing that REX_W would never be set for non-64-bit code, and that
it is being set from VEX.W by generic decoding.
A test for this is going to be introduced in the next patch of this
series.
The low four bits of an immediate being set when the high bits specify a
fourth register operand is not a problem: CPUs ignore these bits rather
than raising #UD. Take care of incrementing codep in OP_EX_VexW()
instead.
Just like %cxl can't be used as shift count register. Otherwise for
consistency %cxl would need to gain "ShiftCount" and use of both ought
to properly cause REX prefixes to be emitted.
Just like is the case for xsave{s,c}64 and xrstors64 already. I wonder
though why xsave{s,c} and xrstors don't allow for the q suffix, other
than the other insns without the "64" suffix do.
The new options are:
+aes: Enables the AES instructions of Armv8-a,
enabled by default with +crypto.
+sha2: Enables the SHA1 and SHA2 instructions of Armv8-a,
enabled by default with +crypto.
These options have been turned on by default when +crypto
is used, as such no breakage is expected.
The reason for the split is because with the introduction of Armv8.4-a
the implementation of AES has explicitly been made independent of the
implementation of the other crypto extensions. Backporting the split does
not break any of the previous requirements and so is safe to do.
gas * config/tc-aarch64.c
(aarch64_features): Include AES and SHA2 in CRYPTO.
Add SHA2 and AES.
include * opcode/aarch64.h:
(AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New.
opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
(aarch64_feature_sha2, aarch64_feature_aes): New.
(SHA2, AES): New.
(AES_INSN, SHA2_INSN): New.
(pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
(sha1h, sha1su1, sha256su0, sha1c, sha1p,
sha1m, sha1su0, sha256h, sha256h2, sha256su1):
Change to SHA2_INS.
gas * config/tc-arm.c (arm_extensions):
(arm_archs): New entry for "armv8.4-a".
Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
(arm_ext_v8_2): New variable.
(enum arm_reg_type): New enumeration REG_TYPE_NSD.
(reg_expected_msgs): New entry for REG_TYPE_NSD.
(parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
(parse_scalar): Support REG_TYPE_VFS.
(enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
(parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
(NEON_SHAPE_DEF): New entries for DHH and DHS.
(neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
for new FP16 instructions in ARMv8.2-A.
(do_neon_fmac_maybe_scalar_long): New function to encode new FP16
instructions in ARMv8.2-A.
(do_neon_vfmal): Wrapper function for vfmal.
(do_neon_vfmsl): Wrapper function for vfmsl.
(insns): New entries for vfmal and vfmsl.
* doc/c-arm.texi (-march): Document "armv8.4-a".
* testsuite/gas/arm/dotprod-mandatory.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16.d: New test.
* testsuite/gas/arm/armv8_3-a-fp16.d: New test.
* testsuite/gas/arm/armv8_4-a-fp16.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.
opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
FP16 instructions, including vfmal.f16 and vfmsl.f16.
include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
(ARM_EXT2_V8_4A): New macro.
(ARM_AEXT2_V8_4A): Likewise.
(ARM_ARCH_V8_4A): Likewise.
A small number of NPS400 instruction incorrectly used NONE as an
insn_class_t, which would trigger a build warning. Fixed by changing to
MISC.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
binutils has lacked proper pluralization of output messages for a long
time, for example, readelf will display information about a section
that "contains 1 entries" or "There are 1 section headers". Fixing
this properly requires us to use ngettext, because other languages
have different rules to English.
This patch defines macros for ngettext and friends to handle builds
with --disable-nls, and tidies the existing nls support. I've
redefined gettext rather than just defining "_" as dgettext in bfd and
opcodes in case someone wants to use gettext there (which might
conceivably happen with generated code).
bfd/
* sysdep.h: Formatting, comment fixes.
(gettext, ngettext): Redefine when ENABLE_NLS.
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
(_): Define using gettext.
(textdomain, bindtextdomain): Use safer "do nothing".
* hosts/alphavms.h (textdomain, bindtextdomain): Likewise.
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
opcodes/
* opintl.h: Formatting, comment fixes.
(gettext, ngettext): Redefine when ENABLE_NLS.
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
(_): Define using gettext.
(textdomain, bindtextdomain): Use safer "do nothing".
binutils/
* sysdep.h (textdomain, bindtextdomain): Use safer "do nothing".
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
gas/
* asintl.h (textdomain, bindtextdomain): Use safer "do nothing".
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
gold/
* system.h (textdomain, bindtextdomain): Use safer "do nothing".
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
ld/
* ld.h (textdomain, bindtextdomain): Use safer "do nothing".
(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
Force printing of the short/signed values using hexadecimal
representation via disassembler option.
opcode/
2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_hex): New variable.
(parse_option): Check for hex option.
(print_insn_arc): Use hexadecimal representation for short
immediate values when requested.
(print_arc_disassembler_options): Add hex option to the list.
binutils/
2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
* doc/binutils.texi (ARC): Update disassembler options.
* testsuite/binutils-all/arc/hexprint.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Test hex printing feature.
These are all invalid instructions, so they should not disassemble.
opcodes/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (match_c_addi16sp) : New function.
(match_c_addi4spn): New function.
(match_c_lui): Don't allow 0-immediate encodings.
(riscv_opcodes) <addi>: Use the above functions.
<add>: Likewise.
<c.addi4spn>: Likewise.
<c.addi16sp>: Likewise.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-addi16sp-fail.d: New test.
testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
testsuite/gas/riscv/riscv.exp: Add new tests.
FT32B is a new FT32 family member. It has a code
compression scheme, which requires the use of linker
relaxations. The change is quite large, so submission
is in several parts.
Part 1 adds a 15-bit instruction field, and CPU-specific functions for
the code compression that are used in binutils and GDB.
bfd/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-ft32.c: Add HOWTO R_FT32_15.
* reloc.c: Add BFD_RELOC_FT32_15.
gas/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with
K15.
(md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15.
include/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* elf/ft32.h: Add R_FT32_15.
* opcode/ft32.h: Replace FT32_FLD_K8 with K15.
(ft32_shortcode, sc_compar, ft32_split_shortcode,
ft32_merge_shortcode, ft32_merge_shortcode): New functions.
opcodes/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
* opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
K15. Add jmpix pattern.
sim/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
prno, tpei, and irbm are missing in the optable.
gas/ChangeLog:
2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-arch12.d (prno, tpei, irbm): New
instructions added.
* testsuite/gas/s390/zarch-arch12.s: Likewise.
* testsuite/gas/s390/zarch-z13.d: Rename ppno to prno.
opcodes/ChangeLog:
2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt (prno, tpei, irbm): New instructions added.
The recent POP adjusted a few of the instruction formats. This patch
adjusts our optable accordingly. No user visible change - hopefully.
opcodes/ChangeLog:
2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
* s390-opc.c (INSTR_SI_RD): New macro.
(INSTR_S_RD): Adjust example instruction.
* s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
SI_RD.
opcodes/
* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
VLE multimple load/store instructions. Old e_ldm* variants are
kept as aliases.
Add missing e_lmvmcsrrw and e_stmvmcsrrw.
gas/
* testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
support for the VLE multiple load/store instructions.
* testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
driver.
* testsuite/gas/ppc/ppc.exp: Run it.
PR 22179
opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
names for the fmv.x.s and fmv.s.x instructions respectively.
gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
renamed fmv.x.s and fmv.s.x instructions.
* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
From PR 22123:
The common opcodes of emac and mac seem to be only implemented for mac.
To reproduce:
echo "macw %d3l,%a0l" > /tmp/dummy.S
m68k-unknown-elf-as -m5208 /tmp/dummy.S
Outputs something like:
/tmp/dummy.S: Assembler messages:
/tmp/dummy.S:1: Error: operands mismatch -- statement `macw %d3l,%a0l' ignored
This behavior occurs only if the CPU supports only emac but not explicitly mac (but emac is a superset of mac).
Hi,
While compiling GDB using a mingw compiler from Fedora 26:
../gdb/configure --host=x86_64-w64-mingw32 --target=x86_64-w64-mingw32 \
--disable-binutils --disable-ld --disable-gold --disable-gas --disable-sim \
--disable-gprof --enable-targets=all
I stumbled upon a simple occurrence of -Werror=maybe-uninitialized:
../../gdb/opcodes/aarch64-opc.c: In function 'expand_fp_imm':
../../gdb/opcodes/aarch64-opc.c:2880:10: error: 'imm' may be used uninitialized in this function [-Werror=maybe-uninitialized]
return imm;
^~~
It is the compiler's fault, because this function always assigns to
'imm' if the necessary conditions are met, and it calls "assert (0)"
otherwise, but I thought it'd be clearer to have 'imm' explicitly set
to zero anyway.
opcodes/ChangeLog:
2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
* aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
Since the NOTRACK prefix is no longer required to be the last prefix
before the REX prefix, restriction on the NOTRACK prefix position is
removed from assembler as well as disassembler. Assembler encodes the
NOTRACK prefix the same way as the DS segment register, which places
it before other prefixes. Disassembler displays prefixes in the order
they appear.
gas/
* config/tc-i386.c (NOTRACK_PREFIX): Removed.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(parse_insn): Remove restriction on NOTRACK prefix position.
* testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix
before other prefixes.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK
prefix before other prefixes.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
* testsuite/gas/i386/notrack-intel.d: Updated.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
opcodes/
* i386-dis.c (last_active_prefix): Removed.
(ckprefix): Don't set last_active_prefix.
(NOTRACK_Fixup): Don't check last_active_prefix.
For opcode fields that are not addresses, display as
integers instead of using print_address_func.
opcodes/ChangeLog:
2017-08-31 James Bowman <james.bowman@ftdichip.com>
* ft32-dis.c (print_insn_ft32): Correct display of non-address
fields.
* ppc-opc.c: Formatting and comment fixes. Move insert and
extract functions earlier, deleting forward declarations.
(insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
RA_MASK.
This fixes "-M noaliases" disassembly for "c.nop", which is an alias for
"c.addi x0, 0".
opcodes/ChangeLog
2017-08-01 Palmer Dabbelt <palmer@dabbelt.com>
* riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
Fix build on x86:
opcodes/disassemble.c: In function ‘disassembler’:
opcodes/disassemble.c:113:52: error: unused parameter ‘big’ [-Werror=unused-parameter]
disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach,
^~~
opcodes/disassemble.c:113:71: error: unused parameter ‘mach’ [-Werror=unused-parameter]
disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach,
^~~~
cc1: all warnings being treated as errors
* disassemble.c (disassembler): Mark big and mach with
ATTRIBUTE_UNUSED.
Fix `set architecture' and `set endian' command disassembly regressions
from commit 39503f8242 ("Delegate opcodes to select disassembler in
GDB"), and commit 003ca0fd22 ("Refactor disassembler selection"), as
well as a MIPS compressed ISA disassembly target regression from commit
6394c60699 ("Don't use print_insn_XXX in GDB"), which caused assertion
failures to trigger.
For example with the `mips-linux-gnu' target we get:
$ cat main.c
int
main (void)
{
return 0;
}
$ gcc -mips32r2 -O2 main.c -o main
$ gcc -mips16 -mips32r2 -O2 main.c -o main16
$ gdb
GNU gdb (GDB) 8.0.50.20170731-git
[...]
(gdb) file main
Reading symbols from main...done.
(gdb) show architecture
The target architecture is set automatically (currently mips:isa32r2)
(gdb) show endian
The target endianness is set automatically (currently big endian)
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: jr ra
0x00400504 <+4>: move v0,zero
End of assembler dump.
(gdb) set architecture mips:isa64r2
The target architecture is assumed to be mips:isa64r2
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) set endian little
The target is assumed to be little endian
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:978: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->endian == (bfd_big_endian (exec_bfd) ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set endian auto
The target endianness is set automatically (currently big endian)
(gdb) set architecture i386
The target architecture is assumed to be i386
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:976: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->arch == bfd_get_arch (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) file main16
Load new symbol table from "main16"? (y or n) y
Reading symbols from main16...done.
(gdb) disassemble main
Dump of assembler code for function main:
0x00400501 <+0>:
.../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
Command aborted.
(gdb)
Remove the assertions then, restoring previous semantics:
(gdb) file main
Reading symbols from main...done.
(gdb) set architecture mips:isa64r2
The target architecture is assumed to be mips:isa64r2
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: jr ra
0x00400504 <+4>: move v0,zero
End of assembler dump.
(gdb) set endian little
The target is assumed to be little endian
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: j 0x3800c
0x00400504 <+4>: addiu s0,t0,0
End of assembler dump.
(gdb) set architecture i386
The target architecture is assumed to be i386
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: add %eax,%esp
0x00400502 <+2>: add %cl,(%eax)
0x00400504 <+4>: add %al,(%eax)
0x00400506 <+6>: adc %ah,0x0
End of assembler dump.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) set endian auto
The target endianness is set automatically (currently big endian)
(gdb) file main16
Load new symbol table from "main16"? (y or n) y
Reading symbols from main16...done.
(gdb) disassemble main
Dump of assembler code for function main:
0x00400501 <+0>: jr ra
0x00400503 <+2>: li v0,0
End of assembler dump.
(gdb)
gdb/
* arch-utils.c (default_print_insn): Remove arch/mach/endian
assertions.
opcodes/
* disassemble.c (disassembler): Remove arch/mach/endian
assertions.
The bit pattern comment in "aarch64_opcode_lookup_1" is reversed.
This patch fixed this.
opcode/
* aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
correct the print.
* aarch64-dis-2.c: Regenerated.
With IBM z14 officially announced I can add z14 as CPU name.
No regressions with that patch on s390x.
gas/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.
The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
When elf section size is beyond unsigned int max value, objdump fails
to disassemble from that section. Ex on PowerPC,
$ objdump -h /proc/kcore
Idx Name Size VMA
4 load2 100000000 c000000000000000
Here, size of load2 section is 0x100000000. Also note that, 0xc00....
address range is kernel space for PowerPC. Now let's try to disassemble
do_sys_open() using /proc/kcore.
$ cat /proc/kallsyms | grep -A1 -w do_sys_open
c00000000036c000 T do_sys_open
c00000000036c2d0 T SyS_open
Before patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: Address 0xc00000000036c000 is out of bounds.
Fix this by changing type of 'buffer_length' from unsigned int to
size_t. After patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: fc 00 4c 3c addis r2,r12,252
c00000000036c004: 00 53 42 38 addi r2,r2,21248
c00000000036c008: a6 02 08 7c mflr r0
include/
* dis-asm.h (struct disassemble_info): Change type of buffer_length
field to size_t.
opcodes/
* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
max_addr_offset and octets variables to size_t.
88c1242dc0 changed some generated files rather than the source.
* cgen-dis.in: Include disassemble.h, not dis-asm.h.
* m32c-dis.c: Regenerate.
* mep-dis.c: Regenerate.
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Tristan - are you ok with the backports ?
Applied to trunk.
regards Ramana
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.
Correct an issue introduced with commit 7361da2c95 ("Add support for
MIPS R6.") and move the LSA and DLSA instructions back to the MSA ASE
instruction block in the regular MIPS opcode table. Adjust formatting
around the "MIPS r6" heading.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
entries to the MSA ASE instruction block.
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support")
disassembler bug with the handling of the ASE_MIPS16E2_MT combination
ASE flag, where the calculation uses MIPS ABI Flags directly rather than
calculated internal ASE flags. Consequently code does not correctly set
the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag
come from different sources, i.e. one from the BFD chosen and the other
one from MIPS ABI Flags.
Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate
subsequent step, factored out to a dedicated function for use with
future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d'
test case accordingly, where the MT flag comes from the BFD selected for
the disassembler and the MIPS16e2 flag comes from the ELF binary itself.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): New function.
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
calculation to the new function.
(set_default_mips_dis_options): Call the new function.
gas/
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
This patch updates arc-dis.c:parse_disassembler_options to use a macro
FOR_EACH_DISASSEMBLER_OPTION, which has been introduced in [1], instead of a
homegrown solution to split option string.
[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=65b48a81
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_disassembler_options): Use
FOR_EACH_DISASSEMBLER_OPTION.
There is a bug in handling of cpu=... disassembler option in case there are
other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is
treated as an option value, and strcasecmp reports is as non-equal to "EM".
This is fixed by using disassembler_options_cmp function, which compares string
treating `,' the same way as `\0'.
This function also solves a problem with option order in parse_option.
Previously, if several option had same prefix (e.g. fpud, fpuda), then the
longer one should have been compared first, otherwise when longer option is
passed it would be treated as a short one, because
CONST_STRNEQ ("fpud", "fpuda")
would be true. The order of options was correct for ARC, so there were no
bugs per se, but with disassembler_option_cmp there is no risk of such a bug
being introduced in the future.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
disassembler option strings.
(parse_cpu_option): Likewise.
binutils/ChangeLog
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* testsuite/binutils-all/arc/double_store.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Tests for disassembler
options.
(do_objfile): New function.
(check_assembly): Likewise.
Jan Beulich
Alan Modra
H.J. Lu
Thomas Preud'homme
Jim Wilson
Maciej W. Rozycki
Nick Clifton
Henry Wong
Igor Tsimbalist
James Greenhalgh
Tamar Christina
Dimitar Dimitrov
Renlin Li
Peter Bergner
Stefan Stroe
claziss
Jiong Wang
Andrew Burgess
Andrew Waterman
Eric Botcazou
James Bowman
Andreas Krebbel
Alexander Fedotov
Sergio Durigan Junior
Kuan-Lin Chen
Palmer Dabbelt
Maciej W. Rozycki
John Eric Martin
Yuri Chornovian
Ravi Bangoria
Borislav Petkov
Ramana Radhakrishnan
Tristan Gingold
Tristan Gingold
Anton Kolesov