251 lines
8.1 KiB
Plaintext
251 lines
8.1 KiB
Plaintext
2013-03-12 Michael Eager <eager@eagercon.com>
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* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
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2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
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2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
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(thumb32_opcodes): Likewise.
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(print_insn_thumb32): Handle 'S' control char.
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2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
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* lm32-desc.c: Regenerate.
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2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* i386-reg.tbl (riz): Add RegRex64.
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* i386-tbl.h: Regenerated.
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2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
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(aarch64_feature_crc): New static.
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(CRC): New macro.
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(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
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crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
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* aarch64-asm-2.c: Re-generate.
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* aarch64-dis-2.c: Ditto.
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* aarch64-opc-2.c: Ditto.
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2013-02-27 Alan Modra <amodra@gmail.com>
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* rl78-decode.opc (rl78_decode_opcode): Fix typo.
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* rl78-decode.c: Regenerate.
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2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
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* rl78-decode.opc: Fix encoding of DIVWU insn.
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* rl78-decode.c: Regenerate.
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2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/15159
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* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
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* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
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(cpu_flags): Add CpuSMAP.
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* i386-opc.h (CpuSMAP): New.
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(i386_cpu_flags): Add cpusmap.
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* i386-opc.tbl: Add clac and stac.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
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* metag-dis.c: Initialize outf->bytes_per_chunk to 4
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which also makes the disassembler output be in little
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endian like it should be.
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2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
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fields to NULL.
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(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
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2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (is_compressed_mode_p): Only match symbols from the
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section disassembled.
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2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* arm-dis.c: Update strht pattern.
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2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
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* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
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single-float. Disable ll, lld, sc and scd for EE. Disable the
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trunc.w.s macro for EE.
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2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
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Andrew Jenner <andrew@codesourcery.com>
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Based on patches from Altera Corporation.
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
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nios2-opc.c.
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* Makefile.in: Regenerated.
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* configure.in: Add case for bfd_nios2_arch.
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* configure: Regenerated.
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* disassemble.c (ARCH_nios2): Define.
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(disassembler): Add case for bfd_arch_nios2.
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* nios2-dis.c: New file.
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* nios2-opc.c: New file.
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2013-02-04 Alan Modra <amodra@gmail.com>
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* po/POTFILES.in: Regenerate.
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* rl78-decode.c: Regenerate.
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* rx-decode.c: Regenerate.
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2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
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ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
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* aarch64-asm.c (convert_xtl_to_shll): New function.
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(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
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calling convert_xtl_to_shll.
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* aarch64-dis.c (convert_shll_to_xtl): New function.
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(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
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calling convert_shll_to_xtl.
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* aarch64-gen.c: Update copyright year.
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* aarch64-asm-2.c: Re-generate.
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* aarch64-dis-2.c: Re-generate.
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* aarch64-opc-2.c: Re-generate.
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2013-01-24 Nick Clifton <nickc@redhat.com>
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* v850-dis.c: Add support for e3v5 architecture.
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* v850-opc.c: Likewise.
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2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
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* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): For
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AARCH64_MOD_LSL, move the range check on the shift amount before the
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alignment check; change to call set_sft_amount_out_of_range_error
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instead of set_imm_out_of_range_error.
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* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
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(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
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8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
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SIMD_IMM_SFT.
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2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2013-01-15 Nick Clifton <nickc@redhat.com>
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* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
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values.
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* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
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2013-01-14 Will Newton <will.newton@imgtec.com>
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* metag-dis.c (REG_WIDTH): Increase to 64.
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2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
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* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
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XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
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(SH6): Update.
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<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
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"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
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"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
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<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
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2013-01-10 Will Newton <will.newton@imgtec.com>
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* Makefile.am: Add Meta.
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* configure.in: Add Meta.
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* disassemble.c: Add Meta support.
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* metag-dis.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
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(match_opcode): Rename to cr16_match_opcode.
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2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
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* mips-dis.c: Add names for CP0 registers of r5900.
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* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
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instructions sq and lq.
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Add support for MIPS r5900 CPU.
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Add support for 128 bit MMI (Multimedia Instructions).
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Add support for EE instructions (Emotion Engine).
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Disable unsupported floating point instructions (64 bit and
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undefined compare operations).
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Enable instructions of MIPS ISA IV which are supported by r5900.
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Disable 64 bit co processor instructions.
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Disable 64 bit multiplication and division instructions.
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Disable instructions for co-processor 2 and 3, because these are
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not supported (preparation for later VU0 support (Vector Unit)).
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Disable cvt.w.s because this behaves like trunc.w.s and the
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correct execution can't be ensured on r5900.
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Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
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will confuse less developers and compilers.
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (aarch64_print_operand): Change to print
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AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
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in comment.
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* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
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from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
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OP_MOV_IMM_WIDE.
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
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PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
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2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (process_copyright): Update copyright year to 2013.
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2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* cr16-dis.c (match_opcode,make_instruction): Remove static
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declaration.
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(dwordU,wordU): Moved typedefs to opcode/cr16.h
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(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
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For older changes see ChangeLog-2012
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Copyright (C) 2013 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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