517 lines
16 KiB
Plaintext
517 lines
16 KiB
Plaintext
2004-09-30 Paul Brook <paul@codesourcery.com>
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* arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
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* arm-opc.h: Document %e. Add ARMv6ZK instructions.
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2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
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(CONFIG_STATUS_DEPENDENCIES): New.
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(Makefile): Removed.
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(config.status): Likewise.
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* Makefile.in: Regenerated.
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2004-09-17 Alan Modra <amodra@bigpond.net.au>
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* Makefile.am: Run "make dep-am".
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* Makefile.in: Regenerate.
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* aclocal.m4: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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2004-09-11 Andreas Schwab <schwab@suse.de>
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* configure: Rebuild.
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2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
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* ppc-opc.c (L): Make this field not optional.
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2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
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* opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
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Fix parameter to 'm[t|f]csr' insns.
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2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
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* configure.in: Autoupdate to autoconf 2.59.
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* aclocal.m4: Rebuild with aclocal 1.4p6.
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* configure: Rebuild with autoconf 2.59.
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* Makefile.in: Rebuild with automake 1.4p6 (picking up
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bfd changes for autoconf 2.59 on the way).
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* config.in: Rebuild with autoheader 2.59.
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2004-08-27 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.[ch], frv-opc.[ch]: Regenerated.
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2004-07-30 Michal Ludvig <mludvig@suse.cz>
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* i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
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(GRPPADLCK2): New define.
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(twobyte_has_modrm): True for 0xA6.
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(grps): GRPPADLCK2 for opcode 0xA6.
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2004-07-29 Alexandre Oliva <aoliva@redhat.com>
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Introduce SH2a support.
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* sh-opc.h (arch_sh2a_base): Renumber.
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(arch_sh2a_nofpu_base): Remove.
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(arch_sh_base_mask): Adjust.
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(arch_opann_mask): New.
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(arch_sh2a, arch_sh2a_nofpu): Adjust.
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(arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
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(sh_table): Adjust whitespace.
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2004-02-24 Corinna Vinschen <vinschen@redhat.com>
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* sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
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instruction list throughout.
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(arch_sh2a_up): Redefine to include fpu instruction set. Use instead
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of arch_sh2a in instruction list throughout.
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(arch_sh2e_up): Accomodate above changes.
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(arch_sh2_up): Ditto.
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2004-02-20 Corinna Vinschen <vinschen@redhat.com>
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* sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
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2004-02-18 Corinna Vinschen <vinschen@redhat.com>
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* sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
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* sh-opc.h (arch_sh2a_nofpu): New.
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(arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
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(sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
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instruction.
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2004-01-20 DJ Delorie <dj@redhat.com>
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* sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
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2003-12-29 DJ Delorie <dj@redhat.com>
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* sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
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sh_opcode_info, sh_table): Add sh2a support.
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(arch_op32): New, to tag 32-bit opcodes.
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* sh-dis.c (print_insn_sh): Support sh2a opcodes.
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2003-12-02 Michael Snyder <msnyder@redhat.com>
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* sh-opc.h (arch_sh2a): Add.
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* sh-dis.c (arch_sh2a): Handle.
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* sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
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2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
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* crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
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2004-07-22 Nick Clifton <nickc@redhat.com>
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PR/280
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* h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
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insns - this is done by objdump itself.
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* h8500-dis.c (print_insn_h8500): Likewise.
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2004-07-21 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
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regardless of address size prefix in effect.
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(ptr_reg): Size or address registers does not depend on rex64, but
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on the presence of an address size override.
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(OP_MMX): Use rex.x only for xmm registers.
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(OP_EM): Use rex.z only for xmm registers.
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
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move/branch operations to the bottom so that VR5400 multimedia
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instructions take precedence in disassembly.
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
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ISA-specific "break" encoding.
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2004-07-13 Elvis Chiang <elvisfb@gmail.com>
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* arm-opc.h: Fix typo in comment.
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2004-07-11 Andreas Schwab <schwab@suse.de>
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* m68k-dis.c (m68k_valid_ea): Fix typos in last change.
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2004-07-09 Andreas Schwab <schwab@suse.de>
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* m68k-dis.c (m68k_valid_ea): Check validity of all codes.
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2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
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* Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
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(ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
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(crx-dis.lo): New target.
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(crx-opc.lo): Likewise.
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* Makefile.in: Regenerate.
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* configure.in: Handle bfd_crx_arch.
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* configure: Regenerate.
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* crx-dis.c: New file.
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* crx-opc.c: New file.
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* disassemble.c (ARCH_crx): Define.
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(disassembler): Handle ARCH_crx.
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2004-06-29 James E Wilson <wilson@specifixinc.com>
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* ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
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* ia64-asmtab.c: Regnerate.
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2004-06-28 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
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(extract_fxm): Don't test dialect.
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(XFXFXM_MASK): Include the power4 bit.
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(XFXM): Add p4 param.
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(powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
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2004-06-27 Alexandre Oliva <aoliva@redhat.com>
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2003-07-21 Richard Sandiford <rsandifo@redhat.com>
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* disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
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2004-06-26 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (BH, XLBH_MASK): Define.
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(powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
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2004-06-24 Alan Modra <amodra@bigpond.net.au>
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* i386-dis.c (x_mode): Comment.
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(two_source_ops): File scope.
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(float_mem): Correct fisttpll and fistpll.
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(float_mem_mode): New table.
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(dofloat): Use it.
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(OP_E): Correct intel mode PTR output.
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(ptr_reg): Use open_char and close_char.
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(PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
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operands. Set two_source_ops.
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2004-06-15 Alan Modra <amodra@bigpond.net.au>
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* arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
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instead of _raw_size.
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2004-06-08 Jakub Jelinek <jakub@redhat.com>
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* ia64-gen.c (in_iclass): Handle more postinc st
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and ld variants.
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* ia64-asmtab.c: Rebuilt.
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2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
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* s390-opc.txt: Correct architecture mask for some opcodes.
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lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
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in the esa mode as well.
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2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-dis.c (target_arch): Make unsigned.
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(print_insn_sh): Replace (most of) switch with a call to
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sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
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* sh-opc.h: Redefine architecture flags values.
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Add sh3-nommu architecture.
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Reorganise <arch>_up macros so they make more visual sense.
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(SH_MERGE_ARCH_SET): Define new macro.
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(SH_VALID_BASE_ARCH_SET): Likewise.
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(SH_VALID_MMU_ARCH_SET): Likewise.
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(SH_VALID_CO_ARCH_SET): Likewise.
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(SH_VALID_ARCH_SET): Likewise.
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(SH_MERGE_ARCH_SET_VALID): Likewise.
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(SH_ARCH_SET_HAS_FPU): Likewise.
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(SH_ARCH_SET_HAS_DSP): Likewise.
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(SH_ARCH_UNKNOWN_ARCH): Likewise.
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(sh_get_arch_from_bfd_mach): Add prototype.
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(sh_get_arch_up_from_bfd_mach): Likewise.
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(sh_get_bfd_mach_from_arch_set): Likewise.
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(sh_merge_bfd_arc): Likewise.
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2004-05-24 Peter Barada <peter@the-baradas.com>
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* m68k-dis.c(print_insn_m68k): Strip body of diassembly out
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into new match_insn_m68k function. Loop over canidate
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matches and select first that completely matches.
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* m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
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* m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
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to verify addressing for MAC/EMAC.
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* m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
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reigster halves since 'fpu' and 'spl' look misleading.
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* m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
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* m68k-opc.c: Rearragne mac/emac cases to use longest for
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first, tighten up match masks.
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* m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
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'size' from special case code in print_insn_m68k to
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determine decode size of insns.
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2004-05-19 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
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well as when -mpower4.
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2004-05-13 Nick Clifton <nickc@redhat.com>
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* po/fr.po: Updated French translation.
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2004-05-05 Peter Barada <peter@the-baradas.com>
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* m68k-dis.c(print_insn_m68k): Add new chips, use core
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variants in arch_mask. Only set m68881/68851 for 68k chips.
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* m68k-op.c: Switch from ColdFire chips to core variants.
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2004-05-05 Alan Modra <amodra@bigpond.net.au>
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PR 147.
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* ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
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2004-04-29 Ben Elliston <bje@au.ibm.com>
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* ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
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(powerpc_opcodes): Add "dbczl" instruction for PPC970.
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2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
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* sh-dis.c (print_insn_sh): Print the value in constant pool
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as a symbol if it looks like a symbol.
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2004-04-22 Peter Barada <peter@the-baradas.com>
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* m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
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appropriate ColdFire architectures.
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(print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
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mask addressing.
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Add EMAC instructions, fix MAC instructions. Remove
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macmw/macml/msacmw/msacml instructions since mask addressing now
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supported.
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2004-04-20 Jakub Jelinek <jakub@redhat.com>
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* sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
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(fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
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suffix. Use fmov*x macros, create all 3 fpsize variants in one
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macro. Adjust all users.
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2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
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* h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
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separately.
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2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
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* m32r-asm.c: Regenerate.
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2004-03-29 Stan Shebs <shebs@apple.com>
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* mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
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used.
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2004-03-19 Alan Modra <amodra@bigpond.net.au>
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* aclocal.m4: Regenerate.
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* config.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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2004-03-16 Alan Modra <amodra@bigpond.net.au>
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* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
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PPC_OPERANDS_GPR_0.
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* ppc-opc.c (RA0): Define.
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(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
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(RAOPT): Rename from RAO. Update all uses.
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(powerpc_opcodes): Use RA0 as appropriate.
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2004-03-15 Aldy Hernandez <aldyh@redhat.com>
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* ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
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2004-03-15 Alan Modra <amodra@bigpond.net.au>
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* sparc-dis.c (print_insn_sparc): Update getword prototype.
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386-dis.c (GRPPLOCK): Delete.
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(grps): Delete GRPPLOCK entry.
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2004-03-12 Alan Modra <amodra@bigpond.net.au>
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* i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
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(M, Mp): Use OP_M.
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(None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
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(GRPPADLCK): Define.
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(dis386): Use NOP_Fixup on "nop".
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(dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
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(twobyte_has_modrm): Set for 0xa7.
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(padlock_table): Delete. Move to..
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(grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
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and clflush.
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(print_insn): Revert PADLOCK_SPECIAL code.
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(OP_E): Delete sfence, lfence, mfence checks.
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2004-03-12 Jakub Jelinek <jakub@redhat.com>
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* i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
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(INVLPG_Fixup): New function.
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(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
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(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
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(padlock_table): New struct with PadLock instructions.
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(print_insn): Handle PADLOCK_SPECIAL.
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2004-03-12 Alan Modra <amodra@bigpond.net.au>
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* i386-dis.c (grps): Use clflush by default for 0x0fae/7.
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(OP_E): Twiddle clflush to sfence here.
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2004-03-08 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
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nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
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* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
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accordingly.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-asm.c: Regenerate.
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* frv-desc.c: Regenerate.
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* frv-desc.h: Regenerate.
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* frv-dis.c: Regenerate.
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* frv-ibld.c: Regenerate.
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* frv-opc.c: Regenerate.
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* frv-opc.h: Regenerate.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.c, frv-opc.c: Regenerate.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
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2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
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Also correct mistake in the comment.
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2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
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ensure that double registers have even numbers.
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Add REG_N_B01 for nn01 (binary 01) nibble to ensure
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that reserved instruction 0xfffd does not decode the same
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as 0xfdfd (ftrv).
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* sh-opc.h: Add REG_N_D nibble type and use it whereever
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REG_N refers to a double register.
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Add REG_N_B01 nibble type and use it instead of REG_NM
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in ftrv.
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Adjust the bit patterns in a few comments.
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2004-02-25 Aldy Hernandez <aldyh@redhat.com>
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* ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
|
||
|
||
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
|
||
|
||
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Add m*ivor35.
|
||
|
||
2004-02-20 Aldy Hernandez <aldyh@redhat.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
|
||
mtivor32, mtivor33, mtivor34.
|
||
|
||
2004-02-19 Aldy Hernandez <aldyh@redhat.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Add mfmcar.
|
||
|
||
2004-02-10 Petko Manolov <petkan@nucleusys.com>
|
||
|
||
* arm-opc.h Maverick accumulator register opcode fixes.
|
||
|
||
2004-02-13 Ben Elliston <bje@wasabisystems.com>
|
||
|
||
* m32r-dis.c: Regenerate.
|
||
|
||
2004-01-27 Michael Snyder <msnyder@redhat.com>
|
||
|
||
* sh-opc.h (sh_table): "fsrra", not "fssra".
|
||
|
||
2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
|
||
|
||
* sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
|
||
contraints.
|
||
|
||
2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
|
||
|
||
* sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
|
||
|
||
2004-01-19 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
* i386-dis.c (OP_E): Print scale factor on intel mode sib when not
|
||
1. Don't print scale factor on AT&T mode when index missing.
|
||
|
||
2004-01-16 Alexandre Oliva <aoliva@redhat.com>
|
||
|
||
* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
|
||
when loaded into XR registers.
|
||
|
||
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
|
||
|
||
* frv-desc.h: Regenerate.
|
||
* frv-desc.c: Regenerate.
|
||
* frv-opc.c: Regenerate.
|
||
|
||
2004-01-13 Michael Snyder <msnyder@redhat.com>
|
||
|
||
* sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
|
||
|
||
2004-01-09 Paul Brook <paul@codesourcery.com>
|
||
|
||
* arm-opc.h (arm_opcodes): Move generic mcrr after known
|
||
specific opcodes.
|
||
|
||
2004-01-07 Daniel Jacobowitz <drow@mvista.com>
|
||
|
||
* Makefile.am (libopcodes_la_DEPENDENCIES)
|
||
(libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
|
||
comment about the problem.
|
||
* Makefile.in: Regenerate.
|
||
|
||
2004-01-06 Alexandre Oliva <aoliva@redhat.com>
|
||
|
||
2003-12-19 Alexandre Oliva <aoliva@redhat.com>
|
||
* frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
|
||
cut&paste errors in shifting/truncating numerical operands.
|
||
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
||
* frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
|
||
(parse_uslo16): Likewise.
|
||
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
|
||
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
|
||
(parse_s12): Likewise.
|
||
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
||
* frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
|
||
(parse_uslo16): Likewise.
|
||
(parse_uhi16): Parse gothi and gotfuncdeschi.
|
||
(parse_d12): Parse got12 and gotfuncdesc12.
|
||
(parse_s12): Likewise.
|
||
|
||
2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
|
||
|
||
* msp430-dis.c (msp430_doubleoperand): Check for an 'add'
|
||
instruction which looks similar to an 'rla' instruction.
|
||
|
||
For older changes see ChangeLog-0203
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|