184 lines
6.6 KiB
C
184 lines
6.6 KiB
C
/* General Cpu tools GENerated simulator support.
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef CGEN_DEFS_H
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#define CGEN_DEFS_H
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/* Compute number of longs required to hold N bits. */
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#define HOST_LONGS_FOR_BITS(n) \
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(((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
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/* Forward decls. Defined in the machine generated files. */
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/* This holds the contents of the extracted insn.
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There are a few common entries (e.g. pc address), and then one big
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union with an entry for each of the instruction formats. */
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typedef struct argbuf ARGBUF;
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/* ARGBUF accessors. */
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#define ARGBUF_ADDR(abuf) ((abuf)->addr)
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#define ARGBUF_IDESC(abuf) ((abuf)->idesc)
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#define ARGBUF_TRACE_P(abuf) ((abuf)->trace_p)
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#define ARGBUF_PROFILE_P(abuf) ((abuf)->profile_p)
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/* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support.
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At present there is nothing else, but it also provides a level of
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abstraction. */
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typedef struct scache SCACHE;
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/* This is a union with one entry for each instruction format.
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Each entry contains all of the non-constant inputs of the instruction
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in the case of read-before-exec support, or all outputs of the instruction
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in the case of write-after-exec support. */
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typedef struct parexec PAREXEC;
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/* An "Instruction DESCriptor".
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This is the main handle on an instruction for the simulator. */
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typedef struct idesc IDESC;
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/* Engine support.
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??? This is here because it's needed before eng.h (built by genmloop.sh)
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which is needed before cgen-engine.h and cpu.h.
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??? This depends on a cpu family specific type, IADDR, but no machine
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generated headers will have been included yet. sim/common currently
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requires the typedef of sim_cia in sim-main.h between the inclusion of
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sim-basics.h and sim-base.h so this is no different. */
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/* SEM_ARG is intended to hide whether or not the scache is in use from the
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semantic routines. In reality for the with-extraction case it is always
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an SCACHE * even when not using the SCACHE since there's no current win to
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making it something else ("not using the SCACHE" is like having a cache
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size of 1).
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The without-extraction case still uses an ARGBUF:
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- consistency with scache version
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- still need to record which operands are written
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This wouldn't be needed if modeling was done in the semantic routines
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but this isn't as general as handling it outside of the semantic routines.
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For example Shade allows calling user-supplied code before/after each
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instruction and this is something that is being planned.
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??? There is still some clumsiness in how much of ARGBUF to use. */
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typedef SCACHE *SEM_ARG;
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/* instruction address
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??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB
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case. The first element is the IADDR, the second element is the SCACHE *.
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Haven't found the time yet to make this work, but it seemed a nicer approach
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than the current br_cache stuff. */
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typedef IADDR PCADDR;
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/* Current instruction address, used by common. */
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typedef IADDR CIA;
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/* Semantic routines' version of the PC. */
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#if WITH_SCACHE_PBB
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typedef SCACHE *SEM_PC;
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#else
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typedef IADDR SEM_PC;
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#endif
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/* Kinds of branches. */
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typedef enum {
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SEM_BRANCH_UNTAKEN,
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/* Branch to an uncacheable address (e.g. j reg). */
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SEM_BRANCH_UNCACHEABLE,
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/* Branch to a cacheable (fixed) address. */
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SEM_BRANCH_CACHEABLE
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} SEM_BRANCH_TYPE;
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/* Virtual insn support. */
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/* Opcode table for virtual insns (only used by the simulator). */
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extern const CGEN_INSN cgen_virtual_insn_table[];
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/* -ve of indices of virtual insns in cgen_virtual_insn_table. */
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typedef enum {
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VIRTUAL_INSN_X_INVALID = 0,
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VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2,
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VIRTUAL_INSN_X_BEGIN = -3,
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VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
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} CGEN_INSN_VIRTUAL_TYPE;
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/* Return non-zero if CGEN_INSN* INSN is a virtual insn. */
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#define CGEN_INSN_VIRTUAL_P(insn) \
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CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL)
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/* GNU C's "computed goto" facility is used to speed things up where
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possible. These macros provide a portable way to use them.
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Nesting of these switch statements is done by providing an extra argument
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that distinguishes them. `N' can be a number or symbol.
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Variable `labels_##N' must be initialized with the labels of each case. */
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#ifdef __GNUC__
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#define SWITCH(N, X) goto *X;
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#define CASE(N, X) case_##N##_##X
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#define BREAK(N) goto end_switch_##N
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#define DEFAULT(N) default_##N
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#define ENDSWITCH(N) end_switch_##N:
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#else
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#define SWITCH(N, X) switch (X)
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#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
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#define BREAK(N) break
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#define DEFAULT(N) default
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#define ENDSWITCH(N)
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#endif
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/* Simulator state. */
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/* Records simulator descriptor so utilities like @cpu@_dump_regs can be
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called from gdb. */
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extern SIM_DESC current_state;
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/* Simulator state. */
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/* CGEN_STATE contains additional state information not present in
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sim_state_base. */
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typedef struct cgen_state {
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/* FIXME: Moved to sim_state_base. */
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/* argv, env */
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char **argv;
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#define STATE_ARGV(s) ((s) -> cgen_state.argv)
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/* FIXME: Move to sim_state_base. */
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char **envp;
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#define STATE_ENVP(s) ((s) -> cgen_state.envp)
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/* Non-zero if no tracing or profiling is selected. */
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int run_fast_p;
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#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
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} CGEN_STATE;
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/* Various utilities. */
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/* Called after sim_post_argv_init to do any cgen initialization. */
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extern void cgen_init (SIM_DESC);
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/* Return the name of an insn. */
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extern CPU_INSN_NAME_FN cgen_insn_name;
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/* Return the maximum number of extra bytes required for a sim_cpu struct. */
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/* ??? Ok, yes, this is less pretty than it should be. Give me a better
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language [or suggest a better way]. */
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extern int cgen_cpu_max_extra_bytes (void);
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/* Target supplied routine to process an invalid instruction. */
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extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC);
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#endif /* CGEN_DEFS_H */
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