231097b03a
This patch changes the eBPF CPU description to prefer the register names %r0 and %r6 instead of %a and %ctx when disassembling. This matches better with the current practice, vs. cBPF. It also updates the GAS tests in order to reflect this change. Tested in a x86_64 host. cpu/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of %a and %ctx. opcodes/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerated. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. |
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| .. | ||
| ChangeLog | ||
| bpf.cpu | ||
| bpf.opc | ||
| cris.cpu | ||
| epiphany.cpu | ||
| epiphany.opc | ||
| fr30.cpu | ||
| fr30.opc | ||
| frv.cpu | ||
| frv.opc | ||
| ip2k.cpu | ||
| ip2k.opc | ||
| iq10.cpu | ||
| iq2000.cpu | ||
| iq2000.opc | ||
| iq2000m.cpu | ||
| lm32.cpu | ||
| lm32.opc | ||
| m32c.cpu | ||
| m32c.opc | ||
| m32r.cpu | ||
| m32r.opc | ||
| mep-avc.cpu | ||
| mep-avc2.cpu | ||
| mep-c5.cpu | ||
| mep-core.cpu | ||
| mep-default.cpu | ||
| mep-ext-cop.cpu | ||
| mep-fmax.cpu | ||
| mep-h1.cpu | ||
| mep-ivc2.cpu | ||
| mep-rhcop.cpu | ||
| mep-sample-ucidsp.cpu | ||
| mep.cpu | ||
| mep.opc | ||
| mt.cpu | ||
| mt.opc | ||
| or1k.cpu | ||
| or1k.opc | ||
| or1kcommon.cpu | ||
| or1korbis.cpu | ||
| or1korfpx.cpu | ||
| sh.cpu | ||
| sh.opc | ||
| sh64-compact.cpu | ||
| sh64-media.cpu | ||
| simplify.inc | ||
| xc16x.cpu | ||
| xc16x.opc | ||
| xstormy16.cpu | ||
| xstormy16.opc | ||