05805feba2
This fixes the testcases that are failing due to my recent patch. It turns out that the start address across baremetal and linux builds isn't entirely predictable without a linker script. Since the address themselves are not the important thing I am ignoring them now. Secondly I was encoding data using .word using non 0 values, however because .word is subjected to endiannes these non-zero values under big-endian happen to fall into the encoding space of instructions which changes the disassembly. Using 0 fixes this problem and the purpose of the test still holds, though objdump will dump ... for data only sections, which is ok as the data/insn mixed sections will test the patch. The ARM Attributes sections is not important and is ignored. binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order.d: Likewise. * testsuite/binutils-all/aarch64/out-of-order.s: Likewise. * testsuite/binutils-all/arm/in-order-all.d: Likewise. * testsuite/binutils-all/arm/in-order.d: Likewise. * testsuite/binutils-all/arm/out-of-order-all.d: Likewise. * testsuite/binutils-all/arm/out-of-order.d: Likewise. * testsuite/binutils-all/arm/out-of-order.s: Likewise.
49 lines
866 B
Makefile
49 lines
866 B
Makefile
#PROG: objcopy
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#source: out-of-order.s
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#ld: -e v1 -Ttext-segment=0x400000
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#objdump: -D
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#name: Check if disassembler can handle all sections in default order
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.*: +file format .*arm.*
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Disassembly of section \.func1:
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.+ <v1>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.func2:
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.+ <\.func2>:
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[^:]+: e0800001 add r0, r0, r1
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Disassembly of section \.func3:
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.+ <\.func3>:
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: e0800001 add r0, r0, r1
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.rodata:
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.+ <\.rodata>:
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[^:]+: 00000000 andeq r0, r0, r0
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Disassembly of section \.global:
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.+ <.+>:
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...
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Disassembly of section \.ARM\.attributes:
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.+ <\.ARM\.attributes>:
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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[^:]+: .+
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