1340 lines
40 KiB
C
1340 lines
40 KiB
C
/* GNU/Linux/AArch64 specific low level interface, for the remote server for
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GDB.
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Copyright (C) 2009-2015 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include "elf/common.h"
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#include <signal.h>
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#include <sys/user.h>
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#include <sys/ptrace.h>
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#include <asm/ptrace.h>
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#include <sys/uio.h>
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#include "gdb_proc_service.h"
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/* Defined in auto-generated files. */
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void init_registers_aarch64 (void);
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extern const struct target_desc *tdesc_aarch64;
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#ifdef HAVE_SYS_REG_H
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#include <sys/reg.h>
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#endif
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#define AARCH64_X_REGS_NUM 31
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#define AARCH64_V_REGS_NUM 32
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#define AARCH64_X0_REGNO 0
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#define AARCH64_SP_REGNO 31
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#define AARCH64_PC_REGNO 32
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#define AARCH64_CPSR_REGNO 33
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#define AARCH64_V0_REGNO 34
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#define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
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#define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
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#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
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static int
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aarch64_regmap [] =
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{
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/* These offsets correspond to GET/SETREGSET */
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/* x0... */
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0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
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8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
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16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
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24*8, 25*8, 26*8, 27*8, 28*8,
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29*8,
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30*8, /* x30 lr */
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31*8, /* x31 sp */
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32*8, /* pc */
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33*8, /* cpsr 4 bytes!*/
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/* FP register offsets correspond to GET/SETFPREGSET */
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0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
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8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
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16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
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24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
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};
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/* Here starts the macro definitions, data structures, and code for
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the hardware breakpoint and hardware watchpoint support. The
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following is the abbreviations that are used frequently in the code
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and comment:
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hw - hardware
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bp - breakpoint
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wp - watchpoint */
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/* Maximum number of hardware breakpoint and watchpoint registers.
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Neither of these values may exceed the width of dr_changed_t
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measured in bits. */
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#define AARCH64_HBP_MAX_NUM 16
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#define AARCH64_HWP_MAX_NUM 16
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/* Alignment requirement in bytes of hardware breakpoint and
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watchpoint address. This is the requirement for the addresses that
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can be written to the hardware breakpoint/watchpoint value
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registers. The kernel currently does not do any alignment on
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addresses when receiving a writing request (via ptrace call) to
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these debug registers, and it will reject any address that is
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unaligned.
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Some limited support has been provided in this gdbserver port for
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unaligned watchpoints, so that from a gdb user point of view, an
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unaligned watchpoint can still be set. This is achieved by
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minimally enlarging the watched area to meet the alignment
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requirement, and if necessary, splitting the watchpoint over
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several hardware watchpoint registers. */
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#define AARCH64_HBP_ALIGNMENT 4
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#define AARCH64_HWP_ALIGNMENT 8
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/* The maximum length of a memory region that can be watched by one
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hardware watchpoint register. */
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#define AARCH64_HWP_MAX_LEN_PER_REG 8
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/* Each bit of a variable of this type is used to indicate whether a
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hardware breakpoint or watchpoint setting has been changed since
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the last updating. Bit N corresponds to the Nth hardware
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breakpoint or watchpoint setting which is managed in
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aarch64_debug_reg_state. Where N is valid between 0 and the total
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number of the hardware breakpoint or watchpoint debug registers
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minus 1. When the bit N is 1, it indicates the corresponding
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breakpoint or watchpoint setting is changed, and thus the
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corresponding hardware debug register needs to be updated via the
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ptrace interface.
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In the per-thread arch-specific data area, we define two such
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variables for per-thread hardware breakpoint and watchpoint
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settings respectively.
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This type is part of the mechanism which helps reduce the number of
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ptrace calls to the kernel, i.e. avoid asking the kernel to write
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to the debug registers with unchanged values. */
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typedef unsigned long long dr_changed_t;
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/* Set each of the lower M bits of X to 1; assert X is wide enough. */
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#define DR_MARK_ALL_CHANGED(x, m) \
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do \
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{ \
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gdb_assert (sizeof ((x)) * 8 >= (m)); \
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(x) = (((dr_changed_t)1 << (m)) - 1); \
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} while (0)
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#define DR_MARK_N_CHANGED(x, n) \
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do \
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{ \
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(x) |= ((dr_changed_t)1 << (n)); \
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} while (0)
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#define DR_CLEAR_CHANGED(x) \
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do \
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{ \
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(x) = 0; \
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} while (0)
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#define DR_HAS_CHANGED(x) ((x) != 0)
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#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
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/* Structure for managing the hardware breakpoint/watchpoint resources.
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DR_ADDR_* stores the address, DR_CTRL_* stores the control register
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content, and DR_REF_COUNT_* counts the numbers of references to the
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corresponding bp/wp, by which way the limited hardware resources
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are not wasted on duplicated bp/wp settings (though so far gdb has
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done a good job by not sending duplicated bp/wp requests). */
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struct aarch64_debug_reg_state
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{
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/* hardware breakpoint */
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CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
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/* hardware watchpoint */
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CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
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};
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/* Per-process arch-specific data we want to keep. */
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struct arch_process_info
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{
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/* Hardware breakpoint/watchpoint data.
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The reason for them to be per-process rather than per-thread is
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due to the lack of information in the gdbserver environment;
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gdbserver is not told that whether a requested hardware
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breakpoint/watchpoint is thread specific or not, so it has to set
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each hw bp/wp for every thread in the current process. The
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higher level bp/wp management in gdb will resume a thread if a hw
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bp/wp trap is not expected for it. Since the hw bp/wp setting is
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same for each thread, it is reasonable for the data to live here.
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*/
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struct aarch64_debug_reg_state debug_reg_state;
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};
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/* Per-thread arch-specific data we want to keep. */
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struct arch_lwp_info
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{
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/* When bit N is 1, it indicates the Nth hardware breakpoint or
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watchpoint register pair needs to be updated when the thread is
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resumed; see aarch64_linux_prepare_to_resume. */
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dr_changed_t dr_changed_bp;
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dr_changed_t dr_changed_wp;
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};
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/* Number of hardware breakpoints/watchpoints the target supports.
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They are initialized with values obtained via the ptrace calls
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with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
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static int aarch64_num_bp_regs;
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static int aarch64_num_wp_regs;
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static int
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aarch64_cannot_store_register (int regno)
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{
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return regno >= AARCH64_NUM_REGS;
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}
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static int
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aarch64_cannot_fetch_register (int regno)
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{
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return regno >= AARCH64_NUM_REGS;
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}
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static void
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aarch64_fill_gregset (struct regcache *regcache, void *buf)
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{
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struct user_pt_regs *regset = buf;
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int i;
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for (i = 0; i < AARCH64_X_REGS_NUM; i++)
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collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
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collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
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collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
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collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
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}
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static void
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aarch64_store_gregset (struct regcache *regcache, const void *buf)
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{
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const struct user_pt_regs *regset = buf;
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int i;
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for (i = 0; i < AARCH64_X_REGS_NUM; i++)
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supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
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supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
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supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
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supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
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}
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static void
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aarch64_fill_fpregset (struct regcache *regcache, void *buf)
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{
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struct user_fpsimd_state *regset = buf;
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int i;
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for (i = 0; i < AARCH64_V_REGS_NUM; i++)
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collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
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collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
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collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
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}
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static void
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aarch64_store_fpregset (struct regcache *regcache, const void *buf)
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{
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const struct user_fpsimd_state *regset = buf;
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int i;
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for (i = 0; i < AARCH64_V_REGS_NUM; i++)
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supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
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supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
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supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
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}
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/* Enable miscellaneous debugging output. The name is historical - it
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was originally used to debug LinuxThreads support. */
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extern int debug_threads;
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static CORE_ADDR
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aarch64_get_pc (struct regcache *regcache)
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{
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unsigned long pc;
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collect_register_by_name (regcache, "pc", &pc);
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if (debug_threads)
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debug_printf ("stop pc is %08lx\n", pc);
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return pc;
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}
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static void
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aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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unsigned long newpc = pc;
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supply_register_by_name (regcache, "pc", &newpc);
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}
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/* Correct in either endianness. */
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#define aarch64_breakpoint_len 4
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static const unsigned long aarch64_breakpoint = 0x00800011;
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static int
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aarch64_breakpoint_at (CORE_ADDR where)
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{
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unsigned long insn;
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(*the_target->read_memory) (where, (unsigned char *) &insn, 4);
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if (insn == aarch64_breakpoint)
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return 1;
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return 0;
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}
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/* Print the values of the cached breakpoint/watchpoint registers.
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This is enabled via the "set debug-hw-points" monitor command. */
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static void
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aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type)
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{
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int i;
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fprintf (stderr, "%s", func);
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if (addr || len)
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fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
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(unsigned long) addr, len,
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type == hw_write ? "hw-write-watchpoint"
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: (type == hw_read ? "hw-read-watchpoint"
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: (type == hw_access ? "hw-access-watchpoint"
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: (type == hw_execute ? "hw-breakpoint"
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: "??unknown??"))));
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fprintf (stderr, ":\n");
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fprintf (stderr, "\tBREAKPOINTs:\n");
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for (i = 0; i < aarch64_num_bp_regs; i++)
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fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
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i, paddress (state->dr_addr_bp[i]),
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state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
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fprintf (stderr, "\tWATCHPOINTs:\n");
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for (i = 0; i < aarch64_num_wp_regs; i++)
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fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
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i, paddress (state->dr_addr_wp[i]),
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state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
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}
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static void
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aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
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{
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int i;
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for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
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{
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state->dr_addr_bp[i] = 0;
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state->dr_ctrl_bp[i] = 0;
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state->dr_ref_count_bp[i] = 0;
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}
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for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
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{
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state->dr_addr_wp[i] = 0;
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state->dr_ctrl_wp[i] = 0;
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state->dr_ref_count_wp[i] = 0;
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}
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}
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/* ptrace expects control registers to be formatted as follows:
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31 13 5 3 1 0
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+--------------------------------+----------+------+------+----+
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| RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
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+--------------------------------+----------+------+------+----+
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The TYPE field is ignored for breakpoints. */
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#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
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#define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
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/* Utility function that returns the length in bytes of a watchpoint
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according to the content of a hardware debug control register CTRL.
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Note that the kernel currently only supports the following Byte
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Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
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that for a hardware watchpoint, its valid length can only be 1
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byte, 2 bytes, 4 bytes or 8 bytes. */
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static inline unsigned int
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aarch64_watchpoint_length (unsigned int ctrl)
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{
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switch (DR_CONTROL_LENGTH (ctrl))
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{
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case 0x01:
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return 1;
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case 0x03:
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return 2;
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case 0x0f:
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return 4;
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case 0xff:
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return 8;
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default:
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return 0;
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}
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}
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/* Given the hardware breakpoint or watchpoint type TYPE and its
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length LEN, return the expected encoding for a hardware
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breakpoint/watchpoint control register. */
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static unsigned int
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aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
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{
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unsigned int ctrl, ttype;
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/* type */
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switch (type)
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{
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case hw_write:
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ttype = 2;
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break;
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case hw_read:
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ttype = 1;
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break;
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case hw_access:
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ttype = 3;
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break;
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case hw_execute:
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ttype = 0;
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break;
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default:
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perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
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}
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/* type */
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ctrl = ttype << 3;
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/* length bitmask */
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ctrl |= ((1 << len) - 1) << 5;
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/* enabled at el0 */
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ctrl |= (2 << 1) | 1;
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return ctrl;
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}
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/* Addresses to be written to the hardware breakpoint and watchpoint
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value registers need to be aligned; the alignment is 4-byte and
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8-type respectively. Linux kernel rejects any non-aligned address
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it receives from the related ptrace call. Furthermore, the kernel
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currently only supports the following Byte Address Select (BAS)
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values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
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watchpoint to be accepted by the kernel (via ptrace call), its
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valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
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Despite these limitations, the unaligned watchpoint is supported in
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this gdbserver port.
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Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
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static int
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aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
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{
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unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
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: AARCH64_HBP_ALIGNMENT;
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if (addr & (alignment - 1))
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return 0;
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if (len != 8 && len != 4 && len != 2 && len != 1)
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return 0;
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return 1;
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}
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/* Given the (potentially unaligned) watchpoint address in ADDR and
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length in LEN, return the aligned address and aligned length in
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*ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
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aligned address and length will be valid to be written to the
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hardware watchpoint value and control registers. See the comment
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above aarch64_point_is_aligned for the information about the
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alignment requirement. The given watchpoint may get truncated if
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more than one hardware register is needed to cover the watched
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region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
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address and length of the remaining part of the watchpoint (which
|
|
can be processed by calling this routine again to generate another
|
|
aligned address and length pair.
|
|
|
|
Essentially, unaligned watchpoint is achieved by minimally
|
|
enlarging the watched area to meet the alignment requirement, and
|
|
if necessary, splitting the watchpoint over several hardware
|
|
watchpoint registers. The trade-off is that there will be
|
|
false-positive hits for the read-type or the access-type hardware
|
|
watchpoints; for the write type, which is more commonly used, there
|
|
will be no such issues, as the higher-level breakpoint management
|
|
in gdb always examines the exact watched region for any content
|
|
change, and transparently resumes a thread from a watchpoint trap
|
|
if there is no change to the watched region.
|
|
|
|
Another limitation is that because the watched region is enlarged,
|
|
the watchpoint fault address returned by
|
|
aarch64_stopped_data_address may be outside of the original watched
|
|
region, especially when the triggering instruction is accessing a
|
|
larger region. When the fault address is not within any known
|
|
range, watchpoints_triggered in gdb will get confused, as the
|
|
higher-level watchpoint management is only aware of original
|
|
watched regions, and will think that some unknown watchpoint has
|
|
been triggered. In such a case, gdb may stop without displaying
|
|
any detailed information.
|
|
|
|
Once the kernel provides the full support for Byte Address Select
|
|
(BAS) in the hardware watchpoint control register, these
|
|
limitations can be largely relaxed with some further work. */
|
|
|
|
static void
|
|
aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
|
|
int *aligned_len_p, CORE_ADDR *next_addr_p,
|
|
int *next_len_p)
|
|
{
|
|
int aligned_len;
|
|
unsigned int offset;
|
|
CORE_ADDR aligned_addr;
|
|
const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
|
|
const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
|
|
|
|
/* As assumed by the algorithm. */
|
|
gdb_assert (alignment == max_wp_len);
|
|
|
|
if (len <= 0)
|
|
return;
|
|
|
|
/* Address to be put into the hardware watchpoint value register
|
|
must be aligned. */
|
|
offset = addr & (alignment - 1);
|
|
aligned_addr = addr - offset;
|
|
|
|
gdb_assert (offset >= 0 && offset < alignment);
|
|
gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
|
|
gdb_assert ((offset + len) > 0);
|
|
|
|
if (offset + len >= max_wp_len)
|
|
{
|
|
/* Need more than one watchpoint registers; truncate it at the
|
|
alignment boundary. */
|
|
aligned_len = max_wp_len;
|
|
len -= (max_wp_len - offset);
|
|
addr += (max_wp_len - offset);
|
|
gdb_assert ((addr & (alignment - 1)) == 0);
|
|
}
|
|
else
|
|
{
|
|
/* Find the smallest valid length that is large enough to
|
|
accommodate this watchpoint. */
|
|
static const unsigned char
|
|
aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
|
|
{ 1, 2, 4, 4, 8, 8, 8, 8 };
|
|
|
|
aligned_len = aligned_len_array[offset + len - 1];
|
|
addr += len;
|
|
len = 0;
|
|
}
|
|
|
|
if (aligned_addr_p != NULL)
|
|
*aligned_addr_p = aligned_addr;
|
|
if (aligned_len_p != NULL)
|
|
*aligned_len_p = aligned_len;
|
|
if (next_addr_p != NULL)
|
|
*next_addr_p = addr;
|
|
if (next_len_p != NULL)
|
|
*next_len_p = len;
|
|
}
|
|
|
|
/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
|
|
registers with data from *STATE. */
|
|
|
|
static void
|
|
aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
|
|
int tid, int watchpoint)
|
|
{
|
|
int i, count;
|
|
struct iovec iov;
|
|
struct user_hwdebug_state regs;
|
|
const CORE_ADDR *addr;
|
|
const unsigned int *ctrl;
|
|
|
|
memset (®s, 0, sizeof (regs));
|
|
iov.iov_base = ®s;
|
|
count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
|
|
addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
|
|
ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
|
|
if (count == 0)
|
|
return;
|
|
iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
|
|
+ sizeof (regs.dbg_regs [count - 1]));
|
|
|
|
for (i = 0; i < count; i++)
|
|
{
|
|
regs.dbg_regs[i].addr = addr[i];
|
|
regs.dbg_regs[i].ctrl = ctrl[i];
|
|
}
|
|
|
|
if (ptrace (PTRACE_SETREGSET, tid,
|
|
watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
|
|
(void *) &iov))
|
|
error (_("Unexpected error setting hardware debug registers"));
|
|
}
|
|
|
|
struct aarch64_dr_update_callback_param
|
|
{
|
|
int pid;
|
|
int is_watchpoint;
|
|
unsigned int idx;
|
|
};
|
|
|
|
/* Callback function which records the information about the change of
|
|
one hardware breakpoint/watchpoint setting for the thread ENTRY.
|
|
The information is passed in via PTR.
|
|
N.B. The actual updating of hardware debug registers is not
|
|
carried out until the moment the thread is resumed. */
|
|
|
|
static int
|
|
debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
|
|
{
|
|
struct thread_info *thread = (struct thread_info *) entry;
|
|
struct lwp_info *lwp = get_thread_lwp (thread);
|
|
struct aarch64_dr_update_callback_param *param_p
|
|
= (struct aarch64_dr_update_callback_param *) ptr;
|
|
int pid = param_p->pid;
|
|
int idx = param_p->idx;
|
|
int is_watchpoint = param_p->is_watchpoint;
|
|
struct arch_lwp_info *info = lwp->arch_private;
|
|
dr_changed_t *dr_changed_ptr;
|
|
dr_changed_t dr_changed;
|
|
|
|
if (show_debug_regs)
|
|
{
|
|
fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
|
|
fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
|
|
"dr_changed_wp=0x%llx\n",
|
|
pid, lwpid_of (thread), info->dr_changed_bp,
|
|
info->dr_changed_wp);
|
|
}
|
|
|
|
dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
|
|
: &info->dr_changed_bp;
|
|
dr_changed = *dr_changed_ptr;
|
|
|
|
/* Only update the threads of this process. */
|
|
if (pid_of (thread) == pid)
|
|
{
|
|
gdb_assert (idx >= 0
|
|
&& (idx <= (is_watchpoint ? aarch64_num_wp_regs
|
|
: aarch64_num_bp_regs)));
|
|
|
|
/* The following assertion is not right, as there can be changes
|
|
that have not been made to the hardware debug registers
|
|
before new changes overwrite the old ones. This can happen,
|
|
for instance, when the breakpoint/watchpoint hit one of the
|
|
threads and the user enters continue; then what happens is:
|
|
1) all breakpoints/watchpoints are removed for all threads;
|
|
2) a single step is carried out for the thread that was hit;
|
|
3) all of the points are inserted again for all threads;
|
|
4) all threads are resumed.
|
|
The 2nd step will only affect the one thread in which the
|
|
bp/wp was hit, which means only that one thread is resumed;
|
|
remember that the actual updating only happen in
|
|
aarch64_linux_prepare_to_resume, so other threads remain
|
|
stopped during the removal and insertion of bp/wp. Therefore
|
|
for those threads, the change of insertion of the bp/wp
|
|
overwrites that of the earlier removals. (The situation may
|
|
be different when bp/wp is steppable, or in the non-stop
|
|
mode.) */
|
|
/* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
|
|
|
|
/* The actual update is done later just before resuming the lwp,
|
|
we just mark that one register pair needs updating. */
|
|
DR_MARK_N_CHANGED (dr_changed, idx);
|
|
*dr_changed_ptr = dr_changed;
|
|
|
|
/* If the lwp isn't stopped, force it to momentarily pause, so
|
|
we can update its debug registers. */
|
|
if (!lwp->stopped)
|
|
linux_stop_lwp (lwp);
|
|
}
|
|
|
|
if (show_debug_regs)
|
|
{
|
|
fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
|
|
"dr_changed_wp=0x%llx\n",
|
|
pid, lwpid_of (thread), info->dr_changed_bp,
|
|
info->dr_changed_wp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Notify each thread that their IDXth breakpoint/watchpoint register
|
|
pair needs to be updated. The message will be recorded in each
|
|
thread's arch-specific data area, the actual updating will be done
|
|
when the thread is resumed. */
|
|
|
|
void
|
|
aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
|
|
int is_watchpoint, unsigned int idx)
|
|
{
|
|
struct aarch64_dr_update_callback_param param;
|
|
|
|
/* Only update the threads of this process. */
|
|
param.pid = pid_of (current_thread);
|
|
|
|
param.is_watchpoint = is_watchpoint;
|
|
param.idx = idx;
|
|
|
|
find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
|
|
}
|
|
|
|
|
|
/* Return the pointer to the debug register state structure in the
|
|
current process' arch-specific data area. */
|
|
|
|
static struct aarch64_debug_reg_state *
|
|
aarch64_get_debug_reg_state ()
|
|
{
|
|
struct process_info *proc;
|
|
|
|
proc = current_process ();
|
|
return &proc->priv->arch_private->debug_reg_state;
|
|
}
|
|
|
|
/* Record the insertion of one breakpoint/watchpoint, as represented
|
|
by ADDR and CTRL, in the process' arch-specific data area *STATE. */
|
|
|
|
static int
|
|
aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
|
|
enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
int i, idx, num_regs, is_watchpoint;
|
|
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
|
|
CORE_ADDR *dr_addr_p;
|
|
|
|
/* Set up state pointers. */
|
|
is_watchpoint = (type != hw_execute);
|
|
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
|
|
if (is_watchpoint)
|
|
{
|
|
num_regs = aarch64_num_wp_regs;
|
|
dr_addr_p = state->dr_addr_wp;
|
|
dr_ctrl_p = state->dr_ctrl_wp;
|
|
dr_ref_count = state->dr_ref_count_wp;
|
|
}
|
|
else
|
|
{
|
|
num_regs = aarch64_num_bp_regs;
|
|
dr_addr_p = state->dr_addr_bp;
|
|
dr_ctrl_p = state->dr_ctrl_bp;
|
|
dr_ref_count = state->dr_ref_count_bp;
|
|
}
|
|
|
|
ctrl = aarch64_point_encode_ctrl_reg (type, len);
|
|
|
|
/* Find an existing or free register in our cache. */
|
|
idx = -1;
|
|
for (i = 0; i < num_regs; ++i)
|
|
{
|
|
if ((dr_ctrl_p[i] & 1) == 0)
|
|
{
|
|
gdb_assert (dr_ref_count[i] == 0);
|
|
idx = i;
|
|
/* no break; continue hunting for an exising one. */
|
|
}
|
|
else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
|
|
{
|
|
gdb_assert (dr_ref_count[i] != 0);
|
|
idx = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* No space. */
|
|
if (idx == -1)
|
|
return -1;
|
|
|
|
/* Update our cache. */
|
|
if ((dr_ctrl_p[idx] & 1) == 0)
|
|
{
|
|
/* new entry */
|
|
dr_addr_p[idx] = addr;
|
|
dr_ctrl_p[idx] = ctrl;
|
|
dr_ref_count[idx] = 1;
|
|
/* Notify the change. */
|
|
aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
|
|
}
|
|
else
|
|
{
|
|
/* existing entry */
|
|
dr_ref_count[idx]++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Record the removal of one breakpoint/watchpoint, as represented by
|
|
ADDR and CTRL, in the process' arch-specific data area *STATE. */
|
|
|
|
static int
|
|
aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
|
|
enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
int i, num_regs, is_watchpoint;
|
|
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
|
|
CORE_ADDR *dr_addr_p;
|
|
|
|
/* Set up state pointers. */
|
|
is_watchpoint = (type != hw_execute);
|
|
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
|
|
if (is_watchpoint)
|
|
{
|
|
num_regs = aarch64_num_wp_regs;
|
|
dr_addr_p = state->dr_addr_wp;
|
|
dr_ctrl_p = state->dr_ctrl_wp;
|
|
dr_ref_count = state->dr_ref_count_wp;
|
|
}
|
|
else
|
|
{
|
|
num_regs = aarch64_num_bp_regs;
|
|
dr_addr_p = state->dr_addr_bp;
|
|
dr_ctrl_p = state->dr_ctrl_bp;
|
|
dr_ref_count = state->dr_ref_count_bp;
|
|
}
|
|
|
|
ctrl = aarch64_point_encode_ctrl_reg (type, len);
|
|
|
|
/* Find the entry that matches the ADDR and CTRL. */
|
|
for (i = 0; i < num_regs; ++i)
|
|
if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
|
|
{
|
|
gdb_assert (dr_ref_count[i] != 0);
|
|
break;
|
|
}
|
|
|
|
/* Not found. */
|
|
if (i == num_regs)
|
|
return -1;
|
|
|
|
/* Clear our cache. */
|
|
if (--dr_ref_count[i] == 0)
|
|
{
|
|
/* Clear the enable bit. */
|
|
ctrl &= ~1;
|
|
dr_addr_p[i] = 0;
|
|
dr_ctrl_p[i] = ctrl;
|
|
/* Notify the change. */
|
|
aarch64_notify_debug_reg_change (state, is_watchpoint, i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
|
|
int len, int is_insert)
|
|
{
|
|
struct aarch64_debug_reg_state *state;
|
|
|
|
/* The hardware breakpoint on AArch64 should always be 4-byte
|
|
aligned. */
|
|
if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
|
|
return -1;
|
|
|
|
state = aarch64_get_debug_reg_state ();
|
|
|
|
if (is_insert)
|
|
return aarch64_dr_state_insert_one_point (state, type, addr, len);
|
|
else
|
|
return aarch64_dr_state_remove_one_point (state, type, addr, len);
|
|
}
|
|
|
|
/* This is essentially the same as aarch64_handle_breakpoint, apart
|
|
from that it is an aligned watchpoint to be handled. */
|
|
|
|
static int
|
|
aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len, int is_insert)
|
|
{
|
|
struct aarch64_debug_reg_state *state;
|
|
|
|
state = aarch64_get_debug_reg_state ();
|
|
|
|
if (is_insert)
|
|
return aarch64_dr_state_insert_one_point (state, type, addr, len);
|
|
else
|
|
return aarch64_dr_state_remove_one_point (state, type, addr, len);
|
|
}
|
|
|
|
/* Insert/remove unaligned watchpoint by calling
|
|
aarch64_align_watchpoint repeatedly until the whole watched region,
|
|
as represented by ADDR and LEN, has been properly aligned and ready
|
|
to be written to one or more hardware watchpoint registers.
|
|
IS_INSERT indicates whether this is an insertion or a deletion.
|
|
Return 0 if succeed. */
|
|
|
|
static int
|
|
aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len, int is_insert)
|
|
{
|
|
struct aarch64_debug_reg_state *state
|
|
= aarch64_get_debug_reg_state ();
|
|
|
|
while (len > 0)
|
|
{
|
|
CORE_ADDR aligned_addr;
|
|
int aligned_len, ret;
|
|
|
|
aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
|
|
&addr, &len);
|
|
|
|
if (is_insert)
|
|
ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
|
|
aligned_len);
|
|
else
|
|
ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
|
|
aligned_len);
|
|
|
|
if (show_debug_regs)
|
|
fprintf (stderr,
|
|
"handle_unaligned_watchpoint: is_insert: %d\n"
|
|
" aligned_addr: 0x%s, aligned_len: %d\n"
|
|
" next_addr: 0x%s, next_len: %d\n",
|
|
is_insert, paddress (aligned_addr), aligned_len,
|
|
paddress (addr), len);
|
|
|
|
if (ret != 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
|
|
int len, int is_insert)
|
|
{
|
|
if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
|
|
return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
|
|
else
|
|
return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
|
|
}
|
|
|
|
static int
|
|
aarch64_supports_z_point_type (char z_type)
|
|
{
|
|
switch (z_type)
|
|
{
|
|
case Z_PACKET_HW_BP:
|
|
case Z_PACKET_WRITE_WP:
|
|
case Z_PACKET_READ_WP:
|
|
case Z_PACKET_ACCESS_WP:
|
|
return 1;
|
|
default:
|
|
/* Leave the handling of sw breakpoints with the gdb client. */
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Insert a hardware breakpoint/watchpoint.
|
|
It actually only records the info of the to-be-inserted bp/wp;
|
|
the actual insertion will happen when threads are resumed.
|
|
|
|
Return 0 if succeed;
|
|
Return 1 if TYPE is unsupported type;
|
|
Return -1 if an error occurs. */
|
|
|
|
static int
|
|
aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
|
|
int len, struct raw_breakpoint *bp)
|
|
{
|
|
int ret;
|
|
enum target_hw_bp_type targ_type;
|
|
|
|
if (show_debug_regs)
|
|
fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
|
|
(unsigned long) addr, len);
|
|
|
|
/* Determine the type from the raw breakpoint type. */
|
|
targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
|
|
|
|
if (targ_type != hw_execute)
|
|
ret =
|
|
aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
|
|
else
|
|
ret =
|
|
aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
|
|
|
|
if (show_debug_regs)
|
|
aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
|
|
"insert_point", addr, len, targ_type);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Remove a hardware breakpoint/watchpoint.
|
|
It actually only records the info of the to-be-removed bp/wp,
|
|
the actual removal will be done when threads are resumed.
|
|
|
|
Return 0 if succeed;
|
|
Return 1 if TYPE is an unsupported type;
|
|
Return -1 if an error occurs. */
|
|
|
|
static int
|
|
aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
|
|
int len, struct raw_breakpoint *bp)
|
|
{
|
|
int ret;
|
|
enum target_hw_bp_type targ_type;
|
|
|
|
if (show_debug_regs)
|
|
fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
|
|
(unsigned long) addr, len);
|
|
|
|
/* Determine the type from the raw breakpoint type. */
|
|
targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
|
|
|
|
/* Set up state pointers. */
|
|
if (targ_type != hw_execute)
|
|
ret =
|
|
aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
|
|
else
|
|
ret =
|
|
aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
|
|
|
|
if (show_debug_regs)
|
|
aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
|
|
"remove_point", addr, len, targ_type);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Returns the address associated with the watchpoint that hit, if
|
|
any; returns 0 otherwise. */
|
|
|
|
static CORE_ADDR
|
|
aarch64_stopped_data_address (void)
|
|
{
|
|
siginfo_t siginfo;
|
|
int pid, i;
|
|
struct aarch64_debug_reg_state *state;
|
|
|
|
pid = lwpid_of (current_thread);
|
|
|
|
/* Get the siginfo. */
|
|
if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
|
|
return (CORE_ADDR) 0;
|
|
|
|
/* Need to be a hardware breakpoint/watchpoint trap. */
|
|
if (siginfo.si_signo != SIGTRAP
|
|
|| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
|
|
return (CORE_ADDR) 0;
|
|
|
|
/* Check if the address matches any watched address. */
|
|
state = aarch64_get_debug_reg_state ();
|
|
for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
|
|
{
|
|
const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
|
|
const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
|
|
const CORE_ADDR addr_watch = state->dr_addr_wp[i];
|
|
if (state->dr_ref_count_wp[i]
|
|
&& DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
|
|
&& addr_trap >= addr_watch
|
|
&& addr_trap < addr_watch + len)
|
|
return addr_trap;
|
|
}
|
|
|
|
return (CORE_ADDR) 0;
|
|
}
|
|
|
|
/* Returns 1 if target was stopped due to a watchpoint hit, 0
|
|
otherwise. */
|
|
|
|
static int
|
|
aarch64_stopped_by_watchpoint (void)
|
|
{
|
|
if (aarch64_stopped_data_address () != 0)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
/* Fetch the thread-local storage pointer for libthread_db. */
|
|
|
|
ps_err_e
|
|
ps_get_thread_area (const struct ps_prochandle *ph,
|
|
lwpid_t lwpid, int idx, void **base)
|
|
{
|
|
struct iovec iovec;
|
|
uint64_t reg;
|
|
|
|
iovec.iov_base = ®
|
|
iovec.iov_len = sizeof (reg);
|
|
|
|
if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
|
|
return PS_ERR;
|
|
|
|
/* IDX is the bias from the thread pointer to the beginning of the
|
|
thread descriptor. It has to be subtracted due to implementation
|
|
quirks in libthread_db. */
|
|
*base = (void *) (reg - idx);
|
|
|
|
return PS_OK;
|
|
}
|
|
|
|
/* Called when a new process is created. */
|
|
|
|
static struct arch_process_info *
|
|
aarch64_linux_new_process (void)
|
|
{
|
|
struct arch_process_info *info = xcalloc (1, sizeof (*info));
|
|
|
|
aarch64_init_debug_reg_state (&info->debug_reg_state);
|
|
|
|
return info;
|
|
}
|
|
|
|
/* Called when a new thread is detected. */
|
|
|
|
static void
|
|
aarch64_linux_new_thread (struct lwp_info *lwp)
|
|
{
|
|
struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
|
|
|
|
/* Mark that all the hardware breakpoint/watchpoint register pairs
|
|
for this thread need to be initialized (with data from
|
|
aarch_process_info.debug_reg_state). */
|
|
DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
|
|
DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
|
|
|
|
lwp->arch_private = info;
|
|
}
|
|
|
|
static void
|
|
aarch64_linux_new_fork (struct process_info *parent,
|
|
struct process_info *child)
|
|
{
|
|
/* These are allocated by linux_add_process. */
|
|
gdb_assert (parent->priv != NULL
|
|
&& parent->priv->arch_private != NULL);
|
|
gdb_assert (child->priv != NULL
|
|
&& child->priv->arch_private != NULL);
|
|
|
|
/* Linux kernel before 2.6.33 commit
|
|
72f674d203cd230426437cdcf7dd6f681dad8b0d
|
|
will inherit hardware debug registers from parent
|
|
on fork/vfork/clone. Newer Linux kernels create such tasks with
|
|
zeroed debug registers.
|
|
|
|
GDB core assumes the child inherits the watchpoints/hw
|
|
breakpoints of the parent, and will remove them all from the
|
|
forked off process. Copy the debug registers mirrors into the
|
|
new process so that all breakpoints and watchpoints can be
|
|
removed together. The debug registers mirror will become zeroed
|
|
in the end before detaching the forked off process, thus making
|
|
this compatible with older Linux kernels too. */
|
|
|
|
*child->priv->arch_private = *parent->priv->arch_private;
|
|
}
|
|
|
|
/* Called when resuming a thread.
|
|
If the debug regs have changed, update the thread's copies. */
|
|
|
|
static void
|
|
aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
|
|
{
|
|
struct thread_info *thread = get_lwp_thread (lwp);
|
|
ptid_t ptid = ptid_of (thread);
|
|
struct arch_lwp_info *info = lwp->arch_private;
|
|
|
|
if (DR_HAS_CHANGED (info->dr_changed_bp)
|
|
|| DR_HAS_CHANGED (info->dr_changed_wp))
|
|
{
|
|
int tid = ptid_get_lwp (ptid);
|
|
struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
|
|
struct aarch64_debug_reg_state *state
|
|
= &proc->priv->arch_private->debug_reg_state;
|
|
|
|
if (show_debug_regs)
|
|
fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
|
|
|
|
/* Watchpoints. */
|
|
if (DR_HAS_CHANGED (info->dr_changed_wp))
|
|
{
|
|
aarch64_linux_set_debug_regs (state, tid, 1);
|
|
DR_CLEAR_CHANGED (info->dr_changed_wp);
|
|
}
|
|
|
|
/* Breakpoints. */
|
|
if (DR_HAS_CHANGED (info->dr_changed_bp))
|
|
{
|
|
aarch64_linux_set_debug_regs (state, tid, 0);
|
|
DR_CLEAR_CHANGED (info->dr_changed_bp);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* ptrace hardware breakpoint resource info is formatted as follows:
|
|
|
|
31 24 16 8 0
|
|
+---------------+--------------+---------------+---------------+
|
|
| RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
|
|
+---------------+--------------+---------------+---------------+ */
|
|
|
|
#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
|
|
#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
|
|
#define AARCH64_DEBUG_ARCH_V8 0x6
|
|
|
|
static void
|
|
aarch64_arch_setup (void)
|
|
{
|
|
int pid;
|
|
struct iovec iov;
|
|
struct user_hwdebug_state dreg_state;
|
|
|
|
current_process ()->tdesc = tdesc_aarch64;
|
|
|
|
pid = lwpid_of (current_thread);
|
|
iov.iov_base = &dreg_state;
|
|
iov.iov_len = sizeof (dreg_state);
|
|
|
|
/* Get hardware watchpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
|
|
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
|
|
{
|
|
aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
|
|
{
|
|
warning ("Unexpected number of hardware watchpoint registers reported"
|
|
" by ptrace, got %d, expected %d.",
|
|
aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
|
|
aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning ("Unable to determine the number of hardware watchpoints"
|
|
" available.");
|
|
aarch64_num_wp_regs = 0;
|
|
}
|
|
|
|
/* Get hardware breakpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
|
|
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
|
|
{
|
|
aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
|
|
{
|
|
warning ("Unexpected number of hardware breakpoint registers reported"
|
|
" by ptrace, got %d, expected %d.",
|
|
aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
|
|
aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning ("Unable to determine the number of hardware breakpoints"
|
|
" available.");
|
|
aarch64_num_bp_regs = 0;
|
|
}
|
|
}
|
|
|
|
static struct regset_info aarch64_regsets[] =
|
|
{
|
|
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
|
|
sizeof (struct user_pt_regs), GENERAL_REGS,
|
|
aarch64_fill_gregset, aarch64_store_gregset },
|
|
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
|
|
sizeof (struct user_fpsimd_state), FP_REGS,
|
|
aarch64_fill_fpregset, aarch64_store_fpregset
|
|
},
|
|
{ 0, 0, 0, -1, -1, NULL, NULL }
|
|
};
|
|
|
|
static struct regsets_info aarch64_regsets_info =
|
|
{
|
|
aarch64_regsets, /* regsets */
|
|
0, /* num_regsets */
|
|
NULL, /* disabled_regsets */
|
|
};
|
|
|
|
static struct usrregs_info aarch64_usrregs_info =
|
|
{
|
|
AARCH64_NUM_REGS,
|
|
aarch64_regmap,
|
|
};
|
|
|
|
static struct regs_info regs_info =
|
|
{
|
|
NULL, /* regset_bitmap */
|
|
&aarch64_usrregs_info,
|
|
&aarch64_regsets_info,
|
|
};
|
|
|
|
static const struct regs_info *
|
|
aarch64_regs_info (void)
|
|
{
|
|
return ®s_info;
|
|
}
|
|
|
|
struct linux_target_ops the_low_target =
|
|
{
|
|
aarch64_arch_setup,
|
|
aarch64_regs_info,
|
|
aarch64_cannot_fetch_register,
|
|
aarch64_cannot_store_register,
|
|
NULL,
|
|
aarch64_get_pc,
|
|
aarch64_set_pc,
|
|
(const unsigned char *) &aarch64_breakpoint,
|
|
aarch64_breakpoint_len,
|
|
NULL,
|
|
0,
|
|
aarch64_breakpoint_at,
|
|
aarch64_supports_z_point_type,
|
|
aarch64_insert_point,
|
|
aarch64_remove_point,
|
|
aarch64_stopped_by_watchpoint,
|
|
aarch64_stopped_data_address,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
aarch64_linux_new_process,
|
|
aarch64_linux_new_thread,
|
|
aarch64_linux_new_fork,
|
|
aarch64_linux_prepare_to_resume,
|
|
};
|
|
|
|
void
|
|
initialize_low_arch (void)
|
|
{
|
|
init_registers_aarch64 ();
|
|
|
|
initialize_regsets_info (&aarch64_regsets_info);
|
|
}
|