a6743a5420
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1039 lines
24 KiB
C
1039 lines
24 KiB
C
/* Altera Nios II disassemble routines
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Copyright (C) 2012-2018 Free Software Foundation, Inc.
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Contributed by Nigel Gray (ngray@altera.com).
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Contributed by Mentor Graphics, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "disassemble.h"
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#include "opintl.h"
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#include "opcode/nios2.h"
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#include "libiberty.h"
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#include <string.h>
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#include <assert.h>
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/* No symbol table is available when this code runs out in an embedded
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system as when it is used for disassembler support in a monitor. */
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#if !defined(EMBEDDED_ENV)
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#define SYMTAB_AVAILABLE 1
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#include "elf-bfd.h"
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#include "elf/nios2.h"
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#endif
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/* Default length of Nios II instruction in bytes. */
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#define INSNLEN 4
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/* Data structures used by the opcode hash table. */
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typedef struct _nios2_opcode_hash
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{
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const struct nios2_opcode *opcode;
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struct _nios2_opcode_hash *next;
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} nios2_opcode_hash;
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/* Hash table size. */
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#define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
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/* Extract the opcode from an instruction word. */
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static unsigned int
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nios2_r1_extract_opcode (unsigned int x)
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{
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return GET_IW_R1_OP (x);
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}
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static unsigned int
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nios2_r2_extract_opcode (unsigned int x)
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{
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return GET_IW_R2_OP (x);
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}
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/* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops
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are stored in a different table than regular instructions. */
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typedef struct _nios2_disassembler_state
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{
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const struct nios2_opcode *opcodes;
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const int *num_opcodes;
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unsigned int (*extract_opcode) (unsigned int);
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nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
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nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
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const struct nios2_opcode *nop;
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bfd_boolean init;
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} nios2_disassembler_state;
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static nios2_disassembler_state
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nios2_r1_disassembler_state = {
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nios2_r1_opcodes,
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&nios2_num_r1_opcodes,
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nios2_r1_extract_opcode,
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{},
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{},
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NULL,
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0
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};
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static nios2_disassembler_state
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nios2_r2_disassembler_state = {
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nios2_r2_opcodes,
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&nios2_num_r2_opcodes,
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nios2_r2_extract_opcode,
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{},
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{},
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NULL,
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0
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};
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/* Function to initialize the opcode hash table. */
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static void
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nios2_init_opcode_hash (nios2_disassembler_state *state)
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{
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unsigned int i;
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register const struct nios2_opcode *op;
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for (i = 0; i < OPCODE_HASH_SIZE; i++)
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for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
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{
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nios2_opcode_hash *new_hash;
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nios2_opcode_hash **bucket = NULL;
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if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
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{
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if (i == state->extract_opcode (op->match)
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&& (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
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& 0x7fffffff))
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{
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bucket = &(state->ps_hash[i]);
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if (strcmp (op->name, "nop") == 0)
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state->nop = op;
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}
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}
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else if (i == state->extract_opcode (op->match))
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bucket = &(state->hash[i]);
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if (bucket)
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{
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new_hash =
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(nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
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if (new_hash == NULL)
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{
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/* xgettext:c-format */
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opcodes_error_handler (_("out of memory"));
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exit (1);
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}
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new_hash->opcode = op;
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new_hash->next = NULL;
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while (*bucket)
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bucket = &((*bucket)->next);
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*bucket = new_hash;
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}
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}
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state->init = 1;
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#ifdef DEBUG_HASHTABLE
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for (i = 0; i < OPCODE_HASH_SIZE; ++i)
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{
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nios2_opcode_hash *tmp_hash = state->hash[i];
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printf ("index: 0x%02X ops: ", i);
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while (tmp_hash != NULL)
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{
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printf ("%s ", tmp_hash->opcode->name);
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tmp_hash = tmp_hash->next;
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}
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printf ("\n");
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}
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for (i = 0; i < OPCODE_HASH_SIZE; ++i)
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{
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nios2_opcode_hash *tmp_hash = state->ps_hash[i];
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printf ("index: 0x%02X ops: ", i);
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while (tmp_hash != NULL)
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{
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printf ("%s ", tmp_hash->opcode->name);
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tmp_hash = tmp_hash->next;
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}
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printf ("\n");
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}
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#endif /* DEBUG_HASHTABLE */
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}
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/* Return a pointer to an nios2_opcode struct for a given instruction
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word OPCODE for bfd machine MACH, or NULL if there is an error. */
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const struct nios2_opcode *
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nios2_find_opcode_hash (unsigned long opcode, unsigned long mach)
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{
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nios2_opcode_hash *entry;
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nios2_disassembler_state *state;
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/* Select the right instruction set, hash tables, and opcode accessor
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for the mach variant. */
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if (mach == bfd_mach_nios2r2)
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state = &nios2_r2_disassembler_state;
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else
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state = &nios2_r1_disassembler_state;
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/* Build a hash table to shorten the search time. */
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if (!state->init)
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nios2_init_opcode_hash (state);
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/* Check for NOP first. Both NOP and MOV are macros that expand into
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an ADD instruction, and we always want to give priority to NOP. */
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if (state->nop->match == (opcode & state->nop->mask))
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return state->nop;
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/* First look in the pseudo-op hashtable. */
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for (entry = state->ps_hash[state->extract_opcode (opcode)];
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entry; entry = entry->next)
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if (entry->opcode->match == (opcode & entry->opcode->mask))
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return entry->opcode;
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/* Otherwise look in the main hashtable. */
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for (entry = state->hash[state->extract_opcode (opcode)];
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entry; entry = entry->next)
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if (entry->opcode->match == (opcode & entry->opcode->mask))
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return entry->opcode;
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return NULL;
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}
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/* There are 32 regular registers, 32 coprocessor registers,
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and 32 control registers. */
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#define NUMREGNAMES 32
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/* Return a pointer to the base of the coprocessor register name array. */
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static struct nios2_reg *
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nios2_coprocessor_regs (void)
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{
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static struct nios2_reg *cached = NULL;
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if (!cached)
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{
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int i;
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for (i = NUMREGNAMES; i < nios2_num_regs; i++)
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if (!strcmp (nios2_regs[i].name, "c0"))
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{
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cached = nios2_regs + i;
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break;
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}
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assert (cached);
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}
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return cached;
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}
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/* Return a pointer to the base of the control register name array. */
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static struct nios2_reg *
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nios2_control_regs (void)
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{
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static struct nios2_reg *cached = NULL;
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if (!cached)
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{
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int i;
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for (i = NUMREGNAMES; i < nios2_num_regs; i++)
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if (!strcmp (nios2_regs[i].name, "status"))
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{
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cached = nios2_regs + i;
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break;
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}
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assert (cached);
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}
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return cached;
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}
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/* Helper routine to report internal errors. */
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static void
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bad_opcode (const struct nios2_opcode *op)
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{
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opcodes_error_handler
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/* xgettext:c-format */
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(_("internal error: broken opcode descriptor for `%s %s'"),
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op->name, op->args);
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abort ();
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}
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/* The function nios2_print_insn_arg uses the character pointed
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to by ARGPTR to determine how it print the next token or separator
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character in the arguments to an instruction. */
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static int
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nios2_print_insn_arg (const char *argptr,
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unsigned long opcode, bfd_vma address,
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disassemble_info *info,
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const struct nios2_opcode *op)
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{
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unsigned long i = 0;
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struct nios2_reg *reg_base;
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switch (*argptr)
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{
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case ',':
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case '(':
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case ')':
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(*info->fprintf_func) (info->stream, "%c", *argptr);
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break;
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case 'c':
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/* Control register index. */
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_IMM5 (opcode);
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break;
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case iw_F3X6L5_type:
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i = GET_IW_F3X6L5_IMM5 (opcode);
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break;
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default:
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bad_opcode (op);
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}
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reg_base = nios2_control_regs ();
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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break;
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case 'd':
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reg_base = nios2_regs;
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_C (opcode);
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_C (opcode);
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if (GET_IW_CUSTOM_READC (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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break;
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case iw_F3X6L5_type:
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case iw_F3X6_type:
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i = GET_IW_F3X6L5_C (opcode);
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break;
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case iw_F3X8_type:
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i = GET_IW_F3X8_C (opcode);
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if (GET_IW_F3X8_READC (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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break;
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case iw_F2_type:
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i = GET_IW_F2_B (opcode);
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break;
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default:
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bad_opcode (op);
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}
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if (i < NUMREGNAMES)
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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else
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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case 's':
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reg_base = nios2_regs;
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_A (opcode);
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break;
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case iw_i_type:
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i = GET_IW_I_A (opcode);
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_A (opcode);
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if (GET_IW_CUSTOM_READA (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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break;
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case iw_F2I16_type:
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i = GET_IW_F2I16_A (opcode);
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break;
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case iw_F2X4I12_type:
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i = GET_IW_F2X4I12_A (opcode);
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break;
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case iw_F1X4I12_type:
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i = GET_IW_F1X4I12_A (opcode);
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break;
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case iw_F1X4L17_type:
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i = GET_IW_F1X4L17_A (opcode);
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break;
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case iw_F3X6L5_type:
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case iw_F3X6_type:
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i = GET_IW_F3X6L5_A (opcode);
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break;
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case iw_F2X6L10_type:
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i = GET_IW_F2X6L10_A (opcode);
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break;
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case iw_F3X8_type:
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i = GET_IW_F3X8_A (opcode);
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if (GET_IW_F3X8_READA (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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break;
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case iw_F1X1_type:
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i = GET_IW_F1X1_A (opcode);
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break;
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case iw_F1I5_type:
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i = 27; /* Implicit stack pointer reference. */
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break;
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case iw_F2_type:
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i = GET_IW_F2_A (opcode);
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break;
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default:
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bad_opcode (op);
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}
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if (i < NUMREGNAMES)
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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else
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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case 't':
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reg_base = nios2_regs;
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_B (opcode);
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break;
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case iw_i_type:
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i = GET_IW_I_B (opcode);
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_B (opcode);
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if (GET_IW_CUSTOM_READB (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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break;
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case iw_F2I16_type:
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i = GET_IW_F2I16_B (opcode);
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break;
|
|
case iw_F2X4I12_type:
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i = GET_IW_F2X4I12_B (opcode);
|
|
break;
|
|
case iw_F3X6L5_type:
|
|
case iw_F3X6_type:
|
|
i = GET_IW_F3X6L5_B (opcode);
|
|
break;
|
|
case iw_F2X6L10_type:
|
|
i = GET_IW_F2X6L10_B (opcode);
|
|
break;
|
|
case iw_F3X8_type:
|
|
i = GET_IW_F3X8_B (opcode);
|
|
if (GET_IW_F3X8_READB (opcode) == 0)
|
|
reg_base = nios2_coprocessor_regs ();
|
|
break;
|
|
case iw_F1I5_type:
|
|
i = GET_IW_F1I5_B (opcode);
|
|
break;
|
|
case iw_F2_type:
|
|
i = GET_IW_F2_B (opcode);
|
|
break;
|
|
case iw_T1X1I6_type:
|
|
i = 0;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
if (i < NUMREGNAMES)
|
|
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "unknown");
|
|
break;
|
|
|
|
case 'D':
|
|
switch (op->format)
|
|
{
|
|
case iw_T1I7_type:
|
|
i = GET_IW_T1I7_A3 (opcode);
|
|
break;
|
|
case iw_T2X1L3_type:
|
|
i = GET_IW_T2X1L3_B3 (opcode);
|
|
break;
|
|
case iw_T2X1I3_type:
|
|
i = GET_IW_T2X1I3_B3 (opcode);
|
|
break;
|
|
case iw_T3X1_type:
|
|
i = GET_IW_T3X1_C3 (opcode);
|
|
break;
|
|
case iw_T2X3_type:
|
|
if (op->num_args == 3)
|
|
i = GET_IW_T2X3_A3 (opcode);
|
|
else
|
|
i = GET_IW_T2X3_B3 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
i = nios2_r2_reg3_mappings[i];
|
|
(*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
|
|
break;
|
|
|
|
case 'M':
|
|
/* 6-bit unsigned immediate with no shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T1X1I6_type:
|
|
i = GET_IW_T1X1I6_IMM6 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'N':
|
|
/* 6-bit unsigned immediate with 2-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T1X1I6_type:
|
|
i = GET_IW_T1X1I6_IMM6 (opcode) << 2;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'S':
|
|
switch (op->format)
|
|
{
|
|
case iw_T1I7_type:
|
|
i = GET_IW_T1I7_A3 (opcode);
|
|
break;
|
|
case iw_T2I4_type:
|
|
i = GET_IW_T2I4_A3 (opcode);
|
|
break;
|
|
case iw_T2X1L3_type:
|
|
i = GET_IW_T2X1L3_A3 (opcode);
|
|
break;
|
|
case iw_T2X1I3_type:
|
|
i = GET_IW_T2X1I3_A3 (opcode);
|
|
break;
|
|
case iw_T3X1_type:
|
|
i = GET_IW_T3X1_A3 (opcode);
|
|
break;
|
|
case iw_T2X3_type:
|
|
i = GET_IW_T2X3_A3 (opcode);
|
|
break;
|
|
case iw_T1X1I6_type:
|
|
i = GET_IW_T1X1I6_A3 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
i = nios2_r2_reg3_mappings[i];
|
|
(*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
|
|
break;
|
|
|
|
case 'T':
|
|
switch (op->format)
|
|
{
|
|
case iw_T2I4_type:
|
|
i = GET_IW_T2I4_B3 (opcode);
|
|
break;
|
|
case iw_T3X1_type:
|
|
i = GET_IW_T3X1_B3 (opcode);
|
|
break;
|
|
case iw_T2X3_type:
|
|
i = GET_IW_T2X3_B3 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
i = nios2_r2_reg3_mappings[i];
|
|
(*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
|
|
break;
|
|
|
|
case 'i':
|
|
/* 16-bit signed immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_i_type:
|
|
i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
|
|
break;
|
|
case iw_F2I16_type:
|
|
i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'I':
|
|
/* 12-bit signed immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_F2X4I12_type:
|
|
i = (signed) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20;
|
|
break;
|
|
case iw_F1X4I12_type:
|
|
i = (signed) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'u':
|
|
/* 16-bit unsigned immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_i_type:
|
|
i = GET_IW_I_IMM16 (opcode);
|
|
break;
|
|
case iw_F2I16_type:
|
|
i = GET_IW_F2I16_IMM16 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'U':
|
|
/* 7-bit unsigned immediate with 2-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T1I7_type:
|
|
i = GET_IW_T1I7_IMM7 (opcode) << 2;
|
|
break;
|
|
case iw_X1I7_type:
|
|
i = GET_IW_X1I7_IMM7 (opcode) << 2;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'V':
|
|
/* 5-bit unsigned immediate with 2-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_F1I5_type:
|
|
i = GET_IW_F1I5_IMM5 (opcode) << 2;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'W':
|
|
/* 4-bit unsigned immediate with 2-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2I4_type:
|
|
i = GET_IW_T2I4_IMM4 (opcode) << 2;
|
|
break;
|
|
case iw_L5I4X1_type:
|
|
i = GET_IW_L5I4X1_IMM4 (opcode) << 2;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'X':
|
|
/* 4-bit unsigned immediate with 1-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2I4_type:
|
|
i = GET_IW_T2I4_IMM4 (opcode) << 1;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'Y':
|
|
/* 4-bit unsigned immediate without shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2I4_type:
|
|
i = GET_IW_T2I4_IMM4 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'o':
|
|
/* 16-bit signed immediate address offset. */
|
|
switch (op->format)
|
|
{
|
|
case iw_i_type:
|
|
i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
|
|
break;
|
|
case iw_F2I16_type:
|
|
i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
address = address + 4 + i;
|
|
(*info->print_address_func) (address, info);
|
|
break;
|
|
|
|
case 'O':
|
|
/* 10-bit signed address offset with 1-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_I10_type:
|
|
i = (signed) (GET_IW_I10_IMM10 (opcode) << 22) >> 21;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
address = address + 2 + i;
|
|
(*info->print_address_func) (address, info);
|
|
break;
|
|
|
|
case 'P':
|
|
/* 7-bit signed address offset with 1-bit shift. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T1I7_type:
|
|
i = (signed) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
address = address + 2 + i;
|
|
(*info->print_address_func) (address, info);
|
|
break;
|
|
|
|
case 'j':
|
|
/* 5-bit unsigned immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_r_type:
|
|
i = GET_IW_R_IMM5 (opcode);
|
|
break;
|
|
case iw_F3X6L5_type:
|
|
i = GET_IW_F3X6L5_IMM5 (opcode);
|
|
break;
|
|
case iw_F2X6L10_type:
|
|
i = GET_IW_F2X6L10_MSB (opcode);
|
|
break;
|
|
case iw_X2L5_type:
|
|
i = GET_IW_X2L5_IMM5 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'k':
|
|
/* Second 5-bit unsigned immediate field. */
|
|
switch (op->format)
|
|
{
|
|
case iw_F2X6L10_type:
|
|
i = GET_IW_F2X6L10_LSB (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'l':
|
|
/* 8-bit unsigned immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_custom_type:
|
|
i = GET_IW_CUSTOM_N (opcode);
|
|
break;
|
|
case iw_F3X8_type:
|
|
i = GET_IW_F3X8_N (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%lu", i);
|
|
break;
|
|
|
|
case 'm':
|
|
/* 26-bit unsigned immediate. */
|
|
switch (op->format)
|
|
{
|
|
case iw_j_type:
|
|
i = GET_IW_J_IMM26 (opcode);
|
|
break;
|
|
case iw_L26_type:
|
|
i = GET_IW_L26_IMM26 (opcode);
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
/* This translates to an address because it's only used in call
|
|
instructions. */
|
|
address = (address & 0xf0000000) | (i << 2);
|
|
(*info->print_address_func) (address, info);
|
|
break;
|
|
|
|
case 'e':
|
|
/* Encoded enumeration for addi.n/subi.n. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2X1I3_type:
|
|
i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%lu", i);
|
|
break;
|
|
|
|
case 'f':
|
|
/* Encoded enumeration for slli.n/srli.n. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2X1L3_type:
|
|
i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%lu", i);
|
|
break;
|
|
|
|
case 'g':
|
|
/* Encoded enumeration for andi.n. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T2I4_type:
|
|
i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)];
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%lu", i);
|
|
break;
|
|
|
|
case 'h':
|
|
/* Encoded enumeration for movi.n. */
|
|
switch (op->format)
|
|
{
|
|
case iw_T1I7_type:
|
|
i = GET_IW_T1I7_IMM7 (opcode);
|
|
if (i == 125)
|
|
i = 0xff;
|
|
else if (i == 126)
|
|
i = -2;
|
|
else if (i == 127)
|
|
i = -1;
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "%ld", i);
|
|
break;
|
|
|
|
case 'R':
|
|
{
|
|
unsigned long reglist = 0;
|
|
int dir = 1;
|
|
int k, t;
|
|
|
|
switch (op->format)
|
|
{
|
|
case iw_F1X4L17_type:
|
|
/* Encoding for ldwm/stwm. */
|
|
i = GET_IW_F1X4L17_REGMASK (opcode);
|
|
if (GET_IW_F1X4L17_RS (opcode))
|
|
{
|
|
reglist = ((i << 14) & 0x00ffc000);
|
|
if (i & (1 << 10))
|
|
reglist |= (1 << 28);
|
|
if (i & (1 << 11))
|
|
reglist |= (1 << 31);
|
|
}
|
|
else
|
|
reglist = i << 2;
|
|
dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1;
|
|
break;
|
|
|
|
case iw_L5I4X1_type:
|
|
/* Encoding for push.n/pop.n. */
|
|
reglist |= (1 << 31);
|
|
if (GET_IW_L5I4X1_FP (opcode))
|
|
reglist |= (1 << 28);
|
|
if (GET_IW_L5I4X1_CS (opcode))
|
|
{
|
|
int val = GET_IW_L5I4X1_REGRANGE (opcode);
|
|
reglist |= nios2_r2_reg_range_mappings[val];
|
|
}
|
|
dir = (op->match == MATCH_R2_POP_N ? 1 : -1);
|
|
break;
|
|
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
|
|
t = 0;
|
|
(*info->fprintf_func) (info->stream, "{");
|
|
for (k = (dir == 1 ? 0 : 31);
|
|
(dir == 1 && k < 32) || (dir == -1 && k >= 0);
|
|
k += dir)
|
|
if (reglist & (1 << k))
|
|
{
|
|
if (t)
|
|
(*info->fprintf_func) (info->stream, ",");
|
|
else
|
|
t++;
|
|
(*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name);
|
|
}
|
|
(*info->fprintf_func) (info->stream, "}");
|
|
break;
|
|
}
|
|
|
|
case 'B':
|
|
/* Base register and options for ldwm/stwm. */
|
|
switch (op->format)
|
|
{
|
|
case iw_F1X4L17_type:
|
|
if (GET_IW_F1X4L17_ID (opcode) == 0)
|
|
(*info->fprintf_func) (info->stream, "--");
|
|
|
|
i = GET_IW_F1X4I12_A (opcode);
|
|
(*info->fprintf_func) (info->stream, "(%s)",
|
|
nios2_builtin_regs[i].name);
|
|
|
|
if (GET_IW_F1X4L17_ID (opcode))
|
|
(*info->fprintf_func) (info->stream, "++");
|
|
if (GET_IW_F1X4L17_WB (opcode))
|
|
(*info->fprintf_func) (info->stream, ",writeback");
|
|
if (GET_IW_F1X4L17_PC (opcode))
|
|
(*info->fprintf_func) (info->stream, ",ret");
|
|
break;
|
|
default:
|
|
bad_opcode (op);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
(*info->fprintf_func) (info->stream, "unknown");
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* nios2_disassemble does all the work of disassembling a Nios II
|
|
instruction opcode. */
|
|
static int
|
|
nios2_disassemble (bfd_vma address, unsigned long opcode,
|
|
disassemble_info *info)
|
|
{
|
|
const struct nios2_opcode *op;
|
|
|
|
info->bytes_per_line = INSNLEN;
|
|
info->bytes_per_chunk = INSNLEN;
|
|
info->display_endian = info->endian;
|
|
info->insn_info_valid = 1;
|
|
info->branch_delay_insns = 0;
|
|
info->data_size = 0;
|
|
info->insn_type = dis_nonbranch;
|
|
info->target = 0;
|
|
info->target2 = 0;
|
|
|
|
/* Find the major opcode and use this to disassemble
|
|
the instruction and its arguments. */
|
|
op = nios2_find_opcode_hash (opcode, info->mach);
|
|
|
|
if (op != NULL)
|
|
{
|
|
const char *argstr = op->args;
|
|
(*info->fprintf_func) (info->stream, "%s", op->name);
|
|
if (argstr != NULL && *argstr != '\0')
|
|
{
|
|
(*info->fprintf_func) (info->stream, "\t");
|
|
while (*argstr != '\0')
|
|
{
|
|
nios2_print_insn_arg (argstr, opcode, address, info, op);
|
|
++argstr;
|
|
}
|
|
}
|
|
/* Tell the caller how far to advance the program counter. */
|
|
info->bytes_per_chunk = op->size;
|
|
return op->size;
|
|
}
|
|
else
|
|
{
|
|
/* Handle undefined instructions. */
|
|
info->insn_type = dis_noninsn;
|
|
(*info->fprintf_func) (info->stream, "0x%lx", opcode);
|
|
return INSNLEN;
|
|
}
|
|
}
|
|
|
|
|
|
/* print_insn_nios2 is the main disassemble function for Nios II.
|
|
The function diassembler(abfd) (source in disassemble.c) returns a
|
|
pointer to this either print_insn_big_nios2 or
|
|
print_insn_little_nios2, which in turn call this function when the
|
|
bfd machine type is Nios II. print_insn_nios2 reads the
|
|
instruction word at the address given, and prints the disassembled
|
|
instruction on the stream info->stream using info->fprintf_func. */
|
|
|
|
static int
|
|
print_insn_nios2 (bfd_vma address, disassemble_info *info,
|
|
enum bfd_endian endianness)
|
|
{
|
|
bfd_byte buffer[INSNLEN];
|
|
int status;
|
|
|
|
status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
|
|
if (status == 0)
|
|
{
|
|
unsigned long insn;
|
|
if (endianness == BFD_ENDIAN_BIG)
|
|
insn = (unsigned long) bfd_getb32 (buffer);
|
|
else
|
|
insn = (unsigned long) bfd_getl32 (buffer);
|
|
return nios2_disassemble (address, insn, info);
|
|
}
|
|
|
|
/* We might have a 16-bit R2 instruction at the end of memory. Try that. */
|
|
if (info->mach == bfd_mach_nios2r2)
|
|
{
|
|
status = (*info->read_memory_func) (address, buffer, 2, info);
|
|
if (status == 0)
|
|
{
|
|
unsigned long insn;
|
|
if (endianness == BFD_ENDIAN_BIG)
|
|
insn = (unsigned long) bfd_getb16 (buffer);
|
|
else
|
|
insn = (unsigned long) bfd_getl16 (buffer);
|
|
return nios2_disassemble (address, insn, info);
|
|
}
|
|
}
|
|
|
|
/* If we got here, we couldn't read anything. */
|
|
(*info->memory_error_func) (status, address, info);
|
|
return -1;
|
|
}
|
|
|
|
/* These two functions are the main entry points, accessed from
|
|
disassemble.c. */
|
|
int
|
|
print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
|
|
{
|
|
return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
|
|
}
|
|
|
|
int
|
|
print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
|
|
{
|
|
return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
|
|
}
|