101 lines
3.5 KiB
Plaintext
101 lines
3.5 KiB
Plaintext
#
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# This file is part of the program psim.
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#
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# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#
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#
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# Instruction unpacking:
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#
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# Once the instruction has been decoded, the register (and other)
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# fields within the instruction need to be extracted.
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#
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# The table that follows determines how each field should be treated.
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# Importantly it considers the case where the extracted field is to
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# be used immediatly or stored in an instruction cache.
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#
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# <valid>
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#
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# Zero marks the end of the table. More importantly 1. indicates
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# that the entry is valid and can be cached. 2. indicates that that
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# the entry is valid but can not be cached.
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#
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# <old_name>
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#
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# The field name as given in the instruction spec.
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#
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# <new_name>
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#
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# A name for <old_name> once it has been extracted from the
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# instructioin (and possibly stored in the instruction cache).
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#
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# <type>
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#
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# String specifying the storage type for <new_name> (the extracted
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# field>.
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#
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# <expression>
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#
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# Specifies how to get <new_name> from <old_name>. If null, old and
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# new name had better be the same. */
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#
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#
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1:RA:RA::
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1:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA)
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1:RA:RA_BITMASK:unsigned32:(1 << RA)
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1:RT:RT::
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1:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT)
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1:RT:RT_BITMASK:unsigned32:(1 << RT)
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2:RS:RS::
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1:RS:rS:signed_word *:(cpu_registers(processor)->gpr + RS)
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1:RS:RS_BITMASK:unsigned32:(1 << RS)
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2:RB:RB::
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1:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB)
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1:RB:RB_BITMASK:unsigned32:(1 << RB)
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2:FRA:FRA::
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1:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA)
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1:FRA:FRA_BITMASK:unsigned32:(1 << FRA)
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2:FRB:FRB::
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1:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB)
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1:FRB:FRB_BITMASK:unsigned32:(1 << FRB)
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2:FRC:FRC::
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1:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC)
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1:FRC:FRC_BITMASK:unsigned32:(1 << FRC)
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2:FRS:FRS::
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1:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS)
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1:FRS:FRS_BITMASK:unsigned32:(1 << FRS)
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2:FRT:FRT::
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1:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT)
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1:FRT:FRT_BITMASK:unsigned32:(1 << FRT)
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1:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction)
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2:BI:BI::
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1:BI:BIT32_BI::BIT32(BI)
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1:BF:BF::
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1:BF:BF_BITMASK:unsigned32:(1 << BF)
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2:BA:BA::
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1:BA:BIT32_BA::BIT32(BA)
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1:BA:BA_BITMASK:unsigned32:(1 << BA)
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2:BB:BB::
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1:BB:BIT32_BB::BIT32(BB)
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1:BB:BB_BITMASK:unsigned32:(1 << BB)
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1:BT:BT::
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1:BT:BT_BITMASK:unsigned32:(1 << BT)
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1:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3)
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#1:BD:CIA_plus_EXTS_BD_0b00:unsigned_word:CIA + EXTS(BD_0b00)
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1:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
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1:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction))
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1:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3)
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