1105 lines
28 KiB
C
1105 lines
28 KiB
C
#include <signal.h>
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#include "sysdep.h"
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#include "bfd.h"
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#include "callback.h"
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#include "remote-sim.h"
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#include "d10v_sim.h"
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#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
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#define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
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#define UMEM_SIZE 17 /* Each unified memory segment is 17 bits */
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#define UMEM_SEGMENTS 128 /* Number of segments in unified memory region */
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enum _leftright { LEFT_FIRST, RIGHT_FIRST };
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static char *myname;
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static SIM_OPEN_KIND sim_kind;
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int d10v_debug;
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host_callback *d10v_callback;
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unsigned long ins_type_counters[ (int)INS_MAX ];
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uint16 OP[4];
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static int init_text_p = 0;
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/* non-zero if we opened prog_bfd */
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static int prog_bfd_was_opened_p;
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bfd *prog_bfd;
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asection *text;
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bfd_vma text_start;
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bfd_vma text_end;
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static long hash PARAMS ((long insn, int format));
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static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
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static void get_operands PARAMS ((struct simops *s, uint32 ins));
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static void do_long PARAMS ((uint32 ins));
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static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
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static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
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static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
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extern void sim_set_profile PARAMS ((int n));
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extern void sim_set_profile_size PARAMS ((int n));
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#ifdef NEED_UI_LOOP_HOOK
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/* How often to run the ui_loop update, when in use */
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#define UI_LOOP_POLL_INTERVAL 0x14000
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/* Counter for the ui_loop_hook update */
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static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
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/* Actual hook to call to run through gdb's gui event loop */
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extern int (*ui_loop_hook) PARAMS ((int signo));
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#endif /* NEED_UI_LOOP_HOOK */
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#ifndef INLINE
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#if defined(__GNUC__) && defined(__OPTIMIZE__)
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#define INLINE __inline__
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#else
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#define INLINE
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#endif
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#endif
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#define MAX_HASH 63
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struct hash_entry
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{
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struct hash_entry *next;
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uint32 opcode;
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uint32 mask;
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int size;
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struct simops *ops;
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};
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struct hash_entry hash_table[MAX_HASH+1];
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INLINE static long
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hash(insn, format)
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long insn;
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int format;
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{
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if (format & LONG_OPCODE)
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return ((insn & 0x3F000000) >> 24);
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else
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return((insn & 0x7E00) >> 9);
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}
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INLINE static struct hash_entry *
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lookup_hash (ins, size)
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uint32 ins;
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int size;
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{
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struct hash_entry *h;
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if (size)
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h = &hash_table[(ins & 0x3F000000) >> 24];
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else
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h = &hash_table[(ins & 0x7E00) >> 9];
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while ((ins & h->mask) != h->opcode || h->size != size)
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{
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if (h->next == NULL)
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
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exit (1);
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}
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h = h->next;
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}
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return (h);
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}
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INLINE static void
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get_operands (struct simops *s, uint32 ins)
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{
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int i, shift, bits, flags;
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uint32 mask;
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for (i=0; i < s->numops; i++)
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{
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shift = s->operands[3*i];
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bits = s->operands[3*i+1];
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flags = s->operands[3*i+2];
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mask = 0x7FFFFFFF >> (31 - bits);
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OP[i] = (ins >> shift) & mask;
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}
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/* FIXME: for tracing, update values that need to be updated each
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instruction decode cycle */
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State.trace.psw = PSW;
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}
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bfd_vma
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decode_pc ()
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{
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asection *s;
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if (!init_text_p && prog_bfd != NULL)
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{
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init_text_p = 1;
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for (s = prog_bfd->sections; s; s = s->next)
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if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
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{
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text = s;
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text_start = bfd_get_section_vma (prog_bfd, s);
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text_end = text_start + bfd_section_size (prog_bfd, s);
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break;
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}
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}
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return (PC << 2) + text_start;
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}
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static void
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do_long (ins)
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uint32 ins;
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{
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struct hash_entry *h;
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
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#endif
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h = lookup_hash (ins, 1);
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get_operands (h->ops, ins);
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State.ins_type = INS_LONG;
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ins_type_counters[ (int)State.ins_type ]++;
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(h->ops->func)();
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}
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static void
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do_2_short (ins1, ins2, leftright)
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uint16 ins1, ins2;
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enum _leftright leftright;
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{
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struct hash_entry *h;
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enum _ins_type first, second;
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
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ins1, (leftright) ? "left" : "right", ins2);
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#endif
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if (leftright == LEFT_FIRST)
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{
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first = INS_LEFT;
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second = INS_RIGHT;
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ins_type_counters[ (int)INS_LEFTRIGHT ]++;
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}
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else
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{
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first = INS_RIGHT;
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second = INS_LEFT;
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ins_type_counters[ (int)INS_RIGHTLEFT ]++;
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}
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/* Issue the first instruction */
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h = lookup_hash (ins1, 0);
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get_operands (h->ops, ins1);
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State.ins_type = first;
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ins_type_counters[ (int)State.ins_type ]++;
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(h->ops->func)();
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/* Issue the second instruction (if the PC hasn't changed) */
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if (!State.pc_changed && !State.exception)
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{
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/* finish any existing instructions */
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SLOT_FLUSH ();
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h = lookup_hash (ins2, 0);
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get_operands (h->ops, ins2);
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State.ins_type = second;
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ins_type_counters[ (int)State.ins_type ]++;
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ins_type_counters[ (int)INS_CYCLES ]++;
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(h->ops->func)();
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}
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else if (!State.exception)
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ins_type_counters[ (int)INS_COND_JUMP ]++;
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}
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static void
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do_parallel (ins1, ins2)
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uint16 ins1, ins2;
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{
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struct hash_entry *h1, *h2;
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
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#endif
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ins_type_counters[ (int)INS_PARALLEL ]++;
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h1 = lookup_hash (ins1, 0);
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h2 = lookup_hash (ins2, 0);
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if (h1->ops->exec_type == PARONLY)
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT_COND_TEST;
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ins_type_counters[ (int)State.ins_type ]++;
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(h1->ops->func)();
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if (State.exe)
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{
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ins_type_counters[ (int)INS_COND_TRUE ]++;
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT_COND_EXE;
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ins_type_counters[ (int)State.ins_type ]++;
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(h2->ops->func)();
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}
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else
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ins_type_counters[ (int)INS_COND_FALSE ]++;
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}
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else if (h2->ops->exec_type == PARONLY)
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{
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT_COND_TEST;
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ins_type_counters[ (int)State.ins_type ]++;
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(h2->ops->func)();
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if (State.exe)
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{
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ins_type_counters[ (int)INS_COND_TRUE ]++;
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT_COND_EXE;
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ins_type_counters[ (int)State.ins_type ]++;
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(h1->ops->func)();
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}
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else
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ins_type_counters[ (int)INS_COND_FALSE ]++;
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}
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else
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT_PARALLEL;
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ins_type_counters[ (int)State.ins_type ]++;
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(h1->ops->func)();
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if (!State.exception)
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{
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT_PARALLEL;
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ins_type_counters[ (int)State.ins_type ]++;
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(h2->ops->func)();
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}
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}
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}
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static char *
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add_commas(buf, sizeof_buf, value)
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char *buf;
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int sizeof_buf;
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unsigned long value;
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{
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int comma = 3;
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char *endbuf = buf + sizeof_buf - 1;
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*--endbuf = '\0';
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do {
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if (comma-- == 0)
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{
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*--endbuf = ',';
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comma = 2;
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}
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*--endbuf = (value % 10) + '0';
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} while ((value /= 10) != 0);
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return endbuf;
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}
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void
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sim_size (power)
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int power;
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{
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int i;
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if (State.imem)
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{
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for (i=0;i<UMEM_SEGMENTS;i++)
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{
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if (State.umem[i])
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{
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free (State.umem[i]);
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State.umem[i] = NULL;
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}
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}
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free (State.imem);
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free (State.dmem);
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}
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State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
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State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
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for (i=1;i<(UMEM_SEGMENTS-1);i++)
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State.umem[i] = NULL;
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State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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State.umem[UMEM_SEGMENTS-1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[UMEM_SEGMENTS-1] )
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
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exit(1);
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}
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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char buffer[20];
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(*d10v_callback->printf_filtered) (d10v_callback,
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"Allocated %s bytes instruction memory and\n",
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add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
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(*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
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add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
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}
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#endif
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}
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/* Transfer data to/from simulated memory. Since a bug in either the
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simulated program or in gdb or the simulator itself may cause a
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bogus address to be passed in, we need to do some sanity checking
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on addresses to make sure they are within bounds. When an address
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fails the bounds check, treat it as a zero length read/write rather
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than aborting the entire run. */
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static int
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xfer_mem (SIM_ADDR addr,
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unsigned char *buffer,
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int size,
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int write_p)
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{
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unsigned char *memory;
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int segment = ((addr >> 24) & 0xff);
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addr = (addr & 0x00ffffff);
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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{
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if (write_p)
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%02x:%06x\n", size, segment, addr);
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}
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else
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%2x:%6x\n", size, segment, addr);
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}
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}
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#endif
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/* to access data, we use the following mapping
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0x00xxxxxx: Logical data address segment (DMAP translated memory)
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0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
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0x10xxxxxx: Physical data memory segment (On-chip data memory)
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0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
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0x12xxxxxx: Phisical unified memory segment (Unified memory)
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*/
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switch (segment)
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{
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case 0x00: /* DMAP translated memory */
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{
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int byte;
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for (byte = 0; byte < size; byte++)
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{
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uint8 *mem = dmem_addr (addr + byte);
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if (mem == NULL)
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return byte;
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else if (write_p)
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*mem = buffer[byte];
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else
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buffer[byte] = *mem;
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}
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return byte;
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}
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case 0x01: /* IMAP translated memory */
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{
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int byte;
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for (byte = 0; byte < size; byte++)
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{
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uint8 *mem = imem_addr (addr + byte);
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if (mem == NULL)
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return byte;
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else if (write_p)
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*mem = buffer[byte];
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else
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buffer[byte] = *mem;
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}
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return byte;
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}
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case 0x10: /* On-chip data memory */
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{
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addr &= ((1 << DMEM_SIZE) - 1);
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if ((addr + size) > (1 << DMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << DMEM_SIZE) - 1);
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return (0);
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}
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memory = State.dmem + addr;
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break;
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}
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case 0x11: /* On-chip insn memory */
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{
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addr &= ((1 << IMEM_SIZE) - 1);
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if ((addr + size) > (1 << IMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << IMEM_SIZE) - 1);
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return (0);
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}
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memory = State.imem + addr;
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break;
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}
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case 0x12: /* Unified memory */
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{
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int startsegment, startoffset; /* Segment and offset within segment where xfer starts */
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int endsegment, endoffset; /* Segment and offset within segment where xfer ends */
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startsegment = addr >> UMEM_SIZE;
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startoffset = addr & ((1 << UMEM_SIZE) - 1);
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endsegment = (addr + size) >> UMEM_SIZE;
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endoffset = (addr + size) & ((1 << UMEM_SIZE) - 1);
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/* FIXME: We do not currently implement xfers across segments,
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so detect this case and fail gracefully. */
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if ((startsegment != endsegment) && !((endsegment == (startsegment + 1)) && endoffset == 0))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
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return (0);
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}
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if (!State.umem[startsegment])
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{
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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(*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
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add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), startsegment);
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}
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#endif
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State.umem[startsegment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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}
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if (!State.umem[startsegment])
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE);
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return (0);
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}
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memory = State.umem[startsegment] + startoffset;
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break;
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}
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default:
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%lx is not in valid range\n", (long) addr);
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(*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
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return (0);
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}
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}
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|
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if (write_p)
|
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{
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memcpy (memory, buffer, size);
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}
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else
|
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{
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memcpy (buffer, memory, size);
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}
|
|
|
|
return size;
|
|
}
|
|
|
|
|
|
int
|
|
sim_write (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
unsigned char *buffer;
|
|
int size;
|
|
{
|
|
/* FIXME: this should be performing a virtual transfer */
|
|
return xfer_mem( addr, buffer, size, 1);
|
|
}
|
|
|
|
int
|
|
sim_read (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
unsigned char *buffer;
|
|
int size;
|
|
{
|
|
/* FIXME: this should be performing a virtual transfer */
|
|
return xfer_mem( addr, buffer, size, 0);
|
|
}
|
|
|
|
|
|
SIM_DESC
|
|
sim_open (kind, callback, abfd, argv)
|
|
SIM_OPEN_KIND kind;
|
|
host_callback *callback;
|
|
struct _bfd *abfd;
|
|
char **argv;
|
|
{
|
|
struct simops *s;
|
|
struct hash_entry *h;
|
|
static int init_p = 0;
|
|
char **p;
|
|
|
|
sim_kind = kind;
|
|
d10v_callback = callback;
|
|
myname = argv[0];
|
|
|
|
for (p = argv + 1; *p; ++p)
|
|
{
|
|
#ifdef DEBUG
|
|
if (strcmp (*p, "-t") == 0)
|
|
d10v_debug = DEBUG;
|
|
else
|
|
#endif
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p);
|
|
}
|
|
|
|
/* put all the opcodes in the hash table */
|
|
if (!init_p++)
|
|
{
|
|
for (s = Simops; s->func; s++)
|
|
{
|
|
h = &hash_table[hash(s->opcode,s->format)];
|
|
|
|
/* go to the last entry in the chain */
|
|
while (h->next)
|
|
h = h->next;
|
|
|
|
if (h->ops)
|
|
{
|
|
h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
|
|
if (!h->next)
|
|
perror ("malloc failure");
|
|
|
|
h = h->next;
|
|
}
|
|
h->ops = s;
|
|
h->mask = s->mask;
|
|
h->opcode = s->opcode;
|
|
h->size = s->is_long;
|
|
}
|
|
}
|
|
|
|
/* reset the processor state */
|
|
if (!State.imem)
|
|
sim_size(1);
|
|
sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
|
|
|
|
/* Fudge our descriptor. */
|
|
return (SIM_DESC) 1;
|
|
}
|
|
|
|
|
|
void
|
|
sim_close (sd, quitting)
|
|
SIM_DESC sd;
|
|
int quitting;
|
|
{
|
|
if (prog_bfd != NULL && prog_bfd_was_opened_p)
|
|
{
|
|
bfd_close (prog_bfd);
|
|
prog_bfd = NULL;
|
|
prog_bfd_was_opened_p = 0;
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_set_profile (n)
|
|
int n;
|
|
{
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
|
|
}
|
|
|
|
void
|
|
sim_set_profile_size (n)
|
|
int n;
|
|
{
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
|
|
}
|
|
|
|
|
|
uint8 *
|
|
dmem_addr( addr )
|
|
uint32 addr;
|
|
{
|
|
int seg;
|
|
|
|
addr &= 0xffff;
|
|
|
|
if (addr > 0xbfff)
|
|
{
|
|
if ( (addr & 0xfff0) != 0xff00)
|
|
{
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
|
|
(long)addr, (long)decode_pc ());
|
|
State.exception = SIGBUS;
|
|
}
|
|
|
|
return State.dmem + addr;
|
|
}
|
|
|
|
if (addr > 0x7fff)
|
|
{
|
|
if (DMAP & 0x1000)
|
|
{
|
|
/* instruction memory */
|
|
return (DMAP & 0xf) * 0x4000 + State.imem + (addr - 0x8000);
|
|
}
|
|
else
|
|
{
|
|
/* unified memory */
|
|
/* this is ugly because we allocate unified memory in 128K segments and */
|
|
/* dmap addresses 16k segments */
|
|
seg = (DMAP & 0x3ff) >> 3;
|
|
if (State.umem[seg] == NULL)
|
|
{
|
|
#ifdef DEBUG
|
|
(*d10v_callback->printf_filtered) (d10v_callback,"Allocating %d bytes unified memory to region %d\n", 1<<UMEM_SIZE, seg);
|
|
#endif
|
|
State.umem[seg] = (uint8 *)calloc(1,1<<UMEM_SIZE);
|
|
if (!State.umem[seg])
|
|
{
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"ERROR: alloc failed. unified memory region %d unmapped, pc = 0x%lx\n",
|
|
seg, (long)decode_pc ());
|
|
State.exception = SIGBUS;
|
|
}
|
|
}
|
|
return State.umem[seg] + (DMAP & 7) * 0x4000 + (addr - 0x8000);
|
|
}
|
|
}
|
|
return State.dmem + addr;
|
|
}
|
|
|
|
|
|
uint8 *
|
|
imem_addr (uint32 pc)
|
|
{
|
|
uint16 imap;
|
|
|
|
if (pc & 0x20000)
|
|
imap = IMAP1;
|
|
else
|
|
imap = IMAP0;
|
|
|
|
if (imap & 0x1000)
|
|
return State.imem + pc;
|
|
|
|
if (State.umem[imap & 0xff] == NULL)
|
|
return 0;
|
|
|
|
/* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
|
|
pc &= (1 << UMEM_SIZE) - 1;
|
|
|
|
return State.umem[imap & 0xff] + pc;
|
|
}
|
|
|
|
|
|
static int stop_simulator = 0;
|
|
|
|
int
|
|
sim_stop (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
stop_simulator = 1;
|
|
return 1;
|
|
}
|
|
|
|
|
|
/* Run (or resume) the program. */
|
|
void
|
|
sim_resume (sd, step, siggnal)
|
|
SIM_DESC sd;
|
|
int step, siggnal;
|
|
{
|
|
uint32 inst;
|
|
uint8 *iaddr;
|
|
|
|
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
|
|
State.exception = 0;
|
|
if (step)
|
|
sim_stop (sd);
|
|
|
|
do
|
|
{
|
|
iaddr = imem_addr ((uint32)PC << 2);
|
|
if (iaddr == NULL)
|
|
{
|
|
State.exception = SIGBUS;
|
|
break;
|
|
}
|
|
|
|
inst = get_longword( iaddr );
|
|
|
|
State.pc_changed = 0;
|
|
ins_type_counters[ (int)INS_CYCLES ]++;
|
|
|
|
switch (inst & 0xC0000000)
|
|
{
|
|
case 0xC0000000:
|
|
/* long instruction */
|
|
do_long (inst & 0x3FFFFFFF);
|
|
break;
|
|
case 0x80000000:
|
|
/* R -> L */
|
|
do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
|
|
break;
|
|
case 0x40000000:
|
|
/* L -> R */
|
|
do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
|
|
break;
|
|
case 0:
|
|
do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
|
|
break;
|
|
}
|
|
|
|
/* If the PC of the current instruction matches RPT_E then
|
|
schedule a branch to the loop start. If one of those
|
|
instructions happens to be a branch, than that instruction
|
|
will be ignored */
|
|
if (!State.pc_changed)
|
|
{
|
|
if (PSW_RP && PC == RPT_E)
|
|
{
|
|
/* Note: The behavour of a branch instruction at RPT_E
|
|
is implementation dependant, this simulator takes the
|
|
branch. Branching to RPT_E is valid, the instruction
|
|
must be executed before the loop is taken. */
|
|
if (RPT_C == 1)
|
|
{
|
|
SET_PSW_RP (0);
|
|
SET_RPT_C (0);
|
|
SET_PC (PC + 1);
|
|
}
|
|
else
|
|
{
|
|
SET_RPT_C (RPT_C - 1);
|
|
SET_PC (RPT_S);
|
|
}
|
|
}
|
|
else
|
|
SET_PC (PC + 1);
|
|
}
|
|
|
|
/* Check for a breakpoint trap on this instruction. This
|
|
overrides any pending branches or loops */
|
|
if (PSW_DB && PC == IBA)
|
|
{
|
|
SET_BPC (PC);
|
|
SET_BPSW (PSW);
|
|
SET_PSW (PSW & PSW_SM_BIT);
|
|
SET_PC (SDBT_VECTOR_START);
|
|
}
|
|
|
|
/* Writeback all the DATA / PC changes */
|
|
SLOT_FLUSH ();
|
|
|
|
#ifdef NEED_UI_LOOP_HOOK
|
|
if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
|
|
{
|
|
ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
|
|
ui_loop_hook (0);
|
|
}
|
|
#endif /* NEED_UI_LOOP_HOOK */
|
|
}
|
|
while ( !State.exception && !stop_simulator);
|
|
|
|
if (step && !State.exception)
|
|
State.exception = SIGTRAP;
|
|
}
|
|
|
|
int
|
|
sim_trace (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
#ifdef DEBUG
|
|
d10v_debug = DEBUG;
|
|
#endif
|
|
sim_resume (sd, 0, 0);
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
sim_info (sd, verbose)
|
|
SIM_DESC sd;
|
|
int verbose;
|
|
{
|
|
char buf1[40];
|
|
char buf2[40];
|
|
char buf3[40];
|
|
char buf4[40];
|
|
char buf5[40];
|
|
unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
|
|
unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
|
|
unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
|
|
unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
|
|
unsigned long left_total = left + left_parallel + left_cond + left_nops;
|
|
|
|
unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
|
|
unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
|
|
unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
|
|
unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
|
|
unsigned long right_total = right + right_parallel + right_cond + right_nops;
|
|
|
|
unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
|
|
unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
|
|
unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
|
|
unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
|
|
unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
|
|
unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
|
|
unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
|
|
unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
|
|
unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
|
|
unsigned long total = (unknown + left_total + right_total + ins_long);
|
|
|
|
int size = strlen (add_commas (buf1, sizeof (buf1), total));
|
|
int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
|
|
(left_parallel > right_parallel) ? left_parallel : right_parallel));
|
|
int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
|
|
int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
|
|
int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
|
|
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
|
|
size, add_commas (buf1, sizeof (buf1), left_total),
|
|
normal_size, add_commas (buf2, sizeof (buf2), left),
|
|
parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
|
|
cond_size, add_commas (buf4, sizeof (buf4), left_cond),
|
|
nop_size, add_commas (buf5, sizeof (buf5), left_nops));
|
|
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
|
|
size, add_commas (buf1, sizeof (buf1), right_total),
|
|
normal_size, add_commas (buf2, sizeof (buf2), right),
|
|
parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
|
|
cond_size, add_commas (buf4, sizeof (buf4), right_cond),
|
|
nop_size, add_commas (buf5, sizeof (buf5), right_nops));
|
|
|
|
if (ins_long)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s long instruction(s)\n",
|
|
size, add_commas (buf1, sizeof (buf1), ins_long));
|
|
|
|
if (parallel)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s parallel instruction(s)\n",
|
|
size, add_commas (buf1, sizeof (buf1), parallel));
|
|
|
|
if (leftright)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s instruction(s) encoded L->R\n",
|
|
size, add_commas (buf1, sizeof (buf1), leftright));
|
|
|
|
if (rightleft)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s instruction(s) encoded R->L\n",
|
|
size, add_commas (buf1, sizeof (buf1), rightleft));
|
|
|
|
if (unknown)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s unknown instruction(s)\n",
|
|
size, add_commas (buf1, sizeof (buf1), unknown));
|
|
|
|
if (cond_true)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s instruction(s) due to EXExxx condition being true\n",
|
|
size, add_commas (buf1, sizeof (buf1), cond_true));
|
|
|
|
if (cond_false)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"skipped %*s instruction(s) due to EXExxx condition being false\n",
|
|
size, add_commas (buf1, sizeof (buf1), cond_false));
|
|
|
|
if (cond_jump)
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"skipped %*s instruction(s) due to conditional branch succeeding\n",
|
|
size, add_commas (buf1, sizeof (buf1), cond_jump));
|
|
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s cycle(s)\n",
|
|
size, add_commas (buf1, sizeof (buf1), cycles));
|
|
|
|
(*d10v_callback->printf_filtered) (d10v_callback,
|
|
"executed %*s total instructions\n",
|
|
size, add_commas (buf1, sizeof (buf1), total));
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (sd, abfd, argv, env)
|
|
SIM_DESC sd;
|
|
struct _bfd *abfd;
|
|
char **argv;
|
|
char **env;
|
|
{
|
|
bfd_vma start_address;
|
|
|
|
/* reset all state information */
|
|
memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
|
|
|
|
if (argv)
|
|
{
|
|
/* a hack to set r0/r1 with argc/argv */
|
|
/* some high memory that won't be overwritten by the stack soon */
|
|
bfd_vma addr = 0x7C00;
|
|
int p = 20;
|
|
int i = 0;
|
|
while (argv[i])
|
|
{
|
|
int size = strlen (argv[i]) + 1;
|
|
SW (addr + 2*i, addr + p);
|
|
sim_write (sd, addr + 0, argv[i], size);
|
|
p += size;
|
|
i++;
|
|
}
|
|
SET_GPR (0, addr);
|
|
SET_GPR (1, i);
|
|
}
|
|
|
|
/* set PC */
|
|
if (abfd != NULL)
|
|
start_address = bfd_get_start_address (abfd);
|
|
else
|
|
start_address = 0xffc0 << 2;
|
|
#ifdef DEBUG
|
|
if (d10v_debug)
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
|
|
#endif
|
|
SET_CREG (PC_CR, start_address >> 2);
|
|
|
|
/* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
|
|
/* resets imap0 and imap1 to 0x1000. */
|
|
if (1)
|
|
{
|
|
SET_IMAP0 (0x0000);
|
|
SET_IMAP1 (0x007f);
|
|
SET_DMAP (0x0000);
|
|
}
|
|
else
|
|
{
|
|
SET_IMAP0 (0x1000);
|
|
SET_IMAP1 (0x1000);
|
|
SET_DMAP(0);
|
|
}
|
|
|
|
SLOT_FLUSH ();
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
|
|
void
|
|
sim_set_callbacks (p)
|
|
host_callback *p;
|
|
{
|
|
d10v_callback = p;
|
|
}
|
|
|
|
void
|
|
sim_stop_reason (sd, reason, sigrc)
|
|
SIM_DESC sd;
|
|
enum sim_stop *reason;
|
|
int *sigrc;
|
|
{
|
|
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
|
|
|
|
switch (State.exception)
|
|
{
|
|
case SIG_D10V_STOP: /* stop instruction */
|
|
*reason = sim_exited;
|
|
*sigrc = 0;
|
|
break;
|
|
|
|
case SIG_D10V_EXIT: /* exit trap */
|
|
*reason = sim_exited;
|
|
*sigrc = GPR (0);
|
|
break;
|
|
|
|
default: /* some signal */
|
|
*reason = sim_stopped;
|
|
if (stop_simulator && !State.exception)
|
|
*sigrc = SIGINT;
|
|
else
|
|
*sigrc = State.exception;
|
|
break;
|
|
}
|
|
|
|
stop_simulator = 0;
|
|
}
|
|
|
|
int
|
|
sim_fetch_register (sd, rn, memory, length)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
int length;
|
|
{
|
|
if (rn > 34)
|
|
WRITE_64 (memory, ACC (rn-35));
|
|
else if (rn == 32)
|
|
WRITE_16 (memory, IMAP0);
|
|
else if (rn == 33)
|
|
WRITE_16 (memory, IMAP1);
|
|
else if (rn == 34)
|
|
WRITE_16 (memory, DMAP);
|
|
else if (rn >= 16)
|
|
WRITE_16 (memory, CREG (rn - 16));
|
|
else
|
|
WRITE_16 (memory, GPR (rn));
|
|
return -1;
|
|
}
|
|
|
|
int
|
|
sim_store_register (sd, rn, memory, length)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
int length;
|
|
{
|
|
if (rn > 34)
|
|
SET_ACC (rn-35, READ_64 (memory) & MASK40);
|
|
else if (rn == 34)
|
|
SET_DMAP( READ_16(memory) );
|
|
else if (rn == 33)
|
|
SET_IMAP1( READ_16(memory) );
|
|
else if (rn == 32)
|
|
SET_IMAP0( READ_16(memory) );
|
|
else if (rn >= 16)
|
|
SET_CREG (rn - 16, READ_16 (memory));
|
|
else
|
|
SET_GPR (rn, READ_16 (memory));
|
|
SLOT_FLUSH ();
|
|
return -1;
|
|
}
|
|
|
|
|
|
void
|
|
sim_do_command (sd, cmd)
|
|
SIM_DESC sd;
|
|
char *cmd;
|
|
{
|
|
(*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
|
|
}
|
|
|
|
SIM_RC
|
|
sim_load (sd, prog, abfd, from_tty)
|
|
SIM_DESC sd;
|
|
char *prog;
|
|
bfd *abfd;
|
|
int from_tty;
|
|
{
|
|
extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
|
|
|
|
if (prog_bfd != NULL && prog_bfd_was_opened_p)
|
|
{
|
|
bfd_close (prog_bfd);
|
|
prog_bfd_was_opened_p = 0;
|
|
}
|
|
prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd,
|
|
sim_kind == SIM_OPEN_DEBUG,
|
|
1/*LMA*/, sim_write);
|
|
if (prog_bfd == NULL)
|
|
return SIM_RC_FAIL;
|
|
prog_bfd_was_opened_p = abfd == NULL;
|
|
return SIM_RC_OK;
|
|
}
|