622 lines
17 KiB
C
622 lines
17 KiB
C
/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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#include "dv-sockser.h"
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#include "sim-assert.h"
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/* DEVICE
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tx3904sio - tx3904 serial I/O
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DESCRIPTION
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Implements one tx3904 serial I/O controller described in the tx3904
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user guide. Three instances are required for SIO0 and SIO1 within
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the tx3904, at different base addresses.
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Both internal and system clocks are synthesized as divided versions
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of the simulator clock.
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There is no support for:
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- CTS/RTS flow control
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- baud rate emulation - use infinite speed instead
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- general frame format - use 8N1
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- multi-controller system
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- DMA - use interrupt-driven or polled-I/O instead
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PROPERTIES
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reg <base> <length>
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Base of SIO control register bank. <length> must equal 0x100.
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Register offsets: 0: SLCR: line control register
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4: SLSR: line status register
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8: SDICR: DMA/interrupt control register
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12: SDISR: DMA/interrupt status register
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16: SFCR: FIFO control register
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20: SBGR: baud rate control register
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32: transfer FIFO buffer
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48: transfer FIFO buffer
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backend {tcp | stdio}
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Use dv-sockser TCP-port backend or stdio for backend. Default: stdio.
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PORTS
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int (output)
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Interrupt port. An event is generated when a timer interrupt
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occurs.
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reset (input)
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Reset port.
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*/
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/* static functions */
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struct tx3904sio_fifo;
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static void tx3904sio_tickle(struct hw*);
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static int tx3904sio_fifo_nonempty(struct hw*, struct tx3904sio_fifo*);
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static char tx3904sio_fifo_pop(struct hw*, struct tx3904sio_fifo*);
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static void tx3904sio_fifo_push(struct hw*, struct tx3904sio_fifo*, char);
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static void tx3904sio_fifo_reset(struct hw*, struct tx3904sio_fifo*);
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static void tx3904sio_poll(struct hw*, void* data);
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/* register numbers; each is one word long */
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enum
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{
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SLCR_REG = 0,
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SLSR_REG = 1,
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SDICR_REG = 2,
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SDISR_REG = 3,
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SFCR_REG = 4,
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SBGR_REG = 5,
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TFIFO_REG = 8,
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SFIFO_REG = 12,
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};
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/* port ID's */
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enum
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{
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RESET_PORT,
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INT_PORT,
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};
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static const struct hw_port_descriptor tx3904sio_ports[] =
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{
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{ "int", INT_PORT, 0, output_port, },
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{ "reset", RESET_PORT, 0, input_port, },
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{ NULL, },
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};
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/* Generic FIFO */
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struct tx3904sio_fifo
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{
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int size, used;
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unsigned_1 *buffer;
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};
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/* The timer/counter register internal state. Note that we store
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state using the control register images, in host endian order. */
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struct tx3904sio
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{
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address_word base_address; /* control register base */
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enum {sio_tcp, sio_stdio} backend; /* backend */
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struct tx3904sio_fifo rx_fifo, tx_fifo; /* FIFOs */
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unsigned_4 slcr;
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#define SLCR_WR_MASK 0xe17f0000U
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#define SLCR_SET_BYTE(c,o,b) ((c)->slcr = SLCR_WR_MASK & (((c)->slcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
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unsigned_4 slsr;
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#define SLSR_WR_MASK 0x00000000 /* UFER/UPER/UOER unimplemented */
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unsigned_4 sdicr;
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#define SDICR_WR_MASK 0x000f0000U
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#define SDICR_SET_BYTE(c,o,b) ((c)->sdicr = SDICR_WR_MASK & (((c)->sdicr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
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#define SDICR_GET_SDMAE(c) ((c)->sdicr & 0x00080000)
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#define SDICR_GET_ERIE(c) ((c)->sdicr & 0x00040000)
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#define SDICR_GET_TDIE(c) ((c)->sdicr & 0x00020000)
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#define SDICR_GET_RDIE(c) ((c)->sdicr & 0x00010000)
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unsigned_4 sdisr;
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#define SDISR_WR_MASK 0x00070000U
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#define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
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#define SDISR_GET_TDIS(c) ((c)->sdisr & 0x00020000)
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#define SDISR_SET_TDIS(c) ((c)->sdisr |= 0x00020000)
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#define SDISR_GET_RDIS(c) ((c)->sdisr & 0x00010000)
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#define SDISR_SET_RDIS(c) ((c)->sdisr |= 0x00010000)
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unsigned_4 sfcr;
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#define SFCR_WR_MASK 0x001f0000U
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#define SFCR_SET_BYTE(c,o,b) ((c)->sfcr = SFCR_WR_MASK & (((c)->sfcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
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#define SFCR_GET_TFRST(c) ((c)->sfcr & 0x00040000)
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#define SFCR_GET_RFRST(c) ((c)->sfcr & 0x00020000)
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#define SFCR_GET_FRSTE(c) ((c)->sfcr & 0x00010000)
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unsigned_4 sbgr;
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#define SBGR_WR_MASK 0x03ff0000U
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#define SBGR_SET_BYTE(c,o,b) ((c)->sbgr = SBGR_WR_MASK & (((c)->sbgr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
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/* Periodic I/O polling */
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struct hw_event* poll_event;
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method tx3904sio_io_read_buffer;
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static hw_io_write_buffer_method tx3904sio_io_write_buffer;
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static hw_port_event_method tx3904sio_port_event;
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static void
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attach_tx3904sio_regs (struct hw *me,
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struct tx3904sio *controller)
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{
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unsigned_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain one addr/size entry");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space,
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&attach_address,
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me);
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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&attach_size, me);
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hw_attach_address (hw_parent (me), 0,
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attach_space, attach_address, attach_size,
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me);
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if(hw_find_property(me, "backend") != NULL)
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{
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const char* value = hw_find_string_property(me, "backend");
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if(! strcmp(value, "tcp"))
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controller->backend = sio_tcp;
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else if(! strcmp(value, "stdio"))
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controller->backend = sio_stdio;
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else
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hw_abort(me, "illegal value for backend parameter `%s': use tcp or stdio", value);
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}
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controller->base_address = attach_address;
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}
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static void
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tx3904sio_finish (struct hw *me)
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{
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struct tx3904sio *controller;
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controller = HW_ZALLOC (me, struct tx3904sio);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, tx3904sio_io_read_buffer);
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set_hw_io_write_buffer (me, tx3904sio_io_write_buffer);
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set_hw_ports (me, tx3904sio_ports);
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set_hw_port_event (me, tx3904sio_port_event);
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/* Preset defaults */
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controller->backend = sio_stdio;
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/* Attach ourself to our parent bus */
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attach_tx3904sio_regs (me, controller);
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/* Initialize to reset state */
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tx3904sio_fifo_reset(me, & controller->rx_fifo);
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tx3904sio_fifo_reset(me, & controller->tx_fifo);
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controller->slsr = controller->sdicr
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= controller->sdisr = controller->sfcr
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= controller->sbgr = 0;
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controller->slcr = 0x40000000; /* set TWUB */
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controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
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controller->poll_event = NULL;
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}
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/* An event arrives on an interrupt port */
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static void
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tx3904sio_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int level)
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{
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struct tx3904sio *controller = hw_data (me);
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switch (my_port)
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{
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case RESET_PORT:
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{
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HW_TRACE ((me, "reset"));
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tx3904sio_fifo_reset(me, & controller->rx_fifo);
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tx3904sio_fifo_reset(me, & controller->tx_fifo);
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controller->slsr = controller->sdicr
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= controller->sdisr = controller->sfcr
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= controller->sbgr = 0;
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controller->slcr = 0x40000000; /* set TWUB */
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controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
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/* Don't interfere with I/O poller. */
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break;
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}
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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}
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}
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/* generic read/write */
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static unsigned
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tx3904sio_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct tx3904sio *controller = hw_data (me);
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unsigned byte;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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/* tickle fifos */
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tx3904sio_tickle(me);
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for (byte = 0; byte < nr_bytes; byte++)
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{
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address_word address = base + byte;
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int reg_number = (address - controller->base_address) / 4;
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int reg_offset = (address - controller->base_address) % 4;
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unsigned_4 register_value; /* in target byte order */
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/* fill in entire register_value word */
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switch (reg_number)
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{
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case SLCR_REG: register_value = controller->slcr; break;
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case SLSR_REG: register_value = controller->slsr; break;
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case SDICR_REG: register_value = controller->sdicr; break;
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case SDISR_REG: register_value = controller->sdisr; break;
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case SFCR_REG: register_value = controller->sfcr; break;
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case SBGR_REG: register_value = controller->sbgr; break;
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case TFIFO_REG: register_value = 0; break;
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case SFIFO_REG:
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/* consume rx fifo for MS byte */
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if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
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register_value = (tx3904sio_fifo_pop(me, & controller->rx_fifo) << 24);
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else
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register_value = 0;
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break;
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default: register_value = 0;
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}
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/* write requested byte out */
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register_value = H2T_4(register_value);
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/* HW_TRACE ((me, "byte %d %02x", reg_offset, ((char*)& register_value)[reg_offset])); */
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memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
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}
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return nr_bytes;
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}
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static unsigned
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tx3904sio_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct tx3904sio *controller = hw_data (me);
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unsigned byte;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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for (byte = 0; byte < nr_bytes; byte++)
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{
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address_word address = base + byte;
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unsigned_1 write_byte = ((const unsigned char*) source)[byte];
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int reg_number = (address - controller->base_address) / 4;
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int reg_offset = 3 - (address - controller->base_address) % 4;
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/* HW_TRACE ((me, "byte %d %02x", reg_offset, write_byte)); */
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/* fill in entire register_value word */
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switch (reg_number)
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{
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case SLCR_REG:
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SLCR_SET_BYTE(controller, reg_offset, write_byte);
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break;
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case SLSR_REG: /* unwriteable */ break;
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case SDICR_REG:
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{
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unsigned_4 last_int, next_int;
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/* deassert interrupt upon clear */
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last_int = controller->sdisr & controller->sdicr;
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/* HW_TRACE ((me, "sdicr - sdisr %08x sdicr %08x",
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controller->sdisr, controller->sdicr)); */
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SDICR_SET_BYTE(controller, reg_offset, write_byte);
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/* HW_TRACE ((me, "sdicr + sdisr %08x sdicr %08x",
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controller->sdisr, controller->sdicr)); */
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next_int = controller->sdisr & controller->sdicr;
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if(SDICR_GET_SDMAE(controller))
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hw_abort(me, "Cannot support DMA-driven sio.");
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if(~last_int & next_int) /* any bits set? */
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hw_port_event(me, INT_PORT, 1);
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if(last_int & ~next_int) /* any bits cleared? */
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hw_port_event(me, INT_PORT, 0);
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}
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break;
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case SDISR_REG:
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{
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unsigned_4 last_int, next_int;
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/* deassert interrupt upon clear */
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last_int = controller->sdisr & controller->sdicr;
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/* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x",
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controller->sdisr, controller->sdicr)); */
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SDISR_SET_BYTE(controller, reg_offset, write_byte);
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/* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x",
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controller->sdisr, controller->sdicr)); */
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next_int = controller->sdisr & controller->sdicr;
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if(~last_int & next_int) /* any bits set? */
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hw_port_event(me, INT_PORT, 1);
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if(last_int & ~next_int) /* any bits cleared? */
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hw_port_event(me, INT_PORT, 0);
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}
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break;
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case SFCR_REG:
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SFCR_SET_BYTE(controller, reg_offset, write_byte);
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if(SFCR_GET_FRSTE(controller))
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{
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if(SFCR_GET_TFRST(controller)) tx3904sio_fifo_reset(me, & controller->tx_fifo);
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if(SFCR_GET_RFRST(controller)) tx3904sio_fifo_reset(me, & controller->rx_fifo);
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}
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break;
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case SBGR_REG:
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SBGR_SET_BYTE(controller, reg_offset, write_byte);
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break;
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case SFIFO_REG: /* unwriteable */ break;
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case TFIFO_REG:
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if(reg_offset == 3) /* first byte */
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tx3904sio_fifo_push(me, & controller->tx_fifo, write_byte);
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break;
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default:
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HW_TRACE ((me, "write to illegal register %d", reg_number));
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}
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} /* loop over bytes */
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/* tickle fifos */
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tx3904sio_tickle(me);
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return nr_bytes;
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}
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/* Send enqueued characters from tx_fifo and trigger TX interrupt.
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Receive characters into rx_fifo and trigger RX interrupt. */
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void
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tx3904sio_tickle(struct hw *me)
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{
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struct tx3904sio* controller = hw_data(me);
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int c;
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char cc;
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unsigned_4 last_int, next_int;
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/* HW_TRACE ((me, "tickle backend: %02x", controller->backend)); */
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switch(controller->backend)
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{
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case sio_tcp:
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while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
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{
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cc = tx3904sio_fifo_pop(me, & controller->tx_fifo);
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dv_sockser_write(hw_system(me), cc);
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HW_TRACE ((me, "tcp output: %02x", cc));
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}
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c = dv_sockser_read(hw_system(me));
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while(c != -1)
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{
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cc = (char) c;
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HW_TRACE ((me, "tcp input: %02x", cc));
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tx3904sio_fifo_push(me, & controller->rx_fifo, cc);
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c = dv_sockser_read(hw_system(me));
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}
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break;
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case sio_stdio:
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while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
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{
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cc = tx3904sio_fifo_pop(me, & controller->tx_fifo);
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sim_io_write_stdout(hw_system(me), & cc, 1);
|
|
sim_io_flush_stdout(hw_system(me));
|
|
HW_TRACE ((me, "stdio output: %02x", cc));
|
|
}
|
|
|
|
c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1);
|
|
while(c == 1)
|
|
{
|
|
HW_TRACE ((me, "stdio input: %02x", cc));
|
|
tx3904sio_fifo_push(me, & controller->rx_fifo, cc);
|
|
c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1);
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
hw_abort(me, "Illegal backend mode: %d", controller->backend);
|
|
}
|
|
|
|
/* Update RDIS / TDIS flags */
|
|
last_int = controller->sdisr & controller->sdicr;
|
|
/* HW_TRACE ((me, "tickle - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
|
|
if(tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
|
|
SDISR_SET_RDIS(controller);
|
|
if(! tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
|
|
SDISR_SET_TDIS(controller);
|
|
next_int = controller->sdisr & controller->sdicr;
|
|
/* HW_TRACE ((me, "tickle + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
|
|
|
|
if(~last_int & next_int) /* any bits set? */
|
|
hw_port_event(me, INT_PORT, 1);
|
|
if(last_int & ~next_int) /* any bits cleared? */
|
|
hw_port_event(me, INT_PORT, 0);
|
|
|
|
/* Add periodic polling for this port, if it's not already going. */
|
|
if(controller->poll_event == NULL)
|
|
{
|
|
controller->poll_event = hw_event_queue_schedule (me, 1000,
|
|
tx3904sio_poll, NULL);
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
tx3904sio_fifo_nonempty(struct hw* me, struct tx3904sio_fifo* fifo)
|
|
{
|
|
/* HW_TRACE ((me, "fifo used: %d", fifo->used)); */
|
|
return(fifo->used > 0);
|
|
}
|
|
|
|
|
|
char
|
|
tx3904sio_fifo_pop(struct hw* me, struct tx3904sio_fifo* fifo)
|
|
{
|
|
char it;
|
|
ASSERT(fifo->used > 0);
|
|
ASSERT(fifo->buffer != NULL);
|
|
it = fifo->buffer[0];
|
|
memcpy(& fifo->buffer[0], & fifo->buffer[1], fifo->used - 1);
|
|
fifo->used --;
|
|
/* HW_TRACE ((me, "pop fifo -> %02x", it)); */
|
|
return it;
|
|
}
|
|
|
|
|
|
void
|
|
tx3904sio_fifo_push(struct hw* me, struct tx3904sio_fifo* fifo, char it)
|
|
{
|
|
/* HW_TRACE ((me, "push %02x -> fifo", it)); */
|
|
if(fifo->size == fifo->used) /* full */
|
|
{
|
|
int next_size = fifo->size * 2 + 16;
|
|
char* next_buf = zalloc(next_size);
|
|
memcpy(next_buf, fifo->buffer, fifo->used);
|
|
|
|
if(fifo->buffer != NULL) zfree(fifo->buffer);
|
|
fifo->buffer = next_buf;
|
|
fifo->size = next_size;
|
|
}
|
|
|
|
fifo->buffer[fifo->used] = it;
|
|
fifo->used ++;
|
|
}
|
|
|
|
|
|
void
|
|
tx3904sio_fifo_reset(struct hw* me, struct tx3904sio_fifo* fifo)
|
|
{
|
|
/* HW_TRACE ((me, "reset fifo")); */
|
|
fifo->used = 0;
|
|
fifo->size = 0;
|
|
zfree(fifo->buffer);
|
|
fifo->buffer = 0;
|
|
}
|
|
|
|
|
|
void
|
|
tx3904sio_poll(struct hw* me, void* ignored)
|
|
{
|
|
struct tx3904sio* controller = hw_data (me);
|
|
tx3904sio_tickle (me);
|
|
hw_event_queue_deschedule (me, controller->poll_event);
|
|
controller->poll_event = hw_event_queue_schedule (me, 1000,
|
|
tx3904sio_poll, NULL);
|
|
}
|
|
|
|
|
|
|
|
const struct hw_descriptor dv_tx3904sio_descriptor[] = {
|
|
{ "tx3904sio", tx3904sio_finish, },
|
|
{ NULL },
|
|
};
|