1848e56734
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C, FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives to x86 assembler. TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_arch): Add 687. (cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. (parse_real_register): Check cpuregmmx instead of cpummx for MMX register. Check cpuregxmm instead of cpusse for XMM register. Check cpuregymm instead of cpuavx for YMM register. Check cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register. * doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. * testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx. * testsuite/gas/i386/arch-10.d (as): Likewise. * testsuite/gas/i386/arch-11.s: Add ".arch .mmx". * testsuite/gas/i386/i386.exp: Pass mmx to assembler for arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3 and noavx-4. * testsuite/gas/i386/no87-3.l: New file. * testsuite/gas/i386/no87-3.s: Likewise. * testsuite/gas/i386/noavx-3.l: Likewise. * testsuite/gas/i386/noavx-3.s: Likewise. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-4.s: Likewise. * testsuite/gas/i386/nosse-4.l: Likewise. * testsuite/gas/i386/nosse-4.s: Likewise. * testsuite/gas/i386/nosse-5.d: Likewise. * testsuite/gas/i386/nosse-5.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and CpuRegMask for AVX512. (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM and CpuRegMask. (set_bitfield_from_cpu_flag_init): New function. (set_bitfield): Remove const on f. Call set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. * i386-opc.h (CpuRegMMX): New. (CpuRegXMM): Likewise. (CpuRegYMM): Likewise. (CpuRegZMM): Likewise. (CpuRegMask): Likewise. (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm and cpuregmask. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
609 lines
19 KiB
Plaintext
609 lines
19 KiB
Plaintext
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20145
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* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
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CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
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CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
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Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
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CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
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CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
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CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
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Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
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CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
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CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
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CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
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for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
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CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
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CpuRegMask for AVX512.
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(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
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and CpuRegMask.
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(set_bitfield_from_cpu_flag_init): New function.
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(set_bitfield): Remove const on f. Call
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set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
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* i386-opc.h (CpuRegMMX): New.
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(CpuRegXMM): Likewise.
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(CpuRegYMM): Likewise.
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(CpuRegZMM): Likewise.
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(CpuRegMask): Likewise.
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(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
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and cpuregmask.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20154
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* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
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(opcode_modifiers): Add AMD64 and Intel64.
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(main): Properly verify CpuMax.
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* i386-opc.h (CpuAMD64): Removed.
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(CpuIntel64): Likewise.
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(CpuMax): Set to CpuNo64.
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(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
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(AMD64): New.
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(Intel64): Likewise.
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(i386_opcode_modifier): Add amd64 and intel64.
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(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
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on call and jmp.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20154
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* i386-gen.c (main): Fail if CpuMax is incorrect.
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* i386-opc.h (CpuMax): Set to CpuIntel64.
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* i386-tbl.h: Regenerated.
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2016-05-27 Nick Clifton <nickc@redhat.com>
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PR target/20150
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* msp430-dis.c (msp430dis_read_two_bytes): New function.
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(msp430dis_opcode_unsigned): New function.
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(msp430dis_opcode_signed): New function.
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(msp430_singleoperand): Use the new opcode reading functions.
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Only disassenmble bytes if they were successfully read.
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(msp430_doubleoperand): Likewise.
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(msp430_branchinstr): Likewise.
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(msp430x_callx_instr): Likewise.
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(print_insn_msp430): Check that it is safe to read bytes before
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attempting disassembly. Use the new opcode reading functions.
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2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (CY): New define. Document it.
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(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
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CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
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and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
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CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
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CPU_ANY_AVX_FLAGS.
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* i386-init.h: Regenerated.
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/20141
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* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
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CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
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* i386-init.h: Regenerated.
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2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
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CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
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* i386-init.h: Regenerated.
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2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
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information.
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(print_insn_arc): Set insn_type information.
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* arc-opc.c (C_CC): Add F_CLASS_COND.
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* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
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(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
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(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
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(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
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(brne, brne_s, jeq_s, jne_s): Likewise.
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2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-tbl.h (neg): New instruction variant.
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2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
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* arc-dis.c (find_format, find_format, get_auxreg)
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(print_insn_arc): Changed.
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* arc-ext.h (INSERT_XOP): Likewise.
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2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* tic54x-dis.c (sprint_mmr): Adjust.
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* tic54x-opc.c: Likewise.
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2016-05-19 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
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2016-05-19 Alan Modra <amodra@gmail.com>
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* ppc-opc.c: Formatting.
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(NSISIGNOPT): Define.
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(powerpc_opcodes <subis>): Use NSISIGNOPT.
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2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
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replacing references to `micromips_ase' throughout.
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(_print_insn_mips): Don't use file-level microMIPS annotation to
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determine the disassembly mode with the symbol table.
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2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
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mips64r6.
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* mips-opc.c (D34): New macro.
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(mips_builtin_opcodes): Define bposge32c for DSPr3.
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2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
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* i386-dis.c (prefix_table): Add RDPID instruction.
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* i386-gen.c (cpu_flag_init): Add RDPID flag.
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(cpu_flags): Add RDPID bitfield.
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* i386-opc.h (enum): Add RDPID element.
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(i386_cpu_flags): Add RDPID field.
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* i386-opc.tbl: Add RDPID instruction.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Regenerate.
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
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branch type of a symbol.
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(print_insn): Likewise.
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
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Mainline Security Extensions instructions.
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(thumb_opcodes): Add entries for narrow ARMv8-M Security
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Extensions instructions.
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(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
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instructions.
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(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
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special registers.
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2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
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2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
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(arcExtMap_genOpcode): Likewise.
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* arc-opc.c (arg_32bit_rc): Define new variable.
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(arg_32bit_u6): Likewise.
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(arg_32bit_limm): Likewise.
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2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-gen.c (VERIFIER): Define.
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* aarch64-opc.c (VERIFIER): Define.
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(verify_ldpsw): Use static linkage.
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* aarch64-opc.h (verify_ldpsw): Remove.
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* aarch64-tbl.h: Use VERIFIER for verifiers.
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2016-04-28 Nick Clifton <nickc@redhat.com>
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PR target/19722
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* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
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* aarch64-opc.c (verify_ldpsw): New function.
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* aarch64-opc.h (verify_ldpsw): New prototype.
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* aarch64-tbl.h: Add initialiser for verifier field.
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(LDPSW): Set verifier to verify_ldpsw.
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2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/19983
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PR binutils/19984
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* i386-dis.c (print_insn): Return -1 if size of bfd_vma is
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smaller than address size.
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2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* alpha-dis.c: Regenerate.
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* crx-dis.c: Likewise.
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* disassemble.c: Likewise.
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* epiphany-opc.c: Likewise.
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* fr30-opc.c: Likewise.
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* frv-opc.c: Likewise.
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* ip2k-opc.c: Likewise.
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* iq2000-opc.c: Likewise.
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* lm32-opc.c: Likewise.
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* lm32-opinst.c: Likewise.
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* m32c-opc.c: Likewise.
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* m32r-opc.c: Likewise.
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* m32r-opinst.c: Likewise.
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* mep-opc.c: Likewise.
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* mt-opc.c: Likewise.
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* or1k-opc.c: Likewise.
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* or1k-opinst.c: Likewise.
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* tic80-opc.c: Likewise.
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* xc16x-opc.c: Likewise.
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* xstormy16-opc.c: Likewise.
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
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fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
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calcsd, and calcxd instructions.
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* arc-opc.c (insert_nps_bitop_size): Delete.
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(extract_nps_bitop_size): Delete.
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(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
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(extract_nps_qcmp_m3): Define.
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(extract_nps_qcmp_m2): Define.
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(extract_nps_qcmp_m1): Define.
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(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
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(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
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(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
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NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
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NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
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NPS_QCMP_M3.
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
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2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.in: Regenerated with automake 1.11.6.
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* aclocal.m4: Likewise.
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2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
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instructions.
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* arc-opc.c (insert_nps_cmem_uimm16): New function.
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(extract_nps_cmem_uimm16): New function.
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(arc_operands): Add NPS_XLDST_UIMM16 operand.
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2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-dis.c (arc_insn_length): New function.
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(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
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(find_format): Change insnLen parameter to unsigned.
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2016-04-13 Nick Clifton <nickc@redhat.com>
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PR target/19937
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* v850-opc.c (v850_opcodes): Correct masks for long versions of
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the LD.B and LD.BU instructions.
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (find_format): Check for extension flags.
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(print_flags): New function.
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(print_insn_arc): Update for .extCondCode, .extCoreRegister and
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.extAuxRegister.
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* arc-ext.c (arcExtMap_coreRegName): Use
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LAST_EXTENSION_CORE_REGISTER.
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(arcExtMap_coreReadWrite): Likewise.
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(dump_ARC_extmap): Update printing.
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* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
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(arc_aux_regs): Add cpu field.
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* arc-regs.h: Add cpu field, lower case name aux registers.
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-tbl.h: Add rtsc, sleep with no arguments.
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2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
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Initialize.
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(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
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(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
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(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
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(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
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(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
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(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
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(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
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(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
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(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
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(arc_opcode arc_opcodes): Null terminate the array.
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(arc_num_opcodes): Remove.
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* arc-ext.h (INSERT_XOP): Define.
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(extInstruction_t): Likewise.
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(arcExtMap_instName): Delete.
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(arcExtMap_insn): New function.
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(arcExtMap_genOpcode): Likewise.
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* arc-ext.c (ExtInstruction): Remove.
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||
(create_map): Zero initialize instruction fields.
|
||
(arcExtMap_instName): Remove.
|
||
(arcExtMap_insn): New function.
|
||
(dump_ARC_extmap): More info while debuging.
|
||
(arcExtMap_genOpcode): New function.
|
||
* arc-dis.c (find_format): New function.
|
||
(print_insn_arc): Use find_format.
|
||
(arc_get_disassembler): Enable dump_ARC_extmap only when
|
||
debugging.
|
||
|
||
2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (print_mips16_insn_arg): Mask unused extended
|
||
instruction bits out.
|
||
|
||
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
|
||
* arc-opc.c (arc_flag_operands): Add new flags.
|
||
(arc_flag_classes): Add new classes.
|
||
|
||
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
|
||
|
||
2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
|
||
encode1, rflt, crc16, and crc32 instructions.
|
||
* arc-opc.c (arc_flag_operands): Add F_NPS_R.
|
||
(arc_flag_classes): Add C_NPS_R.
|
||
(insert_nps_bitop_size_2b): New function.
|
||
(extract_nps_bitop_size_2b): Likewise.
|
||
(insert_nps_bitop_uimm8): Likewise.
|
||
(extract_nps_bitop_uimm8): Likewise.
|
||
(arc_operands): Add new operand entries.
|
||
|
||
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-regs.h: Add a new subclass field. Add double assist
|
||
accumulator register values.
|
||
* arc-tbl.h: Use DPA subclass to mark the double assist
|
||
instructions. Use DPX/SPX subclas to mark the FPX instructions.
|
||
* arc-opc.c (RSP): Define instead of SP.
|
||
(arc_aux_regs): Add the subclass field.
|
||
|
||
2016-04-05 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
|
||
|
||
2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
|
||
NPS_R_SRC1.
|
||
|
||
2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-nps400-tbl.h: Add a header comment, and fix some whitespace
|
||
issues. No functional changes.
|
||
|
||
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
|
||
(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
|
||
(RTT): Remove duplicate.
|
||
(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
|
||
(PCT_CONFIG*): Remove.
|
||
(D1L, D1H, D2H, D2L): Define.
|
||
|
||
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
|
||
|
||
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-tbl.h (invld07): Remove.
|
||
* arc-ext-tbl.h: New file.
|
||
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
|
||
* arc-opc.c (arc_opcodes): Add ext-tbl include.
|
||
|
||
2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
|
||
|
||
Fix -Wstack-usage warnings.
|
||
* aarch64-dis.c (print_operands): Substitute size.
|
||
* aarch64-opc.c (print_register_offset_address): Substitute tblen.
|
||
|
||
2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||
|
||
* sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
|
||
to get a proper diagnostic when an invalid ASR register is used.
|
||
|
||
2016-03-22 Nick Clifton <nickc@redhat.com>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-nps400-tbl.h: New file.
|
||
* arc-opc.c: Add top level comment.
|
||
(insert_nps_3bit_dst): New function.
|
||
(extract_nps_3bit_dst): New function.
|
||
(insert_nps_3bit_src2): New function.
|
||
(extract_nps_3bit_src2): New function.
|
||
(insert_nps_bitop_size): New function.
|
||
(extract_nps_bitop_size): New function.
|
||
(arc_flag_operands): Add nps400 entries.
|
||
(arc_flag_classes): Add nps400 entries.
|
||
(arc_operands): Add nps400 entries.
|
||
(arc_opcodes): Add nps400 include.
|
||
|
||
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
|
||
the new class enum values.
|
||
|
||
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-dis.c (print_insn_arc): Handle nps400.
|
||
|
||
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* arc-opc.c (BASE): Delete.
|
||
|
||
2016-03-18 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR target/19721
|
||
* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
|
||
of MOV insn that aliases an ORR insn.
|
||
|
||
2016-03-16 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* arm-dis.c (neon_opcodes): Support new FP16 instructions.
|
||
|
||
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
||
|
||
* mcore-opc.h: Add const qualifiers.
|
||
* microblaze-opc.h (struct op_code_struct): Likewise.
|
||
* sh-opc.h: Likewise.
|
||
* tic4x-dis.c (tic4x_print_indirect): Likewise.
|
||
(tic4x_print_op): Likewise.
|
||
|
||
2016-03-02 Alan Modra <amodra@gmail.com>
|
||
|
||
* or1k-desc.h: Regenerate.
|
||
* fr30-ibld.c: Regenerate.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2016-03-01 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR target/19747
|
||
* rl78-dis.c (print_insn_rl78_common): Fix typo.
|
||
|
||
2016-02-24 Renlin Li <renlin.li@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
|
||
(print_insn_coprocessor): Support fp16 instructions.
|
||
|
||
2016-02-24 Renlin Li <renlin.li@arm.com>
|
||
|
||
* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
|
||
vminnm, vrint(mpna).
|
||
|
||
2016-02-24 Renlin Li <renlin.li@arm.com>
|
||
|
||
* arm-dis.c (print_insn_coprocessor): Check co-processor number for
|
||
cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
|
||
|
||
2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (print_insn): Parenthesize expression to prevent
|
||
truncated addresses.
|
||
(OP_J): Likewise.
|
||
|
||
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
|
||
Janek van Oirschot <jvanoirs@synopsys.com>
|
||
|
||
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
|
||
variable.
|
||
|
||
2016-02-04 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR target/19561
|
||
* msp430-dis.c (print_insn_msp430): Add a special case for
|
||
decoding an RRC instruction with the ZC bit set in the extension
|
||
word.
|
||
|
||
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* cgen-ibld.in (insert_normal): Rework calculation of shift.
|
||
* epiphany-ibld.c: Regenerate.
|
||
* fr30-ibld.c: Regenerate.
|
||
* frv-ibld.c: Regenerate.
|
||
* ip2k-ibld.c: Regenerate.
|
||
* iq2000-ibld.c: Regenerate.
|
||
* lm32-ibld.c: Regenerate.
|
||
* m32c-ibld.c: Regenerate.
|
||
* m32r-ibld.c: Regenerate.
|
||
* mep-ibld.c: Regenerate.
|
||
* mt-ibld.c: Regenerate.
|
||
* or1k-ibld.c: Regenerate.
|
||
* xc16x-ibld.c: Regenerate.
|
||
* xstormy16-ibld.c: Regenerate.
|
||
|
||
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
||
|
||
* epiphany-dis.c: Regenerated from latest cpu files.
|
||
|
||
2016-02-01 Michael McConville <mmcco@mykolab.com>
|
||
|
||
* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
|
||
test bit.
|
||
|
||
2016-01-25 Renlin Li <renlin.li@arm.com>
|
||
|
||
* arm-dis.c (mapping_symbol_for_insn): New function.
|
||
(find_ifthen_state): Call mapping_symbol_for_insn().
|
||
|
||
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Check validity
|
||
of MSR UAO immediate operand.
|
||
|
||
2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
|
||
instruction support.
|
||
|
||
2016-01-17 Alan Modra <amodra@gmail.com>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2016-01-14 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
|
||
instructions that can support stack pointer operations.
|
||
* rl78-decode.c: Regenerate.
|
||
* rl78-dis.c: Fix display of stack pointer in MOVW based
|
||
instructions.
|
||
|
||
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
|
||
testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
|
||
erxtatus_el1 and erxaddr_el1.
|
||
|
||
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* arm-dis.c (arm_opcodes): Add "esb".
|
||
(thumb_opcodes): Likewise.
|
||
|
||
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c <xscmpnedp>: Delete.
|
||
<xvcmpnedp>: Likewise.
|
||
<xvcmpnedp.>: Likewise.
|
||
<xvcmpnesp>: Likewise.
|
||
<xvcmpnesp.>: Likewise.
|
||
|
||
2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
|
||
|
||
PR gas/13050
|
||
* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
|
||
addition to ISA_A.
|
||
|
||
2016-01-01 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2015
|
||
|
||
Copyright (C) 2016 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|