1121 lines
36 KiB
Plaintext
1121 lines
36 KiB
Plaintext
@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
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@c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node ARM-Dependent
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@chapter ARM Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter ARM Dependent Features
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@end ifclear
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@cindex ARM support
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@cindex Thumb support
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@menu
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* ARM Options:: Options
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* ARM Syntax:: Syntax
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* ARM Floating Point:: Floating Point
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* ARM Directives:: ARM Machine Directives
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* ARM Opcodes:: Opcodes
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* ARM Mapping Symbols:: Mapping Symbols
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* ARM Unwinding Tutorial:: Unwinding
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@end menu
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@node ARM Options
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@section Options
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@cindex ARM options (none)
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@cindex options for ARM (none)
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@table @code
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@cindex @code{-mcpu=} command line option, ARM
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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This option specifies the target processor. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor. The following processor names are
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recognized:
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@code{arm1},
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@code{arm2},
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@code{arm250},
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@code{arm3},
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@code{arm6},
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@code{arm60},
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@code{arm600},
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@code{arm610},
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@code{arm620},
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@code{arm7},
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@code{arm7m},
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@code{arm7d},
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@code{arm7dm},
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@code{arm7di},
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@code{arm7dmi},
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@code{arm70},
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@code{arm700},
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@code{arm700i},
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@code{arm710},
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@code{arm710t},
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@code{arm720},
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@code{arm720t},
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@code{arm740t},
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@code{arm710c},
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@code{arm7100},
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@code{arm7500},
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@code{arm7500fe},
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@code{arm7t},
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@code{arm7tdmi},
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@code{arm7tdmi-s},
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@code{arm8},
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@code{arm810},
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@code{strongarm},
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@code{strongarm1},
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@code{strongarm110},
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@code{strongarm1100},
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@code{strongarm1110},
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@code{arm9},
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@code{arm920},
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@code{arm920t},
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@code{arm922t},
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@code{arm940t},
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@code{arm9tdmi},
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@code{fa526} (Faraday FA526 processor),
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@code{fa626} (Faraday FA626 processor),
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@code{arm9e},
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@code{arm926e},
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@code{arm926ej-s},
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@code{arm946e-r0},
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@code{arm946e},
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@code{arm946e-s},
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@code{arm966e-r0},
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@code{arm966e},
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@code{arm966e-s},
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@code{arm968e-s},
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@code{arm10t},
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@code{arm10tdmi},
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@code{arm10e},
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@code{arm1020},
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@code{arm1020t},
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@code{arm1020e},
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@code{arm1022e},
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@code{arm1026ej-s},
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@code{fa626te} (Faraday FA626TE processor),
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@code{fa726te} (Faraday FA726TE processor),
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@code{arm1136j-s},
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@code{arm1136jf-s},
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@code{arm1156t2-s},
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@code{arm1156t2f-s},
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@code{arm1176jz-s},
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@code{arm1176jzf-s},
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@code{mpcore},
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@code{mpcorenovfp},
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@code{cortex-a5},
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@code{cortex-a8},
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@code{cortex-a9},
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@code{cortex-r4},
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@code{cortex-r4f},
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@code{cortex-m3},
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@code{cortex-m1},
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@code{cortex-m0},
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@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
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@code{i80200} (Intel XScale processor)
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@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
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and
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@code{xscale}.
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The special name @code{all} may be used to allow the
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assembler to accept instructions valid for any ARM processor.
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In addition to the basic instruction set, the assembler can be told to
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accept various extension mnemonics that extend the processor using the
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co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
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is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
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are currently supported:
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@code{+maverick}
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@code{+iwmmxt}
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and
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@code{+xscale}.
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@cindex @code{-march=} command line option, ARM
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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This option specifies the target architecture. The assembler will issue
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an error message if an attempt is made to assemble an instruction which
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will not execute on the target architecture. The following architecture
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names are recognized:
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@code{armv1},
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@code{armv2},
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@code{armv2a},
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@code{armv2s},
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@code{armv3},
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@code{armv3m},
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@code{armv4},
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@code{armv4xm},
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@code{armv4t},
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@code{armv4txm},
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@code{armv5},
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@code{armv5t},
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@code{armv5txm},
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@code{armv5te},
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@code{armv5texp},
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@code{armv6},
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@code{armv6j},
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@code{armv6k},
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@code{armv6z},
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@code{armv6zk},
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@code{armv7},
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@code{armv7-a},
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@code{armv7-r},
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@code{armv7-m},
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@code{armv7e-m},
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@code{iwmmxt}
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and
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@code{xscale}.
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If both @code{-mcpu} and
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@code{-march} are specified, the assembler will use
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the setting for @code{-mcpu}.
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The architecture option can be extended with the same instruction set
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extension options as the @code{-mcpu} option.
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@cindex @code{-mfpu=} command line option, ARM
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@item -mfpu=@var{floating-point-format}
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This option specifies the floating point format to assemble for. The
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assembler will issue an error message if an attempt is made to assemble
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an instruction which will not execute on the target floating point unit.
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The following format options are recognized:
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@code{softfpa},
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@code{fpe},
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@code{fpe2},
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@code{fpe3},
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@code{fpa},
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@code{fpa10},
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@code{fpa11},
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@code{arm7500fe},
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@code{softvfp},
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@code{softvfp+vfp},
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@code{vfp},
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@code{vfp10},
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@code{vfp10-r0},
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@code{vfp9},
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@code{vfpxd},
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@code{vfpv2},
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@code{vfpv3},
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@code{vfpv3-fp16},
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@code{vfpv3-d16},
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@code{vfpv3-d16-fp16},
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@code{vfpv3xd},
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@code{vfpv3xd-d16},
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@code{vfpv4},
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@code{vfpv4-d16},
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@code{arm1020t},
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@code{arm1020e},
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@code{arm1136jf-s},
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@code{maverick},
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@code{neon},
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and
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@code{neon-vfpv4}.
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In addition to determining which instructions are assembled, this option
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also affects the way in which the @code{.double} assembler directive behaves
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when assembling little-endian code.
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The default is dependent on the processor selected. For Architecture 5 or
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later, the default is to assembler for VFP instructions; for earlier
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architectures the default is to assemble for FPA instructions.
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@cindex @code{-mthumb} command line option, ARM
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@item -mthumb
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This option specifies that the assembler should start assembling Thumb
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instructions; that is, it should behave as though the file starts with a
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@code{.code 16} directive.
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@cindex @code{-mthumb-interwork} command line option, ARM
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@item -mthumb-interwork
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This option specifies that the output generated by the assembler should
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be marked as supporting interworking.
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@cindex @code{-mimplicit-it} command line option, ARM
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@item -mimplicit-it=never
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@itemx -mimplicit-it=always
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@itemx -mimplicit-it=arm
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@itemx -mimplicit-it=thumb
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The @code{-mimplicit-it} option controls the behavior of the assembler when
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conditional instructions are not enclosed in IT blocks.
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There are four possible behaviors.
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If @code{never} is specified, such constructs cause a warning in ARM
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code and an error in Thumb-2 code.
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If @code{always} is specified, such constructs are accepted in both
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ARM and Thumb-2 code, where the IT instruction is added implicitly.
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If @code{arm} is specified, such constructs are accepted in ARM code
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and cause an error in Thumb-2 code.
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If @code{thumb} is specified, such constructs cause a warning in ARM
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code and are accepted in Thumb-2 code. If you omit this option, the
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behavior is equivalent to @code{-mimplicit-it=arm}.
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@cindex @code{-mapcs-26} command line option, ARM
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@cindex @code{-mapcs-32} command line option, ARM
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@item -mapcs-26
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@itemx -mapcs-32
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These options specify that the output generated by the assembler should
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be marked as supporting the indicated version of the Arm Procedure.
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Calling Standard.
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@cindex @code{-matpcs} command line option, ARM
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@item -matpcs
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This option specifies that the output generated by the assembler should
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be marked as supporting the Arm/Thumb Procedure Calling Standard. If
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enabled this option will cause the assembler to create an empty
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debugging section in the object file called .arm.atpcs. Debuggers can
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use this to determine the ABI being used by.
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@cindex @code{-mapcs-float} command line option, ARM
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@item -mapcs-float
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This indicates the floating point variant of the APCS should be
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used. In this variant floating point arguments are passed in FP
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registers rather than integer registers.
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@cindex @code{-mapcs-reentrant} command line option, ARM
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@item -mapcs-reentrant
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This indicates that the reentrant variant of the APCS should be used.
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This variant supports position independent code.
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@cindex @code{-mfloat-abi=} command line option, ARM
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@item -mfloat-abi=@var{abi}
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This option specifies that the output generated by the assembler should be
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marked as using specified floating point ABI.
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The following values are recognized:
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@code{soft},
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@code{softfp}
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and
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@code{hard}.
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@cindex @code{-eabi=} command line option, ARM
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@item -meabi=@var{ver}
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This option specifies which EABI version the produced object files should
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conform to.
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The following values are recognized:
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@code{gnu},
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@code{4}
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and
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@code{5}.
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@cindex @code{-EB} command line option, ARM
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command line option, ARM
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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@cindex @code{-k} command line option, ARM
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@cindex PIC code generation for ARM
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@item -k
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This option specifies that the output of the assembler should be marked
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as position-independent code (PIC).
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@cindex @code{--fix-v4bx} command line option, ARM
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@item --fix-v4bx
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Allow @code{BX} instructions in ARMv4 code. This is intended for use with
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the linker option of the same name.
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@cindex @code{-mwarn-deprecated} command line option, ARM
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@item -mwarn-deprecated
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@itemx -mno-warn-deprecated
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Enable or disable warnings about using deprecated options or
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features. The default is to warn.
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@end table
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@node ARM Syntax
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@section Syntax
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@menu
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* ARM-Instruction-Set:: Instruction Set
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* ARM-Chars:: Special Characters
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* ARM-Regs:: Register Names
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* ARM-Relocations:: Relocations
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* ARM-Neon-Alignment:: NEON Alignment Specifiers
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@end menu
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@node ARM-Instruction-Set
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@subsection Instruction Set Syntax
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Two slightly different syntaxes are support for ARM and THUMB
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instructions. The default, @code{divided}, uses the old style where
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ARM and THUMB instructions had their own, separate syntaxes. The new,
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@code{unified} syntax, which can be selected via the @code{.syntax}
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directive, and has the following main features:
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@table @bullet
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@item
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Immediate operands do not require a @code{#} prefix.
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@item
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The @code{IT} instruction may appear, and if it does it is validated
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against subsequent conditional affixes. In ARM mode it does not
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generate machine code, in THUMB mode it does.
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@item
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For ARM instructions the conditional affixes always appear at the end
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of the instruction. For THUMB instructions conditional affixes can be
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used, but only inside the scope of an @code{IT} instruction.
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@item
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All of the instructions new to the V6T2 architecture (and later) are
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available. (Only a few such instructions can be written in the
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@code{divided} syntax).
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@item
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The @code{.N} and @code{.W} suffixes are recognized and honored.
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@item
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All instructions set the flags if and only if they have an @code{s}
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affix.
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@end table
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@node ARM-Chars
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@subsection Special Characters
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@cindex line comment character, ARM
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@cindex ARM line comment character
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The presence of a @samp{@@} on a line indicates the start of a comment
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that extends to the end of the current line. If a @samp{#} appears as
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the first character of a line, the whole line is treated as a comment.
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@cindex line separator, ARM
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@cindex statement separator, ARM
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@cindex ARM line separator
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The @samp{;} character can be used instead of a newline to separate
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statements.
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@cindex immediate character, ARM
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@cindex ARM immediate character
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Either @samp{#} or @samp{$} can be used to indicate immediate operands.
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@cindex identifiers, ARM
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@cindex ARM identifiers
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*TODO* Explain about /data modifier on symbols.
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@node ARM-Regs
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@subsection Register Names
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@cindex ARM register names
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@cindex register names, ARM
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*TODO* Explain about ARM register naming, and the predefined names.
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@node ARM-Neon-Alignment
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@subsection NEON Alignment Specifiers
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@cindex alignment for NEON instructions
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Some NEON load/store instructions allow an optional address
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alignment qualifier.
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The ARM documentation specifies that this is indicated by
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@samp{@@ @var{align}}. However GAS already interprets
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the @samp{@@} character as a "line comment" start,
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so @samp{: @var{align}} is used instead. For example:
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@smallexample
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vld1.8 @{q0@}, [r0, :128]
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@end smallexample
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@node ARM Floating Point
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@section Floating Point
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@cindex floating point, ARM (@sc{ieee})
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@cindex ARM floating point (@sc{ieee})
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The ARM family uses @sc{ieee} floating-point numbers.
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@node ARM-Relocations
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@subsection ARM relocation generation
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@cindex data relocations, ARM
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@cindex ARM data relocations
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Specific data relocations can be generated by putting the relocation name
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in parentheses after the symbol name. For example:
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@smallexample
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.word foo(TARGET1)
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@end smallexample
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This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
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@var{foo}.
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The following relocations are supported:
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@code{GOT},
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@code{GOTOFF},
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@code{TARGET1},
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@code{TARGET2},
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@code{SBREL},
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@code{TLSGD},
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@code{TLSLDM},
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@code{TLSLDO},
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@code{GOTTPOFF},
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@code{GOT_PREL}
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and
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@code{TPOFF}.
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For compatibility with older toolchains the assembler also accepts
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@code{(PLT)} after branch targets. This will generate the deprecated
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@samp{R_ARM_PLT32} relocation.
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@cindex MOVW and MOVT relocations, ARM
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Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
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by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
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respectively. For example to load the 32-bit address of foo into r0:
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@smallexample
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MOVW r0, #:lower16:foo
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MOVT r0, #:upper16:foo
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@end smallexample
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@node ARM Directives
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@section ARM Machine Directives
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@cindex machine directives, ARM
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@cindex ARM machine directives
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@table @code
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@c AAAAAAAAAAAAAAAAAAAAAAAAA
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@cindex @code{.2byte} directive, ARM
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@cindex @code{.4byte} directive, ARM
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@cindex @code{.8byte} directive, ARM
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@item .2byte @var{expression} [, @var{expression}]*
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@itemx .4byte @var{expression} [, @var{expression}]*
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@itemx .8byte @var{expression} [, @var{expression}]*
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These directives write 2, 4 or 8 byte values to the output section.
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@cindex @code{.align} directive, ARM
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@item .align @var{expression} [, @var{expression}]
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This is the generic @var{.align} directive. For the ARM however if the
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first argument is zero (ie no alignment is needed) the assembler will
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behave as if the argument had been 2 (ie pad to the next four byte
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boundary). This is for compatibility with ARM's own assembler.
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@cindex @code{.arch} directive, ARM
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@item .arch @var{name}
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Select the target architecture. Valid values for @var{name} are the same as
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for the @option{-march} commandline option.
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@cindex @code{.arm} directive, ARM
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@item .arm
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This performs the same action as @var{.code 32}.
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|
|
|
@anchor{arm_pad}
|
|
@cindex @code{.pad} directive, ARM
|
|
@item .pad #@var{count}
|
|
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
|
|
A positive value indicates the function prologue allocated stack space by
|
|
decrementing the stack pointer.
|
|
|
|
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
|
|
|
|
@cindex @code{.bss} directive, ARM
|
|
@item .bss
|
|
This directive switches to the @code{.bss} section.
|
|
|
|
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
|
|
|
|
@cindex @code{.cantunwind} directive, ARM
|
|
@item .cantunwind
|
|
Prevents unwinding through the current function. No personality routine
|
|
or exception table data is required or permitted.
|
|
|
|
@cindex @code{.code} directive, ARM
|
|
@item .code @code{[16|32]}
|
|
This directive selects the instruction set being generated. The value 16
|
|
selects Thumb, with the value 32 selecting ARM.
|
|
|
|
@cindex @code{.cpu} directive, ARM
|
|
@item .cpu @var{name}
|
|
Select the target processor. Valid values for @var{name} are the same as
|
|
for the @option{-mcpu} commandline option.
|
|
|
|
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
|
|
|
|
@cindex @code{.dn} and @code{.qn} directives, ARM
|
|
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
|
|
@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
|
|
|
|
The @code{dn} and @code{qn} directives are used to create typed
|
|
and/or indexed register aliases for use in Advanced SIMD Extension
|
|
(Neon) instructions. The former should be used to create aliases
|
|
of double-precision registers, and the latter to create aliases of
|
|
quad-precision registers.
|
|
|
|
If these directives are used to create typed aliases, those aliases can
|
|
be used in Neon instructions instead of writing types after the mnemonic
|
|
or after each operand. For example:
|
|
|
|
@smallexample
|
|
x .dn d2.f32
|
|
y .dn d3.f32
|
|
z .dn d4.f32[1]
|
|
vmul x,y,z
|
|
@end smallexample
|
|
|
|
This is equivalent to writing the following:
|
|
|
|
@smallexample
|
|
vmul.f32 d2,d3,d4[1]
|
|
@end smallexample
|
|
|
|
Aliases created using @code{dn} or @code{qn} can be destroyed using
|
|
@code{unreq}.
|
|
|
|
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
|
|
|
|
@cindex @code{.eabi_attribute} directive, ARM
|
|
@item .eabi_attribute @var{tag}, @var{value}
|
|
Set the EABI object attribute @var{tag} to @var{value}.
|
|
|
|
The @var{tag} is either an attribute number, or one of the following:
|
|
@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
|
|
@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
|
|
@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
|
|
@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
|
|
@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
|
|
@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
|
|
@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
|
|
@code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
|
|
@code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
|
|
@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
|
|
@code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
|
|
@code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
|
|
@code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
|
|
@code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
|
|
@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
|
|
@code{Tag_MPextension_use}, @code{Tag_DIV_use},
|
|
@code{Tag_nodefaults}, @code{Tag_also_compatible_with},
|
|
@code{Tag_conformance}, @code{Tag_T2EE_use},
|
|
@code{Tag_Virtualization_use}
|
|
|
|
The @var{value} is either a @code{number}, @code{"string"}, or
|
|
@code{number, "string"} depending on the tag.
|
|
|
|
Note - the following legacy values are also accepted by @var{tag}:
|
|
@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
|
|
@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
|
|
|
|
@cindex @code{.even} directive, ARM
|
|
@item .even
|
|
This directive aligns to an even-numbered address.
|
|
|
|
@cindex @code{.extend} directive, ARM
|
|
@cindex @code{.ldouble} directive, ARM
|
|
@item .extend @var{expression} [, @var{expression}]*
|
|
@itemx .ldouble @var{expression} [, @var{expression}]*
|
|
These directives write 12byte long double floating-point values to the
|
|
output section. These are not compatible with current ARM processors
|
|
or ABIs.
|
|
|
|
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
|
|
|
|
@anchor{arm_fnend}
|
|
@cindex @code{.fnend} directive, ARM
|
|
@item .fnend
|
|
Marks the end of a function with an unwind table entry. The unwind index
|
|
table entry is created when this directive is processed.
|
|
|
|
If no personality routine has been specified then standard personality
|
|
routine 0 or 1 will be used, depending on the number of unwind opcodes
|
|
required.
|
|
|
|
@anchor{arm_fnstart}
|
|
@cindex @code{.fnstart} directive, ARM
|
|
@item .fnstart
|
|
Marks the start of a function with an unwind table entry.
|
|
|
|
@cindex @code{.force_thumb} directive, ARM
|
|
@item .force_thumb
|
|
This directive forces the selection of Thumb instructions, even if the
|
|
target processor does not support those instructions
|
|
|
|
@cindex @code{.fpu} directive, ARM
|
|
@item .fpu @var{name}
|
|
Select the floating-point unit to assemble for. Valid values for @var{name}
|
|
are the same as for the @option{-mfpu} commandline option.
|
|
|
|
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
|
|
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
|
|
|
|
@cindex @code{.handlerdata} directive, ARM
|
|
@item .handlerdata
|
|
Marks the end of the current function, and the start of the exception table
|
|
entry for that function. Anything between this directive and the
|
|
@code{.fnend} directive will be added to the exception table entry.
|
|
|
|
Must be preceded by a @code{.personality} or @code{.personalityindex}
|
|
directive.
|
|
|
|
@c IIIIIIIIIIIIIIIIIIIIIIIIII
|
|
|
|
@cindex @code{.inst} directive, ARM
|
|
@item .inst @var{opcode} [ , @dots{} ]
|
|
@item .inst.n @var{opcode} [ , @dots{} ]
|
|
@item .inst.w @var{opcode} [ , @dots{} ]
|
|
Generates the instruction corresponding to the numerical value @var{opcode}.
|
|
@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
|
|
specified explicitly, overriding the normal encoding rules.
|
|
|
|
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
|
|
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
|
|
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
|
|
|
|
@item .ldouble @var{expression} [, @var{expression}]*
|
|
See @code{.extend}.
|
|
|
|
@cindex @code{.ltorg} directive, ARM
|
|
@item .ltorg
|
|
This directive causes the current contents of the literal pool to be
|
|
dumped into the current section (which is assumed to be the .text
|
|
section) at the current location (aligned to a word boundary).
|
|
@code{GAS} maintains a separate literal pool for each section and each
|
|
sub-section. The @code{.ltorg} directive will only affect the literal
|
|
pool of the current section and sub-section. At the end of assembly
|
|
all remaining, un-empty literal pools will automatically be dumped.
|
|
|
|
Note - older versions of @code{GAS} would dump the current literal
|
|
pool any time a section change occurred. This is no longer done, since
|
|
it prevents accurate control of the placement of literal pools.
|
|
|
|
@c MMMMMMMMMMMMMMMMMMMMMMMMMM
|
|
|
|
@cindex @code{.movsp} directive, ARM
|
|
@item .movsp @var{reg} [, #@var{offset}]
|
|
Tell the unwinder that @var{reg} contains an offset from the current
|
|
stack pointer. If @var{offset} is not specified then it is assumed to be
|
|
zero.
|
|
|
|
@c NNNNNNNNNNNNNNNNNNNNNNNNNN
|
|
@c OOOOOOOOOOOOOOOOOOOOOOOOOO
|
|
|
|
@cindex @code{.object_arch} directive, ARM
|
|
@item .object_arch @var{name}
|
|
Override the architecture recorded in the EABI object attribute section.
|
|
Valid values for @var{name} are the same as for the @code{.arch} directive.
|
|
Typically this is useful when code uses runtime detection of CPU features.
|
|
|
|
@c PPPPPPPPPPPPPPPPPPPPPPPPPP
|
|
|
|
@cindex @code{.packed} directive, ARM
|
|
@item .packed @var{expression} [, @var{expression}]*
|
|
This directive writes 12-byte packed floating-point values to the
|
|
output section. These are not compatible with current ARM processors
|
|
or ABIs.
|
|
|
|
@cindex @code{.pad} directive, ARM
|
|
@item .pad #@var{count}
|
|
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
|
|
A positive value indicates the function prologue allocated stack space by
|
|
decrementing the stack pointer.
|
|
|
|
@cindex @code{.personality} directive, ARM
|
|
@item .personality @var{name}
|
|
Sets the personality routine for the current function to @var{name}.
|
|
|
|
@cindex @code{.personalityindex} directive, ARM
|
|
@item .personalityindex @var{index}
|
|
Sets the personality routine for the current function to the EABI standard
|
|
routine number @var{index}
|
|
|
|
@cindex @code{.pool} directive, ARM
|
|
@item .pool
|
|
This is a synonym for .ltorg.
|
|
|
|
@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
|
|
@c RRRRRRRRRRRRRRRRRRRRRRRRRR
|
|
|
|
@cindex @code{.req} directive, ARM
|
|
@item @var{name} .req @var{register name}
|
|
This creates an alias for @var{register name} called @var{name}. For
|
|
example:
|
|
|
|
@smallexample
|
|
foo .req r0
|
|
@end smallexample
|
|
|
|
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
|
|
|
|
@anchor{arm_save}
|
|
@cindex @code{.save} directive, ARM
|
|
@item .save @var{reglist}
|
|
Generate unwinder annotations to restore the registers in @var{reglist}.
|
|
The format of @var{reglist} is the same as the corresponding store-multiple
|
|
instruction.
|
|
|
|
@smallexample
|
|
@exdent @emph{core registers}
|
|
.save @{r4, r5, r6, lr@}
|
|
stmfd sp!, @{r4, r5, r6, lr@}
|
|
@exdent @emph{FPA registers}
|
|
.save f4, 2
|
|
sfmfd f4, 2, [sp]!
|
|
@exdent @emph{VFP registers}
|
|
.save @{d8, d9, d10@}
|
|
fstmdx sp!, @{d8, d9, d10@}
|
|
@exdent @emph{iWMMXt registers}
|
|
.save @{wr10, wr11@}
|
|
wstrd wr11, [sp, #-8]!
|
|
wstrd wr10, [sp, #-8]!
|
|
or
|
|
.save wr11
|
|
wstrd wr11, [sp, #-8]!
|
|
.save wr10
|
|
wstrd wr10, [sp, #-8]!
|
|
@end smallexample
|
|
|
|
@anchor{arm_setfp}
|
|
@cindex @code{.setfp} directive, ARM
|
|
@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
|
|
Make all unwinder annotations relative to a frame pointer. Without this
|
|
the unwinder will use offsets from the stack pointer.
|
|
|
|
The syntax of this directive is the same as the @code{add} or @code{mov}
|
|
instruction used to set the frame pointer. @var{spreg} must be either
|
|
@code{sp} or mentioned in a previous @code{.movsp} directive.
|
|
|
|
@smallexample
|
|
.movsp ip
|
|
mov ip, sp
|
|
@dots{}
|
|
.setfp fp, ip, #4
|
|
add fp, ip, #4
|
|
@end smallexample
|
|
|
|
@cindex @code{.secrel32} directive, ARM
|
|
@item .secrel32 @var{expression} [, @var{expression}]*
|
|
This directive emits relocations that evaluate to the section-relative
|
|
offset of each expression's symbol. This directive is only supported
|
|
for PE targets.
|
|
|
|
@cindex @code{.syntax} directive, ARM
|
|
@item .syntax [@code{unified} | @code{divided}]
|
|
This directive sets the Instruction Set Syntax as described in the
|
|
@ref{ARM-Instruction-Set} section.
|
|
|
|
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
|
|
|
|
@cindex @code{.thumb} directive, ARM
|
|
@item .thumb
|
|
This performs the same action as @var{.code 16}.
|
|
|
|
@cindex @code{.thumb_func} directive, ARM
|
|
@item .thumb_func
|
|
This directive specifies that the following symbol is the name of a
|
|
Thumb encoded function. This information is necessary in order to allow
|
|
the assembler and linker to generate correct code for interworking
|
|
between Arm and Thumb instructions and should be used even if
|
|
interworking is not going to be performed. The presence of this
|
|
directive also implies @code{.thumb}
|
|
|
|
This directive is not neccessary when generating EABI objects. On these
|
|
targets the encoding is implicit when generating Thumb code.
|
|
|
|
@cindex @code{.thumb_set} directive, ARM
|
|
@item .thumb_set
|
|
This performs the equivalent of a @code{.set} directive in that it
|
|
creates a symbol which is an alias for another symbol (possibly not yet
|
|
defined). This directive also has the added property in that it marks
|
|
the aliased symbol as being a thumb function entry point, in the same
|
|
way that the @code{.thumb_func} directive does.
|
|
|
|
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
|
|
|
|
@cindex @code{.unreq} directive, ARM
|
|
@item .unreq @var{alias-name}
|
|
This undefines a register alias which was previously defined using the
|
|
@code{req}, @code{dn} or @code{qn} directives. For example:
|
|
|
|
@smallexample
|
|
foo .req r0
|
|
.unreq foo
|
|
@end smallexample
|
|
|
|
An error occurs if the name is undefined. Note - this pseudo op can
|
|
be used to delete builtin in register name aliases (eg 'r0'). This
|
|
should only be done if it is really necessary.
|
|
|
|
@cindex @code{.unwind_raw} directive, ARM
|
|
@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
|
|
Insert one of more arbitary unwind opcode bytes, which are known to adjust
|
|
the stack pointer by @var{offset} bytes.
|
|
|
|
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
|
|
@code{.save @{r0@}}
|
|
|
|
@c VVVVVVVVVVVVVVVVVVVVVVVVVV
|
|
|
|
@cindex @code{.vsave} directive, ARM
|
|
@item .vsave @var{vfp-reglist}
|
|
Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
|
|
using FLDMD. Also works for VFPv3 registers
|
|
that are to be restored using VLDM.
|
|
The format of @var{vfp-reglist} is the same as the corresponding store-multiple
|
|
instruction.
|
|
|
|
@smallexample
|
|
@exdent @emph{VFP registers}
|
|
.vsave @{d8, d9, d10@}
|
|
fstmdd sp!, @{d8, d9, d10@}
|
|
@exdent @emph{VFPv3 registers}
|
|
.vsave @{d15, d16, d17@}
|
|
vstm sp!, @{d15, d16, d17@}
|
|
@end smallexample
|
|
|
|
Since FLDMX and FSTMX are now deprecated, this directive should be
|
|
used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
|
|
|
|
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
|
|
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
|
|
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
|
|
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
|
|
|
|
@end table
|
|
|
|
@node ARM Opcodes
|
|
@section Opcodes
|
|
|
|
@cindex ARM opcodes
|
|
@cindex opcodes for ARM
|
|
@code{@value{AS}} implements all the standard ARM opcodes. It also
|
|
implements several pseudo opcodes, including several synthetic load
|
|
instructions.
|
|
|
|
@table @code
|
|
|
|
@cindex @code{NOP} pseudo op, ARM
|
|
@item NOP
|
|
@smallexample
|
|
nop
|
|
@end smallexample
|
|
|
|
This pseudo op will always evaluate to a legal ARM instruction that does
|
|
nothing. Currently it will evaluate to MOV r0, r0.
|
|
|
|
@cindex @code{LDR reg,=<label>} pseudo op, ARM
|
|
@item LDR
|
|
@smallexample
|
|
ldr <register> , = <expression>
|
|
@end smallexample
|
|
|
|
If expression evaluates to a numeric constant then a MOV or MVN
|
|
instruction will be used in place of the LDR instruction, if the
|
|
constant can be generated by either of these instructions. Otherwise
|
|
the constant will be placed into the nearest literal pool (if it not
|
|
already there) and a PC relative LDR instruction will be generated.
|
|
|
|
@cindex @code{ADR reg,<label>} pseudo op, ARM
|
|
@item ADR
|
|
@smallexample
|
|
adr <register> <label>
|
|
@end smallexample
|
|
|
|
This instruction will load the address of @var{label} into the indicated
|
|
register. The instruction will evaluate to a PC relative ADD or SUB
|
|
instruction depending upon where the label is located. If the label is
|
|
out of range, or if it is not defined in the same file (and section) as
|
|
the ADR instruction, then an error will be generated. This instruction
|
|
will not make use of the literal pool.
|
|
|
|
@cindex @code{ADRL reg,<label>} pseudo op, ARM
|
|
@item ADRL
|
|
@smallexample
|
|
adrl <register> <label>
|
|
@end smallexample
|
|
|
|
This instruction will load the address of @var{label} into the indicated
|
|
register. The instruction will evaluate to one or two PC relative ADD
|
|
or SUB instructions depending upon where the label is located. If a
|
|
second instruction is not needed a NOP instruction will be generated in
|
|
its place, so that this instruction is always 8 bytes long.
|
|
|
|
If the label is out of range, or if it is not defined in the same file
|
|
(and section) as the ADRL instruction, then an error will be generated.
|
|
This instruction will not make use of the literal pool.
|
|
|
|
@end table
|
|
|
|
For information on the ARM or Thumb instruction sets, see @cite{ARM
|
|
Software Development Toolkit Reference Manual}, Advanced RISC Machines
|
|
Ltd.
|
|
|
|
@node ARM Mapping Symbols
|
|
@section Mapping Symbols
|
|
|
|
The ARM ELF specification requires that special symbols be inserted
|
|
into object files to mark certain features:
|
|
|
|
@table @code
|
|
|
|
@cindex @code{$a}
|
|
@item $a
|
|
At the start of a region of code containing ARM instructions.
|
|
|
|
@cindex @code{$t}
|
|
@item $t
|
|
At the start of a region of code containing THUMB instructions.
|
|
|
|
@cindex @code{$d}
|
|
@item $d
|
|
At the start of a region of data.
|
|
|
|
@end table
|
|
|
|
The assembler will automatically insert these symbols for you - there
|
|
is no need to code them yourself. Support for tagging symbols ($b,
|
|
$f, $p and $m) which is also mentioned in the current ARM ELF
|
|
specification is not implemented. This is because they have been
|
|
dropped from the new EABI and so tools cannot rely upon their
|
|
presence.
|
|
|
|
@node ARM Unwinding Tutorial
|
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@section Unwinding
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The ABI for the ARM Architecture specifies a standard format for
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exception unwind information. This information is used when an
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exception is thrown to determine where control should be transferred.
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In particular, the unwind information is used to determine which
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function called the function that threw the exception, and which
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function called that one, and so forth. This information is also used
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to restore the values of callee-saved registers in the function
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catching the exception.
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If you are writing functions in assembly code, and those functions
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call other functions that throw exceptions, you must use assembly
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pseudo ops to ensure that appropriate exception unwind information is
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generated. Otherwise, if one of the functions called by your assembly
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code throws an exception, the run-time library will be unable to
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unwind the stack through your assembly code and your program will not
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behave correctly.
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To illustrate the use of these pseudo ops, we will examine the code
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that G++ generates for the following C++ input:
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@verbatim
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void callee (int *);
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int
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caller ()
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{
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int i;
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callee (&i);
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return i;
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}
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@end verbatim
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This example does not show how to throw or catch an exception from
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assembly code. That is a much more complex operation and should
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always be done in a high-level language, such as C++, that directly
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supports exceptions.
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The code generated by one particular version of G++ when compiling the
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example above is:
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@verbatim
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_Z6callerv:
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.fnstart
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.LFB2:
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@ Function supports interworking.
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@ args = 0, pretend = 0, frame = 8
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@ frame_needed = 1, uses_anonymous_args = 0
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stmfd sp!, {fp, lr}
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.save {fp, lr}
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.LCFI0:
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.setfp fp, sp, #4
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add fp, sp, #4
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.LCFI1:
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.pad #8
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sub sp, sp, #8
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.LCFI2:
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sub r3, fp, #8
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mov r0, r3
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bl _Z6calleePi
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ldr r3, [fp, #-8]
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mov r0, r3
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sub sp, fp, #4
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ldmfd sp!, {fp, lr}
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bx lr
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.LFE2:
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.fnend
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@end verbatim
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Of course, the sequence of instructions varies based on the options
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you pass to GCC and on the version of GCC in use. The exact
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instructions are not important since we are focusing on the pseudo ops
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that are used to generate unwind information.
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An important assumption made by the unwinder is that the stack frame
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does not change during the body of the function. In particular, since
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we assume that the assembly code does not itself throw an exception,
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the only point where an exception can be thrown is from a call, such
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as the @code{bl} instruction above. At each call site, the same saved
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registers (including @code{lr}, which indicates the return address)
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must be located in the same locations relative to the frame pointer.
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The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
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op appears immediately before the first instruction of the function
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while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
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op appears immediately after the last instruction of the function.
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These pseudo ops specify the range of the function.
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Only the order of the other pseudos ops (e.g., @code{.setfp} or
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@code{.pad}) matters; their exact locations are irrelevant. In the
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example above, the compiler emits the pseudo ops with particular
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instructions. That makes it easier to understand the code, but it is
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not required for correctness. It would work just as well to emit all
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of the pseudo ops other than @code{.fnend} in the same order, but
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immediately after @code{.fnstart}.
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The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
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indicates registers that have been saved to the stack so that they can
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be restored before the function returns. The argument to the
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@code{.save} pseudo op is a list of registers to save. If a register
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is ``callee-saved'' (as specified by the ABI) and is modified by the
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function you are writing, then your code must save the value before it
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is modified and restore the original value before the function
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returns. If an exception is thrown, the run-time library restores the
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values of these registers from their locations on the stack before
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returning control to the exception handler. (Of course, if an
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exception is not thrown, the function that contains the @code{.save}
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pseudo op restores these registers in the function epilogue, as is
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done with the @code{ldmfd} instruction above.)
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You do not have to save callee-saved registers at the very beginning
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of the function and you do not need to use the @code{.save} pseudo op
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immediately following the point at which the registers are saved.
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However, if you modify a callee-saved register, you must save it on
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the stack before modifying it and before calling any functions which
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might throw an exception. And, you must use the @code{.save} pseudo
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op to indicate that you have done so.
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The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
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modification of the stack pointer that does not save any registers.
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The argument is the number of bytes (in decimal) that are subtracted
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from the stack pointer. (On ARM CPUs, the stack grows downwards, so
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subtracting from the stack pointer increases the size of the stack.)
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The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
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indicates the register that contains the frame pointer. The first
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argument is the register that is set, which is typically @code{fp}.
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The second argument indicates the register from which the frame
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pointer takes its value. The third argument, if present, is the value
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(in decimal) added to the register specified by the second argument to
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compute the value of the frame pointer. You should not modify the
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frame pointer in the body of the function.
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If you do not use a frame pointer, then you should not use the
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@code{.setfp} pseudo op. If you do not use a frame pointer, then you
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should avoid modifying the stack pointer outside of the function
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prologue. Otherwise, the run-time library will be unable to find
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saved registers when it is unwinding the stack.
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The pseudo ops described above are sufficient for writing assembly
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code that calls functions which may throw exceptions. If you need to
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know more about the object-file format used to represent unwind
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information, you may consult the @cite{Exception Handling ABI for the
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ARM Architecture} available from @uref{http://infocenter.arm.com}.
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