662 lines
18 KiB
C
662 lines
18 KiB
C
/* dv-m68hc11sio.c -- Simulation of the 68HC11 serial device.
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Copyright (C) 1999-2020 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@worldnet.fr)
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(From a driver model Contributed by Cygnus Solutions.)
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This file is part of the program GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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#include "dv-sockser.h"
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#include "sim-assert.h"
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/* DEVICE
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m68hc11sio - m68hc11 serial I/O
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DESCRIPTION
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Implements the m68hc11 serial I/O controller described in the m68hc11
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user guide. The serial I/O controller is directly connected to the CPU
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interrupt. The simulator implements:
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- baud rate emulation
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- 8-bits transfers
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PROPERTIES
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backend {tcp | stdio}
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Use dv-sockser TCP-port backend or stdio for backend. Default: stdio.
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PORTS
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reset (input)
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Reset port. This port is only used to simulate a reset of the serial
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I/O controller. It should be connected to the RESET output of the cpu.
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*/
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/* port ID's */
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enum
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{
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RESET_PORT
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};
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static const struct hw_port_descriptor m68hc11sio_ports[] =
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{
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{ "reset", RESET_PORT, 0, input_port, },
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{ NULL, },
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};
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/* Serial Controller information. */
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struct m68hc11sio
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{
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enum {sio_tcp, sio_stdio} backend; /* backend */
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/* Number of cpu cycles to send a bit on the wire. */
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unsigned long baud_cycle;
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/* Length in bits of characters sent, this includes the
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start/stop and parity bits. Together with baud_cycle, this
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is used to find the number of cpu cycles to send/receive a data. */
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unsigned int data_length;
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/* Information about next character to be transmited. */
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unsigned char tx_has_char;
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unsigned char tx_char;
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unsigned char rx_char;
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unsigned char rx_clear_scsr;
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/* Periodic I/O polling. */
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struct hw_event* tx_poll_event;
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struct hw_event* rx_poll_event;
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc. */
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static hw_io_read_buffer_method m68hc11sio_io_read_buffer;
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static hw_io_write_buffer_method m68hc11sio_io_write_buffer;
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static hw_port_event_method m68hc11sio_port_event;
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static hw_ioctl_method m68hc11sio_ioctl;
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#define M6811_SCI_FIRST_REG (M6811_BAUD)
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#define M6811_SCI_LAST_REG (M6811_SCDR)
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static void
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attach_m68hc11sio_regs (struct hw *me,
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struct m68hc11sio *controller)
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{
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hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
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M6811_SCI_FIRST_REG,
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M6811_SCI_LAST_REG - M6811_SCI_FIRST_REG + 1,
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me);
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if (hw_find_property(me, "backend") != NULL)
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{
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const char *value = hw_find_string_property(me, "backend");
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if(! strcmp(value, "tcp"))
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controller->backend = sio_tcp;
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else if(! strcmp(value, "stdio"))
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controller->backend = sio_stdio;
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else
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hw_abort (me, "illegal value for backend parameter `%s':"
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"use tcp or stdio", value);
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}
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}
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static void
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m68hc11sio_finish (struct hw *me)
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{
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struct m68hc11sio *controller;
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controller = HW_ZALLOC (me, struct m68hc11sio);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, m68hc11sio_io_read_buffer);
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set_hw_io_write_buffer (me, m68hc11sio_io_write_buffer);
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set_hw_ports (me, m68hc11sio_ports);
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set_hw_port_event (me, m68hc11sio_port_event);
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#ifdef set_hw_ioctl
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set_hw_ioctl (me, m68hc11sio_ioctl);
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#else
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me->to_ioctl = m68hc11sio_ioctl;
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#endif
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/* Preset defaults. */
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controller->backend = sio_stdio;
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/* Attach ourself to our parent bus. */
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attach_m68hc11sio_regs (me, controller);
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/* Initialize to reset state. */
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controller->tx_poll_event = NULL;
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controller->rx_poll_event = NULL;
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controller->tx_char = 0;
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controller->tx_has_char = 0;
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controller->rx_clear_scsr = 0;
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controller->rx_char = 0;
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}
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/* An event arrives on an interrupt port. */
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static void
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m68hc11sio_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int level)
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{
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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unsigned8 val;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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switch (my_port)
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{
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case RESET_PORT:
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{
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HW_TRACE ((me, "SCI reset"));
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/* Reset the state of SCI registers. */
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val = 0;
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m68hc11sio_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_BAUD, 1);
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m68hc11sio_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_SCCR1, 1);
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m68hc11sio_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_SCCR2, 1);
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cpu->ios[M6811_SCSR] = M6811_TC | M6811_TDRE;
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controller->rx_char = 0;
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controller->tx_char = 0;
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controller->tx_has_char = 0;
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controller->rx_clear_scsr = 0;
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if (controller->rx_poll_event)
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{
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hw_event_queue_deschedule (me, controller->rx_poll_event);
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controller->rx_poll_event = 0;
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}
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if (controller->tx_poll_event)
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{
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hw_event_queue_deschedule (me, controller->tx_poll_event);
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controller->tx_poll_event = 0;
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}
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/* In bootstrap mode, initialize the SCI to 1200 bauds to
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simulate some initial setup by the internal rom. */
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if (((cpu->ios[M6811_HPRIO]) & (M6811_SMOD | M6811_MDA)) == M6811_SMOD)
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{
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unsigned char val = 0x33;
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m68hc11sio_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_BAUD, 1);
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val = 0x12;
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m68hc11sio_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_SCCR2, 1);
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}
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break;
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}
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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}
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}
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static void
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m68hc11sio_rx_poll (struct hw *me, void *data)
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{
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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char cc;
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int cnt;
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int check_interrupt = 0;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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switch (controller->backend)
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{
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case sio_tcp:
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cnt = dv_sockser_read (sd);
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if (cnt != -1)
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{
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cc = (char) cnt;
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cnt = 1;
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}
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break;
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case sio_stdio:
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cnt = sim_io_poll_read (sd, 0 /* stdin */, &cc, 1);
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break;
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default:
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cnt = 0;
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break;
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}
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if (cnt == 1)
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{
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/* Raise the overrun flag if the previous character was not read. */
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if (cpu->ios[M6811_SCSR] & M6811_RDRF)
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cpu->ios[M6811_SCSR] |= M6811_OR;
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cpu->ios[M6811_SCSR] |= M6811_RDRF;
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controller->rx_char = cc;
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controller->rx_clear_scsr = 0;
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check_interrupt = 1;
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}
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else
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{
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/* handle idle line detect here. */
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;
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}
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if (controller->rx_poll_event)
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{
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hw_event_queue_deschedule (me, controller->rx_poll_event);
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controller->rx_poll_event = 0;
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}
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if (cpu->ios[M6811_SCCR2] & M6811_RE)
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{
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unsigned long clock_cycle;
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/* Compute CPU clock cycles to wait for the next character. */
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clock_cycle = controller->data_length * controller->baud_cycle;
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controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
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m68hc11sio_rx_poll,
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NULL);
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}
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if (check_interrupt)
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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static void
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m68hc11sio_tx_poll (struct hw *me, void *data)
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{
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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cpu->ios[M6811_SCSR] |= M6811_TDRE;
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cpu->ios[M6811_SCSR] |= M6811_TC;
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/* Transmitter is enabled and we have something to send. */
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if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char)
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{
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cpu->ios[M6811_SCSR] &= ~M6811_TDRE;
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cpu->ios[M6811_SCSR] &= ~M6811_TC;
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controller->tx_has_char = 0;
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switch (controller->backend)
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{
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case sio_tcp:
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dv_sockser_write (sd, controller->tx_char);
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break;
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case sio_stdio:
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sim_io_write_stdout (sd, &controller->tx_char, 1);
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sim_io_flush_stdout (sd);
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break;
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default:
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break;
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}
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}
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if (controller->tx_poll_event)
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{
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hw_event_queue_deschedule (me, controller->tx_poll_event);
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controller->tx_poll_event = 0;
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}
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if ((cpu->ios[M6811_SCCR2] & M6811_TE)
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&& ((cpu->ios[M6811_SCSR] & M6811_TC) == 0))
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{
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unsigned long clock_cycle;
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/* Compute CPU clock cycles to wait for the next character. */
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clock_cycle = controller->data_length * controller->baud_cycle;
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controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle,
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m68hc11sio_tx_poll,
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NULL);
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}
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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/* Descriptions of the SIO I/O ports. These descriptions are only used to
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give information of the SIO device under GDB. */
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io_reg_desc sccr2_desc[] = {
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{ M6811_TIE, "TIE ", "Transmit Interrupt Enable" },
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{ M6811_TCIE, "TCIE ", "Transmit Complete Interrupt Enable" },
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{ M6811_RIE, "RIE ", "Receive Interrupt Enable" },
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{ M6811_ILIE, "ILIE ", "Idle Line Interrupt Enable" },
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{ M6811_TE, "TE ", "Transmit Enable" },
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{ M6811_RE, "RE ", "Receive Enable" },
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{ M6811_RWU, "RWU ", "Receiver Wake Up" },
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{ M6811_SBK, "SBRK ", "Send Break" },
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{ 0, 0, 0 }
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};
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io_reg_desc sccr1_desc[] = {
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{ M6811_R8, "R8 ", "Receive Data bit 8" },
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{ M6811_T8, "T8 ", "Transmit Data bit 8" },
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{ M6811_M, "M ", "SCI Character length (0=8-bits, 1=9-bits)" },
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{ M6811_WAKE, "WAKE ", "Wake up method select (0=idle, 1=addr mark" },
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{ 0, 0, 0 }
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};
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io_reg_desc scsr_desc[] = {
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{ M6811_TDRE, "TDRE ", "Transmit Data Register Empty" },
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{ M6811_TC, "TC ", "Transmit Complete" },
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{ M6811_RDRF, "RDRF ", "Receive Data Register Full" },
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{ M6811_IDLE, "IDLE ", "Idle Line Detect" },
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{ M6811_OR, "OR ", "Overrun Error" },
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{ M6811_NF, "NF ", "Noise Flag" },
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{ M6811_FE, "FE ", "Framing Error" },
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{ 0, 0, 0 }
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};
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io_reg_desc baud_desc[] = {
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{ M6811_TCLR, "TCLR ", "Clear baud rate (test mode)" },
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{ M6811_SCP1, "SCP1 ", "SCI baud rate prescaler select (SCP1)" },
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{ M6811_SCP0, "SCP0 ", "SCI baud rate prescaler select (SCP0)" },
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{ M6811_RCKB, "RCKB ", "Baur Rate Clock Check (test mode)" },
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{ M6811_SCR2, "SCR2 ", "SCI Baud rate select (SCR2)" },
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{ M6811_SCR1, "SCR1 ", "SCI Baud rate select (SCR1)" },
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{ M6811_SCR0, "SCR0 ", "SCI Baud rate select (SCR0)" },
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{ 0, 0, 0 }
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};
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static void
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m68hc11sio_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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sim_cpu *cpu;
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struct m68hc11sio *controller;
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uint8 val;
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long clock_cycle;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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sim_io_printf (sd, "M68HC11 SIO:\n");
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base = cpu_get_io_base (cpu);
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val = cpu->ios[M6811_BAUD];
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print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD);
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sim_io_printf (sd, " (%ld baud)\n",
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(cpu->cpu_frequency / 4) / controller->baud_cycle);
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val = cpu->ios[M6811_SCCR1];
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print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1);
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sim_io_printf (sd, " (%d bits) (%dN1)\n",
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controller->data_length, controller->data_length - 2);
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val = cpu->ios[M6811_SCCR2];
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print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2);
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sim_io_printf (sd, "\n");
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val = cpu->ios[M6811_SCSR];
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print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR);
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sim_io_printf (sd, "\n");
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clock_cycle = controller->data_length * controller->baud_cycle;
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if (controller->tx_poll_event)
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{
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signed64 t;
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int n;
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t = hw_event_remain_time (me, controller->tx_poll_event);
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n = (clock_cycle - t) / controller->baud_cycle;
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n = controller->data_length - n;
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sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n",
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cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE),
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n, (n > 1 ? "s" : ""));
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}
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if (controller->rx_poll_event)
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{
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signed64 t;
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t = hw_event_remain_time (me, controller->rx_poll_event);
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sim_io_printf (sd, " Receive finished in %s\n",
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cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
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}
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}
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static int
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m68hc11sio_ioctl (struct hw *me,
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hw_ioctl_request request,
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va_list ap)
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{
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m68hc11sio_info (me);
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return 0;
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}
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/* generic read/write */
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static unsigned
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m68hc11sio_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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SIM_DESC sd;
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struct m68hc11sio *controller;
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sim_cpu *cpu;
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unsigned8 val;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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switch (base)
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{
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case M6811_SCSR:
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controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
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& (M6811_RDRF | M6811_IDLE | M6811_OR | M6811_NF | M6811_FE);
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case M6811_BAUD:
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case M6811_SCCR1:
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case M6811_SCCR2:
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val = cpu->ios[base];
|
|
break;
|
|
|
|
case M6811_SCDR:
|
|
if (controller->rx_clear_scsr)
|
|
{
|
|
cpu->ios[M6811_SCSR] &= ~controller->rx_clear_scsr;
|
|
}
|
|
val = controller->rx_char;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
*((unsigned8*) dest) = val;
|
|
return 1;
|
|
}
|
|
|
|
static unsigned
|
|
m68hc11sio_io_write_buffer (struct hw *me,
|
|
const void *source,
|
|
int space,
|
|
unsigned_word base,
|
|
unsigned nr_bytes)
|
|
{
|
|
SIM_DESC sd;
|
|
struct m68hc11sio *controller;
|
|
sim_cpu *cpu;
|
|
unsigned8 val;
|
|
|
|
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
|
|
|
|
sd = hw_system (me);
|
|
cpu = STATE_CPU (sd, 0);
|
|
controller = hw_data (me);
|
|
|
|
val = *((const unsigned8*) source);
|
|
switch (base)
|
|
{
|
|
case M6811_BAUD:
|
|
{
|
|
long divisor;
|
|
long baud;
|
|
|
|
cpu->ios[M6811_BAUD] = val;
|
|
switch (val & (M6811_SCP1|M6811_SCP0))
|
|
{
|
|
case M6811_BAUD_DIV_1:
|
|
divisor = 1 * 16;
|
|
break;
|
|
|
|
case M6811_BAUD_DIV_3:
|
|
divisor = 3 * 16;
|
|
break;
|
|
|
|
case M6811_BAUD_DIV_4:
|
|
divisor = 4 * 16;
|
|
break;
|
|
|
|
default:
|
|
case M6811_BAUD_DIV_13:
|
|
divisor = 13 * 16;
|
|
break;
|
|
}
|
|
val &= (M6811_SCR2|M6811_SCR1|M6811_SCR0);
|
|
divisor *= (1 << val);
|
|
|
|
baud = (cpu->cpu_frequency / 4) / divisor;
|
|
|
|
HW_TRACE ((me, "divide rate %ld, baud rate %ld",
|
|
divisor, baud));
|
|
|
|
controller->baud_cycle = divisor;
|
|
}
|
|
break;
|
|
|
|
case M6811_SCCR1:
|
|
{
|
|
if (val & M6811_M)
|
|
controller->data_length = 11;
|
|
else
|
|
controller->data_length = 10;
|
|
|
|
cpu->ios[M6811_SCCR1] = val;
|
|
}
|
|
break;
|
|
|
|
case M6811_SCCR2:
|
|
if ((val & M6811_RE) == 0)
|
|
{
|
|
val &= ~(M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF);
|
|
val |= (cpu->ios[M6811_SCCR2]
|
|
& (M6811_RDRF|M6811_IDLE|M6811_OR|M6811_NF|M6811_NF));
|
|
cpu->ios[M6811_SCCR2] = val;
|
|
break;
|
|
}
|
|
|
|
/* Activate reception. */
|
|
if (controller->rx_poll_event == 0)
|
|
{
|
|
long clock_cycle;
|
|
|
|
/* Compute CPU clock cycles to wait for the next character. */
|
|
clock_cycle = controller->data_length * controller->baud_cycle;
|
|
|
|
controller->rx_poll_event = hw_event_queue_schedule (me, clock_cycle,
|
|
m68hc11sio_rx_poll,
|
|
NULL);
|
|
}
|
|
cpu->ios[M6811_SCCR2] = val;
|
|
interrupts_update_pending (&cpu->cpu_interrupts);
|
|
break;
|
|
|
|
/* No effect. */
|
|
case M6811_SCSR:
|
|
return 1;
|
|
|
|
case M6811_SCDR:
|
|
if (!(cpu->ios[M6811_SCSR] & M6811_TDRE))
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
controller->tx_char = val;
|
|
controller->tx_has_char = 1;
|
|
if ((cpu->ios[M6811_SCCR2] & M6811_TE)
|
|
&& controller->tx_poll_event == 0)
|
|
{
|
|
m68hc11sio_tx_poll (me, NULL);
|
|
}
|
|
return 1;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
return nr_bytes;
|
|
}
|
|
|
|
|
|
const struct hw_descriptor dv_m68hc11sio_descriptor[] = {
|
|
{ "m68hc11sio", m68hc11sio_finish },
|
|
{ "m68hc12sio", m68hc11sio_finish },
|
|
{ NULL },
|
|
};
|
|
|