820 lines
22 KiB
C
820 lines
22 KiB
C
/* Blackfin Core Event Controller (CEC) model.
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Copyright (C) 2010-2019 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_cec.h"
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#include "dv-bfin_evt.h"
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#include "dv-bfin_mmu.h"
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struct bfin_cec
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{
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bu32 base;
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SIM_CPU *cpu;
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struct hw *me;
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struct hw_event *pending;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 evt_override, imask, ipend, ilat, iprio;
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};
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#define mmr_base() offsetof(struct bfin_cec, evt_override)
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#define mmr_offset(mmr) (offsetof(struct bfin_cec, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"EVT_OVERRIDE", "IMASK", "IPEND", "ILAT", "IPRIO",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static void _cec_raise (SIM_CPU *, struct bfin_cec *, int);
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static void
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bfin_cec_hw_event_callback (struct hw *me, void *data)
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{
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struct bfin_cec *cec = data;
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hw_event_queue_deschedule (me, cec->pending);
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_cec_raise (cec->cpu, cec, -1);
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cec->pending = NULL;
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}
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static void
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bfin_cec_check_pending (struct hw *me, struct bfin_cec *cec)
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{
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if (cec->pending)
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return;
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cec->pending = hw_event_queue_schedule (me, 0, bfin_cec_hw_event_callback, cec);
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}
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static void
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_cec_check_pending (SIM_CPU *cpu, struct bfin_cec *cec)
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{
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bfin_cec_check_pending (cec->me, cec);
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}
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static void
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_cec_imask_write (struct bfin_cec *cec, bu32 value)
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{
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cec->imask = (value & IVG_MASKABLE_B) | (cec->imask & IVG_UNMASKABLE_B);
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}
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static unsigned
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bfin_cec_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_cec *cec = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_4 (source);
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mmr_off = addr - cec->base;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(evt_override):
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cec->evt_override = value;
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break;
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case mmr_offset(imask):
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_cec_imask_write (cec, value);
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bfin_cec_check_pending (me, cec);
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break;
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case mmr_offset(ipend):
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/* Read-only register. */
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break;
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case mmr_offset(ilat):
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dv_w1c_4 (&cec->ilat, value, 0xffee);
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break;
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case mmr_offset(iprio):
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cec->iprio = (value & IVG_UNMASKABLE_B);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_cec_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_cec *cec = hw_data (me);
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bu32 mmr_off;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - cec->base;
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valuep = (void *)((unsigned long)cec + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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dv_store_4 (dest, *valuep);
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_cec_ports[] =
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{
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{ "emu", IVG_EMU, 0, input_port, },
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{ "rst", IVG_RST, 0, input_port, },
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{ "nmi", IVG_NMI, 0, input_port, },
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{ "evx", IVG_EVX, 0, input_port, },
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{ "ivhw", IVG_IVHW, 0, input_port, },
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{ "ivtmr", IVG_IVTMR, 0, input_port, },
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{ "ivg7", IVG7, 0, input_port, },
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{ "ivg8", IVG8, 0, input_port, },
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{ "ivg9", IVG9, 0, input_port, },
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{ "ivg10", IVG10, 0, input_port, },
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{ "ivg11", IVG11, 0, input_port, },
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{ "ivg12", IVG12, 0, input_port, },
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{ "ivg13", IVG13, 0, input_port, },
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{ "ivg14", IVG14, 0, input_port, },
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{ "ivg15", IVG15, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_cec_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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struct bfin_cec *cec = hw_data (me);
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_cec_raise (cec->cpu, cec, my_port);
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}
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static void
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attach_bfin_cec_regs (struct hw *me, struct bfin_cec *cec)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_CEC_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CEC_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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cec->base = attach_address;
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/* XXX: should take from the device tree. */
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cec->cpu = STATE_CPU (hw_system (me), 0);
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cec->me = me;
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}
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static void
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bfin_cec_finish (struct hw *me)
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{
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struct bfin_cec *cec;
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cec = HW_ZALLOC (me, struct bfin_cec);
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set_hw_data (me, cec);
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set_hw_io_read_buffer (me, bfin_cec_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_cec_io_write_buffer);
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set_hw_ports (me, bfin_cec_ports);
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set_hw_port_event (me, bfin_cec_port_event);
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attach_bfin_cec_regs (me, cec);
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/* Initialize the CEC. */
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cec->imask = IVG_UNMASKABLE_B;
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cec->ipend = IVG_RST_B | IVG_IRPTEN_B;
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}
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const struct hw_descriptor dv_bfin_cec_descriptor[] =
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{
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{"bfin_cec", bfin_cec_finish,},
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{NULL, NULL},
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};
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static const char * const excp_decoded[] =
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{
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[VEC_SYS ] = "Custom exception 0 (system call)",
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[VEC_EXCPT01 ] = "Custom exception 1 (software breakpoint)",
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[VEC_EXCPT02 ] = "Custom exception 2 (KGDB hook)",
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[VEC_EXCPT03 ] = "Custom exception 3 (userspace stack overflow)",
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[VEC_EXCPT04 ] = "Custom exception 4 (dump trace buffer)",
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[VEC_EXCPT05 ] = "Custom exception 5",
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[VEC_EXCPT06 ] = "Custom exception 6",
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[VEC_EXCPT07 ] = "Custom exception 7",
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[VEC_EXCPT08 ] = "Custom exception 8",
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[VEC_EXCPT09 ] = "Custom exception 9",
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[VEC_EXCPT10 ] = "Custom exception 10",
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[VEC_EXCPT11 ] = "Custom exception 11",
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[VEC_EXCPT12 ] = "Custom exception 12",
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[VEC_EXCPT13 ] = "Custom exception 13",
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[VEC_EXCPT14 ] = "Custom exception 14",
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[VEC_EXCPT15 ] = "Custom exception 15",
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[VEC_STEP ] = "Hardware single step",
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[VEC_OVFLOW ] = "Trace buffer overflow",
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[VEC_UNDEF_I ] = "Undefined instruction",
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[VEC_ILGAL_I ] = "Illegal instruction combo (multi-issue)",
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[VEC_CPLB_VL ] = "DCPLB protection violation",
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[VEC_MISALI_D ] = "Unaligned data access",
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[VEC_UNCOV ] = "Unrecoverable event (double fault)",
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[VEC_CPLB_M ] = "DCPLB miss",
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[VEC_CPLB_MHIT ] = "Multiple DCPLB hit",
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[VEC_WATCH ] = "Watchpoint match",
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[VEC_ISTRU_VL ] = "ADSP-BF535 only",
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[VEC_MISALI_I ] = "Unaligned instruction access",
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[VEC_CPLB_I_VL ] = "ICPLB protection violation",
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[VEC_CPLB_I_M ] = "ICPLB miss",
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[VEC_CPLB_I_MHIT] = "Multiple ICPLB hit",
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[VEC_ILL_RES ] = "Illegal supervisor resource",
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};
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#define CEC_STATE(cpu) DV_STATE_CACHED (cpu, cec)
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#define __cec_get_ivg(val) (ffs ((val) & ~IVG_IRPTEN_B) - 1)
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#define _cec_get_ivg(cec) __cec_get_ivg ((cec)->ipend & ~IVG_EMU_B)
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int
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cec_get_ivg (SIM_CPU *cpu)
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{
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switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
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{
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case OPERATING_ENVIRONMENT:
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return _cec_get_ivg (CEC_STATE (cpu));
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default:
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return IVG_USER;
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}
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}
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static bool
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_cec_is_supervisor_mode (struct bfin_cec *cec)
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{
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return (cec->ipend & ~(IVG_EMU_B | IVG_IRPTEN_B));
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}
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bool
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cec_is_supervisor_mode (SIM_CPU *cpu)
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{
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switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
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{
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case OPERATING_ENVIRONMENT:
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return _cec_is_supervisor_mode (CEC_STATE (cpu));
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case USER_ENVIRONMENT:
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return false;
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default:
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return true;
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}
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}
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static bool
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_cec_is_user_mode (struct bfin_cec *cec)
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{
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return !_cec_is_supervisor_mode (cec);
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}
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bool
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cec_is_user_mode (SIM_CPU *cpu)
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{
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return !cec_is_supervisor_mode (cpu);
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}
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static void
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_cec_require_supervisor (SIM_CPU *cpu, struct bfin_cec *cec)
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{
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if (_cec_is_user_mode (cec))
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cec_exception (cpu, VEC_ILL_RES);
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}
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void
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cec_require_supervisor (SIM_CPU *cpu)
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{
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/* Do not call _cec_require_supervisor() to avoid CEC_STATE()
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as that macro requires OS operating mode. */
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if (cec_is_user_mode (cpu))
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cec_exception (cpu, VEC_ILL_RES);
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}
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#define excp_to_sim_halt(reason, sigrc) \
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sim_engine_halt (CPU_STATE (cpu), cpu, NULL, PCREG, reason, sigrc)
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void
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cec_exception (SIM_CPU *cpu, int excp)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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int sigrc = -1;
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TRACE_EVENTS (cpu, "processing exception %#x in EVT%i", excp,
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cec_get_ivg (cpu));
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/* Ideally what would happen here for real hardware exceptions (not
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fake sim ones) is that:
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- For service exceptions (excp <= 0x11):
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RETX is the _next_ PC which can be tricky with jumps/hardware loops/...
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- For error exceptions (excp > 0x11):
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RETX is the _current_ PC (i.e. the one causing the exception)
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- PC is loaded with EVT3 MMR
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- ILAT/IPEND in CEC is updated depending on current IVG level
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- the fault address MMRs get updated with data/instruction info
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- Execution continues on in the EVT3 handler */
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/* Handle simulator exceptions first. */
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switch (excp)
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{
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case VEC_SIM_HLT:
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excp_to_sim_halt (sim_exited, 0);
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return;
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case VEC_SIM_ABORT:
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excp_to_sim_halt (sim_exited, 1);
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return;
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case VEC_SIM_TRAP:
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/* GDB expects us to step over EMUEXCPT. */
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/* XXX: What about hwloops and EMUEXCPT at the end?
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Pretty sure gdb doesn't handle this already... */
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SET_PCREG (PCREG + 2);
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/* Only trap when we are running in gdb. */
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if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
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excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
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return;
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case VEC_SIM_DBGA:
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/* If running in gdb, simply trap. */
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if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
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excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
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else
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excp_to_sim_halt (sim_exited, 2);
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}
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if (excp <= 0x3f)
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{
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SET_EXCAUSE (excp);
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if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
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{
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/* ICPLB regs always get updated. */
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/* XXX: Should optimize this call path ... */
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if (excp != VEC_MISALI_I && excp != VEC_MISALI_D
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&& excp != VEC_CPLB_I_M && excp != VEC_CPLB_M
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&& excp != VEC_CPLB_I_VL && excp != VEC_CPLB_VL
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&& excp != VEC_CPLB_I_MHIT && excp != VEC_CPLB_MHIT)
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mmu_log_ifault (cpu);
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_cec_raise (cpu, CEC_STATE (cpu), IVG_EVX);
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/* We need to restart the engine so that we don't return
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and continue processing this bad insn. */
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if (EXCAUSE >= 0x20)
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sim_engine_restart (sd, cpu, NULL, PCREG);
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return;
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}
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}
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TRACE_EVENTS (cpu, "running virtual exception handler");
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switch (excp)
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{
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case VEC_SYS:
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bfin_syscall (cpu);
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break;
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case VEC_EXCPT01: /* Userspace gdb breakpoint. */
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sigrc = SIM_SIGTRAP;
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break;
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case VEC_UNDEF_I: /* Undefined instruction. */
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sigrc = SIM_SIGILL;
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break;
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case VEC_ILL_RES: /* Illegal supervisor resource. */
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case VEC_MISALI_I: /* Misaligned instruction. */
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sigrc = SIM_SIGBUS;
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break;
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case VEC_CPLB_M:
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case VEC_CPLB_I_M:
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sigrc = SIM_SIGSEGV;
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break;
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default:
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sim_io_eprintf (sd, "Unhandled exception %#x at 0x%08x (%s)\n",
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excp, PCREG, excp_decoded[excp]);
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sigrc = SIM_SIGILL;
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break;
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}
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if (sigrc != -1)
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excp_to_sim_halt (sim_stopped, sigrc);
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}
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bu32 cec_cli (SIM_CPU *cpu)
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{
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struct bfin_cec *cec;
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bu32 old_mask;
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if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
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return 0;
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cec = CEC_STATE (cpu);
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_cec_require_supervisor (cpu, cec);
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/* XXX: what about IPEND[4] ? */
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old_mask = cec->imask;
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_cec_imask_write (cec, 0);
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TRACE_EVENTS (cpu, "CLI changed IMASK from %#x to %#x", old_mask, cec->imask);
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return old_mask;
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}
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void cec_sti (SIM_CPU *cpu, bu32 ints)
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{
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struct bfin_cec *cec;
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bu32 old_mask;
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if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
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return;
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cec = CEC_STATE (cpu);
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_cec_require_supervisor (cpu, cec);
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/* XXX: what about IPEND[4] ? */
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old_mask = cec->imask;
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_cec_imask_write (cec, ints);
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TRACE_EVENTS (cpu, "STI changed IMASK from %#x to %#x", old_mask, cec->imask);
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/* Check for pending interrupts that are now enabled. */
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_cec_check_pending (cpu, cec);
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}
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static void
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cec_irpten_enable (SIM_CPU *cpu, struct bfin_cec *cec)
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{
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/* Globally mask interrupts. */
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TRACE_EVENTS (cpu, "setting IPEND[4] to globally mask interrupts");
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cec->ipend |= IVG_IRPTEN_B;
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}
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static void
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cec_irpten_disable (SIM_CPU *cpu, struct bfin_cec *cec)
|
|
{
|
|
/* Clear global interrupt mask. */
|
|
TRACE_EVENTS (cpu, "clearing IPEND[4] to not globally mask interrupts");
|
|
cec->ipend &= ~IVG_IRPTEN_B;
|
|
}
|
|
|
|
static void
|
|
_cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
|
|
{
|
|
SIM_DESC sd = CPU_STATE (cpu);
|
|
int curr_ivg = _cec_get_ivg (cec);
|
|
bool snen;
|
|
bool irpten;
|
|
|
|
TRACE_EVENTS (cpu, "processing request for EVT%i while at EVT%i",
|
|
ivg, curr_ivg);
|
|
|
|
irpten = (cec->ipend & IVG_IRPTEN_B);
|
|
snen = (SYSCFGREG & SYSCFG_SNEN);
|
|
|
|
if (curr_ivg == -1)
|
|
curr_ivg = IVG_USER;
|
|
|
|
/* Just check for higher latched interrupts. */
|
|
if (ivg == -1)
|
|
{
|
|
if (irpten)
|
|
goto done; /* All interrupts are masked anyways. */
|
|
|
|
ivg = __cec_get_ivg (cec->ilat & cec->imask);
|
|
if (ivg < 0)
|
|
goto done; /* Nothing latched. */
|
|
|
|
if (ivg > curr_ivg)
|
|
goto done; /* Nothing higher latched. */
|
|
|
|
if (!snen && ivg == curr_ivg)
|
|
goto done; /* Self nesting disabled. */
|
|
|
|
/* Still here, so fall through to raise to higher pending. */
|
|
}
|
|
|
|
cec->ilat |= (1 << ivg);
|
|
|
|
if (ivg <= IVG_EVX)
|
|
{
|
|
/* These two are always processed. */
|
|
if (ivg == IVG_EMU || ivg == IVG_RST)
|
|
goto process_int;
|
|
|
|
/* Anything lower might trigger a double fault. */
|
|
if (curr_ivg <= ivg)
|
|
{
|
|
/* Double fault ! :( */
|
|
SET_EXCAUSE (VEC_UNCOV);
|
|
/* XXX: SET_RETXREG (...); */
|
|
sim_io_error (sd, "%s: double fault at 0x%08x ! :(", __func__, PCREG);
|
|
excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
|
|
}
|
|
|
|
/* No double fault -> always process. */
|
|
goto process_int;
|
|
}
|
|
else if (irpten && curr_ivg != IVG_USER)
|
|
{
|
|
/* Interrupts are globally masked. */
|
|
}
|
|
else if (!(cec->imask & (1 << ivg)))
|
|
{
|
|
/* This interrupt is masked. */
|
|
}
|
|
else if (ivg < curr_ivg || (snen && ivg == curr_ivg))
|
|
{
|
|
/* Do transition! */
|
|
bu32 oldpc;
|
|
|
|
process_int:
|
|
cec->ipend |= (1 << ivg);
|
|
cec->ilat &= ~(1 << ivg);
|
|
|
|
/* Interrupts are processed in between insns which means the return
|
|
point is the insn-to-be-executed (which is the current PC). But
|
|
exceptions are handled while executing an insn, so we may have to
|
|
advance the PC ourselves when setting RETX.
|
|
XXX: Advancing the PC should only be for "service" exceptions, and
|
|
handling them after executing the insn should be OK, which
|
|
means we might be able to use the event interface for it. */
|
|
|
|
oldpc = PCREG;
|
|
switch (ivg)
|
|
{
|
|
case IVG_EMU:
|
|
/* Signal the JTAG ICE. */
|
|
/* XXX: what happens with 'raise 0' ? */
|
|
SET_RETEREG (oldpc);
|
|
excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
|
|
/* XXX: Need an easy way for gdb to signal it isnt here. */
|
|
cec->ipend &= ~IVG_EMU_B;
|
|
break;
|
|
case IVG_RST:
|
|
/* Have the core reset simply exit (i.e. "shutdown"). */
|
|
excp_to_sim_halt (sim_exited, 0);
|
|
break;
|
|
case IVG_NMI:
|
|
/* XXX: Should check this. */
|
|
SET_RETNREG (oldpc);
|
|
break;
|
|
case IVG_EVX:
|
|
/* Non-service exceptions point to the excepting instruction. */
|
|
if (EXCAUSE >= 0x20)
|
|
SET_RETXREG (oldpc);
|
|
else
|
|
{
|
|
bu32 nextpc = hwloop_get_next_pc (cpu, oldpc, INSN_LEN);
|
|
SET_RETXREG (nextpc);
|
|
}
|
|
|
|
break;
|
|
case IVG_IRPTEN:
|
|
/* XXX: what happens with 'raise 4' ? */
|
|
sim_io_error (sd, "%s: what to do with 'raise 4' ?", __func__);
|
|
break;
|
|
default:
|
|
SET_RETIREG (oldpc | (ivg == curr_ivg ? 1 : 0));
|
|
break;
|
|
}
|
|
|
|
/* If EVT_OVERRIDE is in effect (IVG7+), use the reset address. */
|
|
if ((cec->evt_override & 0xff80) & (1 << ivg))
|
|
SET_PCREG (cec_get_reset_evt (cpu));
|
|
else
|
|
SET_PCREG (cec_get_evt (cpu, ivg));
|
|
|
|
BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (to EVT%i):", ivg);
|
|
BFIN_CPU_STATE.did_jump = true;
|
|
|
|
/* Enable the global interrupt mask upon interrupt entry. */
|
|
if (ivg >= IVG_IVHW)
|
|
cec_irpten_enable (cpu, cec);
|
|
}
|
|
|
|
/* When moving between states, don't let internal states bleed through. */
|
|
DIS_ALGN_EXPT &= ~1;
|
|
|
|
/* When going from user to super, we set LSB in LB regs to avoid
|
|
misbehavior and/or malicious code.
|
|
Also need to load SP alias with KSP. */
|
|
if (curr_ivg == IVG_USER)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 2; ++i)
|
|
if (!(LBREG (i) & 1))
|
|
SET_LBREG (i, LBREG (i) | 1);
|
|
SET_USPREG (SPREG);
|
|
SET_SPREG (KSPREG);
|
|
}
|
|
|
|
done:
|
|
TRACE_EVENTS (cpu, "now at EVT%i", _cec_get_ivg (cec));
|
|
}
|
|
|
|
static bu32
|
|
cec_read_ret_reg (SIM_CPU *cpu, int ivg)
|
|
{
|
|
switch (ivg)
|
|
{
|
|
case IVG_EMU: return RETEREG;
|
|
case IVG_NMI: return RETNREG;
|
|
case IVG_EVX: return RETXREG;
|
|
default: return RETIREG;
|
|
}
|
|
}
|
|
|
|
void
|
|
cec_latch (SIM_CPU *cpu, int ivg)
|
|
{
|
|
struct bfin_cec *cec;
|
|
|
|
if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
|
|
{
|
|
bu32 oldpc = PCREG;
|
|
SET_PCREG (cec_read_ret_reg (cpu, ivg));
|
|
BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
|
|
return;
|
|
}
|
|
|
|
cec = CEC_STATE (cpu);
|
|
cec->ilat |= (1 << ivg);
|
|
_cec_check_pending (cpu, cec);
|
|
}
|
|
|
|
void
|
|
cec_hwerr (SIM_CPU *cpu, int hwerr)
|
|
{
|
|
SET_HWERRCAUSE (hwerr);
|
|
cec_latch (cpu, IVG_IVHW);
|
|
}
|
|
|
|
void
|
|
cec_return (SIM_CPU *cpu, int ivg)
|
|
{
|
|
SIM_DESC sd = CPU_STATE (cpu);
|
|
struct bfin_cec *cec;
|
|
bool snen;
|
|
int curr_ivg;
|
|
bu32 oldpc, newpc;
|
|
|
|
oldpc = PCREG;
|
|
|
|
BFIN_CPU_STATE.did_jump = true;
|
|
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
|
|
{
|
|
SET_PCREG (cec_read_ret_reg (cpu, ivg));
|
|
BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
|
|
return;
|
|
}
|
|
|
|
cec = CEC_STATE (cpu);
|
|
|
|
/* XXX: This isn't entirely correct ... */
|
|
cec->ipend &= ~IVG_EMU_B;
|
|
|
|
curr_ivg = _cec_get_ivg (cec);
|
|
if (curr_ivg == -1)
|
|
curr_ivg = IVG_USER;
|
|
if (ivg == -1)
|
|
ivg = curr_ivg;
|
|
|
|
TRACE_EVENTS (cpu, "returning from EVT%i (should be EVT%i)", curr_ivg, ivg);
|
|
|
|
/* Not allowed to return from usermode. */
|
|
if (curr_ivg == IVG_USER)
|
|
cec_exception (cpu, VEC_ILL_RES);
|
|
|
|
if (ivg > IVG15 || ivg < 0)
|
|
sim_io_error (sd, "%s: ivg %i out of range !", __func__, ivg);
|
|
|
|
_cec_require_supervisor (cpu, cec);
|
|
|
|
switch (ivg)
|
|
{
|
|
case IVG_EMU:
|
|
/* RTE -- only valid in emulation mode. */
|
|
/* XXX: What does the hardware do ? */
|
|
if (curr_ivg != IVG_EMU)
|
|
cec_exception (cpu, VEC_ILL_RES);
|
|
break;
|
|
case IVG_NMI:
|
|
/* RTN -- only valid in NMI. */
|
|
/* XXX: What does the hardware do ? */
|
|
if (curr_ivg != IVG_NMI)
|
|
cec_exception (cpu, VEC_ILL_RES);
|
|
break;
|
|
case IVG_EVX:
|
|
/* RTX -- only valid in exception. */
|
|
/* XXX: What does the hardware do ? */
|
|
if (curr_ivg != IVG_EVX)
|
|
cec_exception (cpu, VEC_ILL_RES);
|
|
break;
|
|
default:
|
|
/* RTI -- not valid in emulation, nmi, exception, or user. */
|
|
/* XXX: What does the hardware do ? */
|
|
if (curr_ivg == IVG_EMU || curr_ivg == IVG_NMI
|
|
|| curr_ivg == IVG_EVX || curr_ivg == IVG_USER)
|
|
cec_exception (cpu, VEC_ILL_RES);
|
|
break;
|
|
case IVG_IRPTEN:
|
|
/* XXX: Is this even possible ? */
|
|
excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
|
|
break;
|
|
}
|
|
newpc = cec_read_ret_reg (cpu, ivg);
|
|
|
|
/* XXX: Does this nested trick work on EMU/NMI/EVX ? */
|
|
snen = (newpc & 1);
|
|
/* XXX: Delayed clear shows bad PCREG register trace above ? */
|
|
SET_PCREG (newpc & ~1);
|
|
|
|
BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (from EVT%i)", ivg);
|
|
|
|
/* Update ipend after the BFIN_TRACE_BRANCH so dv-bfin_trace
|
|
knows current CEC state wrt overflow. */
|
|
if (!snen)
|
|
cec->ipend &= ~(1 << ivg);
|
|
|
|
/* Disable global interrupt mask to let any interrupt take over, but
|
|
only when we were already in a RTI level. Only way we could have
|
|
raised at that point is if it was cleared in the first place. */
|
|
if (ivg >= IVG_IVHW || ivg == IVG_RST)
|
|
cec_irpten_disable (cpu, cec);
|
|
|
|
/* When going from super to user, we clear LSB in LB regs in case
|
|
it was set on the transition up.
|
|
Also need to load SP alias with USP. */
|
|
if (_cec_get_ivg (cec) == -1)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 2; ++i)
|
|
if (LBREG (i) & 1)
|
|
SET_LBREG (i, LBREG (i) & ~1);
|
|
SET_KSPREG (SPREG);
|
|
SET_SPREG (USPREG);
|
|
}
|
|
|
|
/* Check for pending interrupts before we return to usermode. */
|
|
_cec_check_pending (cpu, cec);
|
|
}
|
|
|
|
void
|
|
cec_push_reti (SIM_CPU *cpu)
|
|
{
|
|
/* XXX: Need to check hardware with popped RETI value
|
|
and bit 1 is set (when handling nested interrupts).
|
|
Also need to check behavior wrt SNEN in SYSCFG. */
|
|
struct bfin_cec *cec;
|
|
|
|
if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
|
|
return;
|
|
|
|
TRACE_EVENTS (cpu, "pushing RETI");
|
|
|
|
cec = CEC_STATE (cpu);
|
|
cec_irpten_disable (cpu, cec);
|
|
/* Check for pending interrupts. */
|
|
_cec_check_pending (cpu, cec);
|
|
}
|
|
|
|
void
|
|
cec_pop_reti (SIM_CPU *cpu)
|
|
{
|
|
/* XXX: Need to check hardware with popped RETI value
|
|
and bit 1 is set (when handling nested interrupts).
|
|
Also need to check behavior wrt SNEN in SYSCFG. */
|
|
struct bfin_cec *cec;
|
|
|
|
if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
|
|
return;
|
|
|
|
TRACE_EVENTS (cpu, "popping RETI");
|
|
|
|
cec = CEC_STATE (cpu);
|
|
cec_irpten_enable (cpu, cec);
|
|
}
|