219 lines
5.4 KiB
C
219 lines
5.4 KiB
C
/* Blackfin Watchdog (WDOG) model.
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Copyright (C) 2010-2019 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "dv-sockser.h"
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#include "devices.h"
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#include "dv-bfin_wdog.h"
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/* XXX: Should we bother emulating the TX/RX FIFOs ? */
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struct bfin_wdog
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{
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bu32 base;
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(ctl);
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bu32 cnt, stat;
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};
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#define mmr_base() offsetof(struct bfin_wdog, ctl)
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#define mmr_offset(mmr) (offsetof(struct bfin_wdog, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"WDOG_CTL", "WDOG_CNT", "WDOG_STAT",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static bool
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bfin_wdog_enabled (struct bfin_wdog *wdog)
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{
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return ((wdog->ctl & WDEN) != WDDIS);
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}
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static unsigned
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bfin_wdog_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_wdog *wdog = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
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return 0;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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mmr_off = addr - wdog->base;
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valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(ctl):
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dv_w1c_2_partial (value16p, value, WDRO);
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/* XXX: Should enable an event here to handle timeouts. */
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break;
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case mmr_offset(cnt):
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/* Writes are discarded when enabeld. */
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if (!bfin_wdog_enabled (wdog))
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{
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*value32p = value;
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/* Writes to CNT preloads the STAT. */
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wdog->stat = wdog->cnt;
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}
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break;
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case mmr_offset(stat):
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/* When enabled, writes to STAT reload the counter. */
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if (bfin_wdog_enabled (wdog))
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wdog->stat = wdog->cnt;
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/* XXX: When disabled, are writes just ignored ? */
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_wdog_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_wdog *wdog = hw_data (me);
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bu32 mmr_off;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - wdog->base;
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valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(ctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16p);
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break;
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case mmr_offset(cnt):
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case mmr_offset(stat):
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dv_store_4 (dest, *value32p);
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break;
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}
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_wdog_ports[] =
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{
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{ "reset", WDEV_RESET, 0, output_port, },
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{ "nmi", WDEV_NMI, 0, output_port, },
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{ "gpi", WDEV_GPI, 0, output_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_wdog_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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struct bfin_wdog *wdog = hw_data (me);
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bu16 wdev;
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wdog->ctl |= WDRO;
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wdev = (wdog->ctl & WDEV);
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if (wdev != WDEV_NONE)
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hw_port_event (me, wdev, 1);
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}
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static void
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attach_bfin_wdog_regs (struct hw *me, struct bfin_wdog *wdog)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_WDOG_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_WDOG_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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wdog->base = attach_address;
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}
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static void
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bfin_wdog_finish (struct hw *me)
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{
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struct bfin_wdog *wdog;
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wdog = HW_ZALLOC (me, struct bfin_wdog);
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set_hw_data (me, wdog);
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set_hw_io_read_buffer (me, bfin_wdog_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_wdog_io_write_buffer);
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set_hw_ports (me, bfin_wdog_ports);
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set_hw_port_event (me, bfin_wdog_port_event);
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attach_bfin_wdog_regs (me, wdog);
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/* Initialize the Watchdog. */
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wdog->ctl = WDDIS;
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}
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const struct hw_descriptor dv_bfin_wdog_descriptor[] =
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{
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{"bfin_wdog", bfin_wdog_finish,},
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{NULL, NULL},
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};
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