1837 lines
61 KiB
Plaintext
1837 lines
61 KiB
Plaintext
2017-12-03 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (extract_li20): Rewrite.
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2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
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* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
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(operand_value_powerpc): Update return and argument type.
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<value, top>: Update type.
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(skip_optional_operands): Update argument type.
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(lookup_powerpc): Likewise.
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(lookup_vle): Likewise.
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<table_opcd, table_mask, insn2>: Update type.
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(lookup_spe2): Update argument type.
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<table_opcd, table_mask, insn2>: Update type.
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(print_insn_powerpc) <insn, value>: Update type.
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Use PPC_INT_FMT for printing instructions and operands.
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* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
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insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
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insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
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extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
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extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
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insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
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extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
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insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
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extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
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insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
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extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
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insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
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extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
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insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
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extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
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insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
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extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
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insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
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extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
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extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
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extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
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insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
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extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
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insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
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extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
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extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
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(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
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BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
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DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
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SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
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VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
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VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
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VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
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XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
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XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
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XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
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XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
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2017-11-29 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (active_cpu_flags, active_isstring, enum stage):
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New.
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(output_cpu_flags): Update active_cpu_flags.
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(process_i386_opcode_modifier): Update active_isstring.
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(output_operand_type): Rename "macro" parameter to "stage",
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changing its type.
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(process_i386_operand_type): Likewise. Track presence of
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BaseIndex and emit DispN accordingly.
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(output_i386_opcode, process_i386_registers,
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process_i386_initializers): Adjust calls to
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process_i386_operand_type() for its changed parameter type.
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* i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
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all insns operands having BaseIndex set.
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* i386-tbl.h: Re-generate.
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2017-11-29 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
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entry.
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(operand_types): Remove Vec_Disp8 entry.
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* i386-opc.h (Vec_Disp8): Delete.
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(union i386_operand_type): Remove vec_disp8.
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(i386-opc.tbl): Remove Vec_Disp8.
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* i386-init.h, i386-tbl.h: Re-generate.
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2017-11-29 Stefan Stroe <stroestefan@gmail.com>
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* po/Make-in (datadir): Define as @datadir@.
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(localedir): Define as @localedir@.
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(gnulocaledir, gettextsrcdir): Use @datarootdir@.
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2017-11-27 Nick Clifton <nickc@redhat.com>
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* po/zh_CN.po: Updated simplified Chinese translation.
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2017-11-24 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
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"df" groups.
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2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
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* i386-tbl.h: Regenerate.
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2017-11-23 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
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the 16-bit addressing case.
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2017-11-23 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
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(twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
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* i386-opc.tbl (ud1, ud2b): Add operands.
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(ud0): New.
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* i386-tbl.h: Re-generate.
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2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
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* i386-tbl.h: Regenerate.
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2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
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* i386-tbl.h: Regenerate.
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2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
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*arc-opc (insert_rhv2): Check h-regs range.
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2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
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* arc-opc.c (SIMM21_A16_5): Make it pc-relative.
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2017-11-16 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
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and AARCH64_FEATURE_F16.
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2017-11-16 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
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(rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
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(sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
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(fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
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(ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
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(ldapur, ldapursw, stlur): New.
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* aarch64-dis-2.c: Regenerate.
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2017-11-16 Jan Beulich <jbeulich@suse.com>
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(get_valid_dis386): Never flag bad opcode when
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vex.register_specifier is beyond 7. Always store all four
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bits of it. Move 16-/32-bit override in EVEX handling after
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all to be overridden bits have been set.
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(OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
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Use rex to determine GPR register set.
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(OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
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OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
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2017-11-15 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
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determine GPR register set.
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2017-11-15 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (VEXI4_Fixup, VexI4): Delete.
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(prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
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(OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
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pass.
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(OP_REG_VexI4): Drop low 4 bits check.
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2017-11-15 Jan Beulich <jbeulich@suse.com>
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* i386-reg.tbl (axl): Remove Acc and Byte.
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* i386-tbl.h: Re-generate.
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2017-11-14 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
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(vex_len_table): Use VPCOM.
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2017-11-14 Jan Beulich <jbeulich@suse.com>
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* i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
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(evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
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* i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
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vpcmpw): Move up.
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(vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
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vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
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vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
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vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
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vpcmpnltuw): New.
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* i386-tbl.h: Re-generate.
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2017-11-14 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
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smov, ssca, stos, ssto, xlat): Drop Disp*.
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* i386-tbl.h: Re-generate.
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2017-11-13 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
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xsaveopt64): Add No_qSuf.
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* i386-tbl.h: Re-generate.
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
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dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
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cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
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sder32_el2, vncr_el2.
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(aarch64_sys_reg_supported_p): Likewise.
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(aarch64_pstatefields): Add dit register.
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(aarch64_pstatefield_supported_p): Likewise.
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(aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
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vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
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vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
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rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
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rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
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ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
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rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
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(QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
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(QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
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(QL_STLW, QL_STLX): New.
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* aarch64-asm.h (ins_addr_offset): New.
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* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
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(aarch64_ins_addr_offset): New.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis.h (ext_addr_offset): New.
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* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
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(aarch64_ext_addr_offset): New.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
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FLD_imm4_2 and FLD_SM3_imm2.
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* aarch64-opc.c (fields): Add FLD_imm6_2,
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FLD_imm4_2 and FLD_SM3_imm2.
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(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
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(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
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AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
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* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
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* aarch64-tbl.h
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(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h
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(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
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(aarch64_feature_sm4, aarch64_feature_sha3): New.
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(aarch64_feature_fp_16_v8_2): New.
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(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
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(V8_4_INSN, CRYPTO_V8_2_INSN): New.
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(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
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2017-11-08 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
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(aarch64_feature_sha2, aarch64_feature_aes): New.
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(SHA2, AES): New.
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(AES_INSN, SHA2_INSN): New.
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(pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
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(sha1h, sha1su1, sha256su0, sha1c, sha1p,
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sha1m, sha1su0, sha256h, sha256h2, sha256su1):
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Change to SHA2_INS.
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2017-11-08 Jiong Wang <jiong.wang@arm.com>
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Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
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FP16 instructions, including vfmal.f16 and vfmsl.f16.
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2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
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2017-11-07 Alan Modra <amodra@gmail.com>
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* opintl.h: Formatting, comment fixes.
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(gettext, ngettext): Redefine when ENABLE_NLS.
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(ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
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(_): Define using gettext.
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(textdomain, bindtextdomain): Use safer "do nothing".
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2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (print_hex): New variable.
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(parse_option): Check for hex option.
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(print_insn_arc): Use hexadecimal representation for short
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immediate values when requested.
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(print_arc_disassembler_options): Add hex option to the list.
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2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
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(asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
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(cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
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(dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
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(dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
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(macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
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(macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
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(mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
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(msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
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(negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
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(sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
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(vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
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(vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
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(vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
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(vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
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(vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
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(vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
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||
(vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
|
||
(vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
|
||
Changed opcodes.
|
||
(prealloc, prefetch*): Place them before ld instruction.
|
||
* arc-opc.c (skip_this_opcode): Add ARITH class.
|
||
|
||
2017-10-25 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 22348
|
||
* cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
|
||
(cr16_words, cr16_allWords, processing_argument_number): Likewise.
|
||
(imm4flag, size_changed): Likewise.
|
||
* crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
|
||
(words, allWords, processing_argument_number): Likewise.
|
||
(cst4flag, size_changed): Likewise.
|
||
* crx-opc.c (crx_cst4_map): Rename from cst4_map.
|
||
(crx_cst4_maps): Rename from cst4_maps.
|
||
(crx_no_op_insn): Rename from no_op_insn.
|
||
|
||
2017-10-24 Andrew Waterman <andrew@sifive.com>
|
||
|
||
* riscv-opc.c (match_c_addi16sp) : New function.
|
||
(match_c_addi4spn): New function.
|
||
(match_c_lui): Don't allow 0-immediate encodings.
|
||
(riscv_opcodes) <addi>: Use the above functions.
|
||
<add>: Likewise.
|
||
<c.addi4spn>: Likewise.
|
||
<c.addi16sp>: Likewise.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-init.h: Regenerate
|
||
* i386-tbl.h: Likewise
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
|
||
(enum): Add EVEX_W_0F3854_P_2.
|
||
* i386-dis-evex.h (evex_table): Updated.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
|
||
CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
||
(cpu_flags): Add CpuAVX512_BITALG.
|
||
* i386-opc.h (enum): Add CpuAVX512_BITALG.
|
||
(i386_cpu_flags): Add cpuavx512_bitalg..
|
||
* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
|
||
* i386-dis-evex.h (evex_table): Updated.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
|
||
CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
||
(cpu_flags): Add CpuAVX512_VNNI.
|
||
* i386-opc.h (enum): Add CpuAVX512_VNNI.
|
||
(i386_cpu_flags): Add cpuavx512_vnni.
|
||
* i386-opc.tbl Add Intel AVX512_VNNI instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
|
||
(enum): Remove VEX_LEN_0F3A44_P_2.
|
||
(vex_len_table): Ditto.
|
||
(enum): Remove VEX_W_0F3A44_P_2.
|
||
(vew_w_table): Ditto.
|
||
(prefix_table): Adjust instructions (see prefixes above).
|
||
* i386-dis-evex.h (evex_table):
|
||
Add new instructions (see prefixes above).
|
||
* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
|
||
(bitfield_cpu_flags): Ditto.
|
||
* i386-opc.h (enum): Ditto.
|
||
(i386_cpu_flags): Ditto.
|
||
(CpuUnused): Comment out to avoid zero-width field problem.
|
||
* i386-opc.tbl (vpclmulqdq): New instruction.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Ditto.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
|
||
PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
|
||
(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
|
||
VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
|
||
(vex_len_table): Ditto.
|
||
(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
|
||
VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
|
||
(vew_w_table): Ditto.
|
||
(prefix_table): Adjust instructions (see prefixes above).
|
||
* i386-dis-evex.h (evex_table):
|
||
Add new instructions (see prefixes above).
|
||
* i386-gen.c (cpu_flag_init): Add VAES.
|
||
(bitfield_cpu_flags): Ditto.
|
||
* i386-opc.h (enum): Ditto.
|
||
(i386_cpu_flags): Ditto.
|
||
* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Ditto.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
|
||
PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
|
||
PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
|
||
(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
|
||
EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
|
||
(prefix_table): Updated (see prefixes above).
|
||
(three_byte_table): Likewise.
|
||
(vex_w_table): Likewise.
|
||
* i386-dis-evex.h: Likewise.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
|
||
(cpu_flags): Add CpuGFNI.
|
||
* i386-opc.h (enum): Add CpuGFNI.
|
||
(i386_cpu_flags): Add cpugfni.
|
||
* i386-opc.tbl: Add Intel GFNI instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
|
||
Define EXbScalar and EXwScalar for OP_EX.
|
||
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
|
||
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
|
||
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
|
||
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
|
||
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
|
||
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
|
||
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
|
||
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
|
||
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
|
||
(OP_E_memory): Likewise.
|
||
* i386-dis-evex.h: Updated.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
|
||
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
||
(cpu_flags): Add CpuAVX512_VBMI2.
|
||
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
|
||
(i386_cpu_flags): Add cpuavx512_vbmi2.
|
||
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
|
||
|
||
* visium-dis.c (disassem_class1) <case 0>: Print the operands.
|
||
|
||
2017-10-12 James Bowman <james.bowman@ftdichip.com>
|
||
|
||
* ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
|
||
* ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
|
||
K15. Add jmpix pattern.
|
||
|
||
2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-opc.txt (prno, tpei, irbm): New instructions added.
|
||
|
||
2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
|
||
|
||
* s390-opc.c (INSTR_SI_RD): New macro.
|
||
(INSTR_S_RD): Adjust example instruction.
|
||
* s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
|
||
SI_RD.
|
||
|
||
2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
|
||
|
||
* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
|
||
e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
|
||
VLE multimple load/store instructions. Old e_ldm* variants are
|
||
kept as aliases.
|
||
Add missing e_lmvmcsrrw and e_stmvmcsrrw.
|
||
|
||
2017-09-27 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 22179
|
||
* riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
|
||
names for the fmv.x.s and fmv.s.x instructions respectively.
|
||
|
||
2017-09-26 do <do@nerilex.org>
|
||
|
||
PR 22123
|
||
* m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
|
||
be used on CPUs that have emacs support.
|
||
|
||
2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
|
||
|
||
* aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
|
||
|
||
2017-09-09 Kamil Rytarowski <n54@gmx.com>
|
||
|
||
* nds32-asm.c: Rename __BIT() to N32_BIT().
|
||
* nds32-asm.h: Likewise.
|
||
* nds32-dis.c: Likewise.
|
||
|
||
2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (last_active_prefix): Removed.
|
||
(ckprefix): Don't set last_active_prefix.
|
||
(NOTRACK_Fixup): Don't check last_active_prefix.
|
||
|
||
2017-08-31 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/fr.po: Updated French translation.
|
||
|
||
2017-08-31 James Bowman <james.bowman@ftdichip.com>
|
||
|
||
* ft32-dis.c (print_insn_ft32): Correct display of non-address
|
||
fields.
|
||
|
||
2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
|
||
Edmar Wienskoski <edmar.wienskoski@nxp.com>
|
||
|
||
* ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
|
||
PPC_OPCODE_EFS2 flag to "e200z4" entry.
|
||
New entries efs2 and spe2.
|
||
Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
|
||
(SPE2_OPCD_SEGS): New macro.
|
||
(spe2_opcd_indices): New.
|
||
(disassemble_init_powerpc): Handle SPE2 opcodes.
|
||
(lookup_spe2): New function.
|
||
(print_insn_powerpc): call lookup_spe2.
|
||
* ppc-opc.c (insert_evuimm1_ex0): New function.
|
||
(extract_evuimm1_ex0): Likewise.
|
||
(insert_evuimm_lt8): Likewise.
|
||
(extract_evuimm_lt8): Likewise.
|
||
(insert_off_spe2): Likewise.
|
||
(extract_off_spe2): Likewise.
|
||
(insert_Ddd): Likewise.
|
||
(extract_Ddd): Likewise.
|
||
(DD): New operand.
|
||
(EVUIMM_LT8): Likewise.
|
||
(EVUIMM_LT16): Adjust.
|
||
(MMMM): New operand.
|
||
(EVUIMM_1): Likewise.
|
||
(EVUIMM_1_EX0): Likewise.
|
||
(EVUIMM_2): Adjust.
|
||
(NNN): New operand.
|
||
(VX_OFF_SPE2): Likewise.
|
||
(BBB): Likewise.
|
||
(DDD): Likewise.
|
||
(VX_MASK_DDD): New mask.
|
||
(HH): New operand.
|
||
(VX_RA_CONST): New macro.
|
||
(VX_RA_CONST_MASK): Likewise.
|
||
(VX_RB_CONST): Likewise.
|
||
(VX_RB_CONST_MASK): Likewise.
|
||
(VX_OFF_SPE2_MASK): Likewise.
|
||
(VX_SPE_CRFD): Likewise.
|
||
(VX_SPE_CRFD_MASK VX): Likewise.
|
||
(VX_SPE2_CLR): Likewise.
|
||
(VX_SPE2_CLR_MASK): Likewise.
|
||
(VX_SPE2_SPLATB): Likewise.
|
||
(VX_SPE2_SPLATB_MASK): Likewise.
|
||
(VX_SPE2_OCTET): Likewise.
|
||
(VX_SPE2_OCTET_MASK): Likewise.
|
||
(VX_SPE2_DDHH): Likewise.
|
||
(VX_SPE2_DDHH_MASK): Likewise.
|
||
(VX_SPE2_HH): Likewise.
|
||
(VX_SPE2_HH_MASK): Likewise.
|
||
(VX_SPE2_EVMAR): Likewise.
|
||
(VX_SPE2_EVMAR_MASK): Likewise.
|
||
(PPCSPE2): Likewise.
|
||
(PPCEFS2): Likewise.
|
||
(vle_opcodes): Add EFS2 and some missing SPE opcodes.
|
||
(powerpc_macros): Map old SPE instructions have new names
|
||
with the same opcodes. Add SPE2 instructions which just are
|
||
mapped to SPE2.
|
||
(spe2_opcodes): Add SPE2 opcodes.
|
||
|
||
2017-08-23 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c: Formatting and comment fixes. Move insert and
|
||
extract functions earlier, deleting forward declarations.
|
||
(insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
|
||
RA_MASK.
|
||
|
||
2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
|
||
|
||
2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
|
||
Edmar Wienskoski <edmar.wienskoski@nxp.com>
|
||
|
||
* ppc-opc.c (insert_evuimm2_ex0): New function.
|
||
(extract_evuimm2_ex0): Likewise.
|
||
(insert_evuimm4_ex0): Likewise.
|
||
(extract_evuimm4_ex0): Likewise.
|
||
(insert_evuimm8_ex0): Likewise.
|
||
(extract_evuimm8_ex0): Likewise.
|
||
(insert_evuimm_lt16): Likewise.
|
||
(extract_evuimm_lt16): Likewise.
|
||
(insert_rD_rS_even): Likewise.
|
||
(extract_rD_rS_even): Likewise.
|
||
(insert_off_lsp): Likewise.
|
||
(extract_off_lsp): Likewise.
|
||
(RD_EVEN): New operand.
|
||
(RS_EVEN): Likewise.
|
||
(RSQ): Adjust.
|
||
(EVUIMM_LT16): New operand.
|
||
(HTM_SI): Adjust.
|
||
(EVUIMM_2_EX0): New operand.
|
||
(EVUIMM_4): Adjust.
|
||
(EVUIMM_4_EX0): New operand.
|
||
(EVUIMM_8): Adjust.
|
||
(EVUIMM_8_EX0): New operand.
|
||
(WS): Adjust.
|
||
(VX_OFF): New operand.
|
||
(VX_LSP): New macro.
|
||
(VX_LSP_MASK): Likewise.
|
||
(VX_LSP_OFF_MASK): Likewise.
|
||
(PPC_OPCODE_LSP): Likewise.
|
||
(vle_opcodes): Add LSP opcodes.
|
||
* ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
|
||
|
||
2017-08-09 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
|
||
register operands in CRC instructions.
|
||
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
|
||
comments.
|
||
|
||
2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* disassemble.c (disassembler): Mark big and mach with
|
||
ATTRIBUTE_UNUSED.
|
||
|
||
2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* disassemble.c (disassembler): Remove arch/mach/endian
|
||
assertions.
|
||
|
||
2017-07-25 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 21739
|
||
* arc-opc.c (insert_rhv2): Use lower case first letter in error
|
||
message.
|
||
(insert_r0): Likewise.
|
||
(insert_r1): Likewise.
|
||
(insert_r2): Likewise.
|
||
(insert_r3): Likewise.
|
||
(insert_sp): Likewise.
|
||
(insert_gp): Likewise.
|
||
(insert_pcl): Likewise.
|
||
(insert_blink): Likewise.
|
||
(insert_ilink1): Likewise.
|
||
(insert_ilink2): Likewise.
|
||
(insert_ras): Likewise.
|
||
(insert_rbs): Likewise.
|
||
(insert_rcs): Likewise.
|
||
(insert_simm3s): Likewise.
|
||
(insert_rrange): Likewise.
|
||
(insert_r13el): Likewise.
|
||
(insert_fpel): Likewise.
|
||
(insert_blinkel): Likewise.
|
||
(insert_pclel): Likewise.
|
||
(insert_nps_bitop_size_2b): Likewise.
|
||
(insert_nps_imm_offset): Likewise.
|
||
(insert_nps_imm_entry): Likewise.
|
||
(insert_nps_size_16bit): Likewise.
|
||
(insert_nps_##NAME##_pos): Likewise.
|
||
(insert_nps_##NAME): Likewise.
|
||
(insert_nps_bitop_ins_ext): Likewise.
|
||
(insert_nps_##NAME): Likewise.
|
||
(insert_nps_min_hofs): Likewise.
|
||
(insert_nps_##NAME): Likewise.
|
||
(insert_nps_rbdouble_64): Likewise.
|
||
(insert_nps_misc_imm_offset): Likewise.
|
||
* riscv-dis.c (print_riscv_disassembler_options): Fix typo in
|
||
option description.
|
||
|
||
2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
|
||
Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
|
||
correct the print.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
|
||
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
|
||
table.
|
||
|
||
2017-07-20 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/de.po: Updated German translation.
|
||
|
||
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-regs.h (sec_stat): New aux register.
|
||
(aux_kernel_sp): Likewise.
|
||
(aux_sec_u_sp): Likewise.
|
||
(aux_sec_k_sp): Likewise.
|
||
(sec_vecbase_build): Likewise.
|
||
(nsc_table_top): Likewise.
|
||
(nsc_table_base): Likewise.
|
||
(ersec_stat): Likewise.
|
||
(aux_sec_except): Likewise.
|
||
|
||
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-opc.c (extract_uimm12_20): New function.
|
||
(UIMM12_20): New operand.
|
||
(SIMM3_5_S): Adjust.
|
||
* arc-tbl.h (sjli): Add new instruction.
|
||
|
||
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
|
||
John Eric Martin <John.Martin@emmicro-us.com>
|
||
|
||
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
|
||
(UIMM3_23): Adjust accordingly.
|
||
* arc-regs.h: Add/correct jli_base register.
|
||
* arc-tbl.h (jli_s): Likewise.
|
||
|
||
2017-07-18 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 21775
|
||
* aarch64-opc.c: Fix spelling typos.
|
||
* i386-dis.c: Likewise.
|
||
|
||
2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
|
||
|
||
* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
|
||
max_addr_offset and octets variables to size_t.
|
||
|
||
2017-07-12 Alan Modra <amodra@gmail.com>
|
||
|
||
* po/da.po: Update from translationproject.org/latest/opcodes/.
|
||
* po/de.po: Likewise.
|
||
* po/es.po: Likewise.
|
||
* po/fi.po: Likewise.
|
||
* po/fr.po: Likewise.
|
||
* po/id.po: Likewise.
|
||
* po/it.po: Likewise.
|
||
* po/nl.po: Likewise.
|
||
* po/pt_BR.po: Likewise.
|
||
* po/ro.po: Likewise.
|
||
* po/sv.po: Likewise.
|
||
* po/tr.po: Likewise.
|
||
* po/uk.po: Likewise.
|
||
* po/vi.po: Likewise.
|
||
* po/zh_CN.po: Likewise.
|
||
|
||
2017-07-11 Yao Qi <yao.qi@linaro.org>
|
||
Alan Modra <amodra@gmail.com>
|
||
|
||
* cgen.sh: Mark generated files read-only.
|
||
* epiphany-asm.c: Regenerate.
|
||
* epiphany-desc.c: Regenerate.
|
||
* epiphany-desc.h: Regenerate.
|
||
* epiphany-dis.c: Regenerate.
|
||
* epiphany-ibld.c: Regenerate.
|
||
* epiphany-opc.c: Regenerate.
|
||
* epiphany-opc.h: Regenerate.
|
||
* fr30-asm.c: Regenerate.
|
||
* fr30-desc.c: Regenerate.
|
||
* fr30-desc.h: Regenerate.
|
||
* fr30-dis.c: Regenerate.
|
||
* fr30-ibld.c: Regenerate.
|
||
* fr30-opc.c: Regenerate.
|
||
* fr30-opc.h: Regenerate.
|
||
* frv-asm.c: Regenerate.
|
||
* frv-desc.c: Regenerate.
|
||
* frv-desc.h: Regenerate.
|
||
* frv-dis.c: Regenerate.
|
||
* frv-ibld.c: Regenerate.
|
||
* frv-opc.c: Regenerate.
|
||
* frv-opc.h: Regenerate.
|
||
* ip2k-asm.c: Regenerate.
|
||
* ip2k-desc.c: Regenerate.
|
||
* ip2k-desc.h: Regenerate.
|
||
* ip2k-dis.c: Regenerate.
|
||
* ip2k-ibld.c: Regenerate.
|
||
* ip2k-opc.c: Regenerate.
|
||
* ip2k-opc.h: Regenerate.
|
||
* iq2000-asm.c: Regenerate.
|
||
* iq2000-desc.c: Regenerate.
|
||
* iq2000-desc.h: Regenerate.
|
||
* iq2000-dis.c: Regenerate.
|
||
* iq2000-ibld.c: Regenerate.
|
||
* iq2000-opc.c: Regenerate.
|
||
* iq2000-opc.h: Regenerate.
|
||
* lm32-asm.c: Regenerate.
|
||
* lm32-desc.c: Regenerate.
|
||
* lm32-desc.h: Regenerate.
|
||
* lm32-dis.c: Regenerate.
|
||
* lm32-ibld.c: Regenerate.
|
||
* lm32-opc.c: Regenerate.
|
||
* lm32-opc.h: Regenerate.
|
||
* lm32-opinst.c: Regenerate.
|
||
* m32c-asm.c: Regenerate.
|
||
* m32c-desc.c: Regenerate.
|
||
* m32c-desc.h: Regenerate.
|
||
* m32c-dis.c: Regenerate.
|
||
* m32c-ibld.c: Regenerate.
|
||
* m32c-opc.c: Regenerate.
|
||
* m32c-opc.h: Regenerate.
|
||
* m32r-asm.c: Regenerate.
|
||
* m32r-desc.c: Regenerate.
|
||
* m32r-desc.h: Regenerate.
|
||
* m32r-dis.c: Regenerate.
|
||
* m32r-ibld.c: Regenerate.
|
||
* m32r-opc.c: Regenerate.
|
||
* m32r-opc.h: Regenerate.
|
||
* m32r-opinst.c: Regenerate.
|
||
* mep-asm.c: Regenerate.
|
||
* mep-desc.c: Regenerate.
|
||
* mep-desc.h: Regenerate.
|
||
* mep-dis.c: Regenerate.
|
||
* mep-ibld.c: Regenerate.
|
||
* mep-opc.c: Regenerate.
|
||
* mep-opc.h: Regenerate.
|
||
* mt-asm.c: Regenerate.
|
||
* mt-desc.c: Regenerate.
|
||
* mt-desc.h: Regenerate.
|
||
* mt-dis.c: Regenerate.
|
||
* mt-ibld.c: Regenerate.
|
||
* mt-opc.c: Regenerate.
|
||
* mt-opc.h: Regenerate.
|
||
* or1k-asm.c: Regenerate.
|
||
* or1k-desc.c: Regenerate.
|
||
* or1k-desc.h: Regenerate.
|
||
* or1k-dis.c: Regenerate.
|
||
* or1k-ibld.c: Regenerate.
|
||
* or1k-opc.c: Regenerate.
|
||
* or1k-opc.h: Regenerate.
|
||
* or1k-opinst.c: Regenerate.
|
||
* xc16x-asm.c: Regenerate.
|
||
* xc16x-desc.c: Regenerate.
|
||
* xc16x-desc.h: Regenerate.
|
||
* xc16x-dis.c: Regenerate.
|
||
* xc16x-ibld.c: Regenerate.
|
||
* xc16x-opc.c: Regenerate.
|
||
* xc16x-opc.h: Regenerate.
|
||
* xstormy16-asm.c: Regenerate.
|
||
* xstormy16-desc.c: Regenerate.
|
||
* xstormy16-desc.h: Regenerate.
|
||
* xstormy16-dis.c: Regenerate.
|
||
* xstormy16-ibld.c: Regenerate.
|
||
* xstormy16-opc.c: Regenerate.
|
||
* xstormy16-opc.h: Regenerate.
|
||
|
||
2017-07-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* cgen-dis.in: Include disassemble.h, not dis-asm.h.
|
||
* m32c-dis.c: Regenerate.
|
||
* mep-dis.c: Regenerate.
|
||
|
||
2017-07-05 Borislav Petkov <bp@suse.de>
|
||
|
||
* i386-dis.c: Enable ModRM.reg /6 aliases.
|
||
|
||
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
||
|
||
* opcodes/arm-dis.c: Support MVFR2 in disassembly
|
||
with vmrs and vmsr.
|
||
|
||
2017-07-04 Tristan Gingold <gingold@adacore.com>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2017-07-03 Tristan Gingold <gingold@adacore.com>
|
||
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
|
||
entries to the MSA ASE instruction block.
|
||
|
||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* micromips-opc.c (XPA, XPAVZ): New macros.
|
||
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
|
||
"mthgc0".
|
||
|
||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* micromips-opc.c (I36): New macro.
|
||
(micromips_opcodes): Add "eretnc".
|
||
|
||
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
||
Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-dis.c (mips_calculate_combination_ases): Handle the
|
||
ASE_XPA_VIRT flag.
|
||
(parse_mips_ase_option): New function.
|
||
(parse_mips_dis_option): Factor out ASE option handling to the
|
||
new function. Call `mips_calculate_combination_ases'.
|
||
* mips-opc.c (XPAVZ): New macro.
|
||
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
|
||
"mfhgc0", "mthc0" and "mthgc0".
|
||
|
||
2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (mips_calculate_combination_ases): New function.
|
||
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
|
||
calculation to the new function.
|
||
(set_default_mips_dis_options): Call the new function.
|
||
|
||
2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
||
|
||
* arc-dis.c (parse_disassembler_options): Use
|
||
FOR_EACH_DISASSEMBLER_OPTION.
|
||
|
||
2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
|
||
|
||
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
|
||
disassembler option strings.
|
||
(parse_cpu_option): Likewise.
|
||
|
||
2017-06-28 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
|
||
* aarch64-dis.c (aarch64_ext_reglane): Likewise.
|
||
* aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
|
||
(aarch64_feature_dotprod, DOT_INSN): New.
|
||
(udot, sdot): New.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
|
||
2017-06-28 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
|
||
|
||
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
||
Matthew Fortune <matthew.fortune@imgtec.com>
|
||
Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-formats.h (INT_BIAS): New macro.
|
||
(INT_ADJ): Redefine in INT_BIAS terms.
|
||
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
|
||
(mips_print_save_restore): New function.
|
||
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
|
||
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
|
||
call.
|
||
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
|
||
(print_mips16_insn_arg): Call `mips_print_save_restore' for
|
||
OP_SAVE_RESTORE_LIST handling, factored out from here.
|
||
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
|
||
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
|
||
(mips_builtin_opcodes): Add "restore" and "save" entries.
|
||
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
|
||
(IAMR2): New macro.
|
||
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
|
||
|
||
2017-06-23 Andrew Waterman <andrew@sifive.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
|
||
alias; do not mark SLTI instruction as an alias.
|
||
|
||
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (RM_0FAE_REG_5): Removed.
|
||
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
|
||
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
|
||
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
|
||
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
|
||
PREFIX_MOD_3_0F01_REG_5_RM_0.
|
||
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
|
||
PREFIX_MOD_3_0FAE_REG_5.
|
||
(mod_table): Update MOD_0FAE_REG_5.
|
||
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
|
||
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
|
||
* i386-opc.tbl: Likewise.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
|
||
and "jmp{&|}".
|
||
(NOTRACK_Fixup): Support memory indirect branch with NOTRACK
|
||
prefix.
|
||
|
||
2017-06-19 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21614
|
||
* score-dis.c (score_opcodes): Add sentinel.
|
||
|
||
2017-06-16 Alan Modra <amodra@gmail.com>
|
||
|
||
* rx-decode.c: Regenerate.
|
||
|
||
2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/21594
|
||
* i386-dis.c (OP_E_register): Check valid bnd register.
|
||
(OP_G): Likewise.
|
||
|
||
2017-06-15 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21595
|
||
* aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
|
||
range value.
|
||
|
||
2017-06-15 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21588
|
||
* rl78-decode.opc (OP_BUF_LEN): Define.
|
||
(GETBYTE): Check for the index exceeding OP_BUF_LEN.
|
||
(rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
|
||
array.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2017-06-15 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21586
|
||
* bfin-dis.c (gregs): Clip index to prevent overflow.
|
||
(regs): Likewise.
|
||
(regs_lo): Likewise.
|
||
(regs_hi): Likewise.
|
||
|
||
2017-06-14 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21576
|
||
* score7-dis.c (score_opcodes): Add sentinel.
|
||
|
||
2017-06-14 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
|
||
* arm-dis.c: Likewise.
|
||
* ia64-dis.c: Likewise.
|
||
* mips-dis.c: Likewise.
|
||
* spu-dis.c: Likewise.
|
||
* disassemble.h (print_insn_aarch64): New declaration, moved from
|
||
include/dis-asm.h.
|
||
(print_insn_big_arm, print_insn_big_mips): Likewise.
|
||
(print_insn_i386, print_insn_ia64): Likewise.
|
||
(print_insn_little_arm, print_insn_little_mips): Likewise.
|
||
|
||
2017-06-14 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21587
|
||
* rx-decode.opc: Include libiberty.h
|
||
(GET_SCALE): New macro - validates access to SCALE array.
|
||
(GET_PSCALE): New macro - validates access to PSCALE array.
|
||
(DIs, SIs, S2Is, rx_disp): Use new macros.
|
||
* rx-decode.c: Regenerate.
|
||
|
||
2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||
|
||
* arm-dis.c (print_insn_arm): Remove bogus entry for bx.
|
||
|
||
2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
|
||
|
||
* arc-dis.c (enforced_isa_mask): Declare.
|
||
(cpu_types): Likewise.
|
||
(parse_cpu_option): New function.
|
||
(parse_disassembler_options): Use it.
|
||
(print_insn_arc): Use enforced_isa_mask.
|
||
(print_arc_disassembler_options): Document new options.
|
||
|
||
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* alpha-dis.c: Include disassemble.h, don't include
|
||
dis-asm.h.
|
||
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
|
||
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
|
||
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
|
||
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
|
||
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
|
||
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
|
||
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
|
||
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
|
||
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
|
||
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
|
||
* moxie-dis.c, msp430-dis.c, mt-dis.c:
|
||
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
|
||
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
|
||
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
|
||
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
|
||
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
|
||
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
|
||
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
|
||
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
|
||
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
|
||
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
|
||
* z80-dis.c, z8k-dis.c: Likewise.
|
||
* disassemble.h: New file.
|
||
|
||
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* rl78-dis.c (rl78_get_disassembler): If parameter abfd
|
||
is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
|
||
|
||
2017-05-24 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* disassemble.c (disassembler): Add arguments a, big and mach.
|
||
Use them.
|
||
|
||
2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (NOTRACK_Fixup): New.
|
||
(NOTRACK): Likewise.
|
||
(NOTRACK_PREFIX): Likewise.
|
||
(last_active_prefix): Likewise.
|
||
(reg_table): Use NOTRACK on indirect call and jmp.
|
||
(ckprefix): Set last_active_prefix.
|
||
(prefix_name): Return "notrack" for NOTRACK_PREFIX.
|
||
* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
|
||
* i386-opc.h (NoTrackPrefixOk): New.
|
||
(i386_opcode_modifier): Add notrackprefixok.
|
||
* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
|
||
Add notrack.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||
|
||
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
|
||
(X_IMM2): Define.
|
||
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
|
||
bfd_mach_sparc_v9m8.
|
||
(print_insn_sparc): Handle new operand types.
|
||
* sparc-opc.c (MASK_M8): Define.
|
||
(v6): Add MASK_M8.
|
||
(v6notlet): Likewise.
|
||
(v7): Likewise.
|
||
(v8): Likewise.
|
||
(v9): Likewise.
|
||
(v9a): Likewise.
|
||
(v9b): Likewise.
|
||
(v9c): Likewise.
|
||
(v9d): Likewise.
|
||
(v9e): Likewise.
|
||
(v9v): Likewise.
|
||
(v9m): Likewise.
|
||
(v9andleon): Likewise.
|
||
(m8): Define.
|
||
(HWS_VM8): Define.
|
||
(HWS2_VM8): Likewise.
|
||
(sparc_opcode_archs): Add entry for "m8".
|
||
(sparc_opcodes): Add OSA2017 and M8 instructions
|
||
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
|
||
fpx{ll,ra,rl}64x,
|
||
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
|
||
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
|
||
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
|
||
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
|
||
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
|
||
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
|
||
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
|
||
ASI_CORE_SELECT_COMMIT_NHT.
|
||
|
||
2017-05-18 Alan Modra <amodra@gmail.com>
|
||
|
||
* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
|
||
* aarch64-dis.c: Likewise.
|
||
* aarch64-gen.c: Likewise.
|
||
* aarch64-opc.c: Likewise.
|
||
|
||
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
|
||
Matthew Fortune <matthew.fortune@imgtec.com>
|
||
|
||
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
|
||
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
|
||
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
|
||
(print_insn_arg) <OP_REG28>: Add handler.
|
||
(validate_insn_args) <OP_REG28>: Handle.
|
||
(print_mips16_insn_arg): Handle MIPS16 instructions that require
|
||
32-bit encoding and 9-bit immediates.
|
||
(print_insn_mips16): Handle MIPS16 instructions that require
|
||
32-bit encoding and MFC0/MTC0 operand decoding.
|
||
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
|
||
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
|
||
(RD_C0, WR_C0, E2, E2MT): New macros.
|
||
(mips16_opcodes): Add entries for MIPS16e2 instructions:
|
||
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
|
||
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
|
||
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
|
||
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
|
||
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
|
||
instructions, "swl", "swr", "sync" and its "sync_acquire",
|
||
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
|
||
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
|
||
regular/extended entries for original MIPS16 ISA revision
|
||
instructions whose extended forms are subdecoded in the MIPS16e2
|
||
ISA revision: "li", "sll" and "srl".
|
||
|
||
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
|
||
reference in CP0 move operand decoding.
|
||
|
||
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
|
||
type to hexadecimal.
|
||
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
|
||
|
||
2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
|
||
"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
|
||
"sync_rmb" and "sync_wmb" as aliases.
|
||
* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
|
||
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
|
||
|
||
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-dis.c (parse_option): Update quarkse_em option..
|
||
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
|
||
QUARKSE1.
|
||
(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
|
||
|
||
2017-05-03 Kito Cheng <kito.cheng@gmail.com>
|
||
|
||
* riscv-dis.c (print_insn_args): Handle 'Co' operands.
|
||
|
||
2017-05-01 Michael Clark <michaeljclark@mac.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
|
||
register.
|
||
|
||
2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
|
||
and branches and not synthetic data instructions.
|
||
|
||
2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Fix value_in_comment.
|
||
|
||
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
|
||
* arc-opc.c (insert_r13el): New function.
|
||
(R13_EL): Define.
|
||
* arc-tbl.h: Add new enter/leave variants.
|
||
|
||
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
|
||
|
||
2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips-dis.c (print_mips_disassembler_options): Add
|
||
`no-aliases'.
|
||
|
||
2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
|
||
|
||
* mips16-opc.c (AL): New macro.
|
||
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
|
||
of "ld" and "lw" as aliases.
|
||
|
||
2017-04-24 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
|
||
arguments.
|
||
|
||
2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
|
||
Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c (ELEV): Define.
|
||
(vle_opcodes): Add se_rfgi and e_sc.
|
||
(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
|
||
for E200Z4.
|
||
|
||
2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||
|
||
* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
|
||
|
||
2017-04-21 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/21380
|
||
* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
|
||
LD3R and LD4R.
|
||
|
||
2017-04-13 Alan Modra <amodra@gmail.com>
|
||
|
||
* epiphany-desc.c: Regenerate.
|
||
* fr30-desc.c: Regenerate.
|
||
* frv-desc.c: Regenerate.
|
||
* ip2k-desc.c: Regenerate.
|
||
* iq2000-desc.c: Regenerate.
|
||
* lm32-desc.c: Regenerate.
|
||
* m32c-desc.c: Regenerate.
|
||
* m32r-desc.c: Regenerate.
|
||
* mep-desc.c: Regenerate.
|
||
* mt-desc.c: Regenerate.
|
||
* or1k-desc.c: Regenerate.
|
||
* xc16x-desc.c: Regenerate.
|
||
* xstormy16-desc.c: Regenerate.
|
||
|
||
2017-04-11 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
|
||
PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
|
||
PPC_OPCODE_TMR for e6500.
|
||
* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
|
||
(PPCVEC3): Define as PPC_OPCODE_POWER9.
|
||
(PPCVSX2): Define as PPC_OPCODE_POWER8.
|
||
(PPCVSX3): Define as PPC_OPCODE_POWER9.
|
||
(PPCHTM): Define as PPC_OPCODE_POWER8.
|
||
(powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
|
||
|
||
2017-04-10 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
|
||
* ppc-opc.c (MULHW): Add PPC_OPCODE_476.
|
||
(powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
|
||
removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
|
||
|
||
2017-04-09 Pip Cet <pipcet@gmail.com>
|
||
|
||
* wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
|
||
appropriate floating-point precision directly.
|
||
|
||
2017-04-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
|
||
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
|
||
lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
|
||
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
|
||
vector instructions with E6500 not PPCVEC2.
|
||
|
||
2017-04-06 Pip Cet <pipcet@gmail.com>
|
||
|
||
* Makefile.am: Add wasm32-dis.c.
|
||
* configure.ac: Add wasm32-dis.c to wasm32 target.
|
||
* disassemble.c: Add wasm32 disassembler code.
|
||
* wasm32-dis.c: New file.
|
||
* Makefile.in: Regenerate.
|
||
* configure: Regenerate.
|
||
* po/POTFILES.in: Regenerate.
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2017-04-05 Pedro Alves <palves@redhat.com>
|
||
|
||
* arc-dis.c (parse_option, parse_disassembler_options): Constify.
|
||
* arm-dis.c (parse_arm_disassembler_options): Constify.
|
||
* ppc-dis.c (powerpc_init_dialect): Constify local.
|
||
* vax-dis.c (parse_disassembler_options): Constify.
|
||
|
||
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
||
|
||
* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
|
||
RISCV_GP_SYMBOL.
|
||
|
||
2017-03-30 Pip Cet <pipcet@gmail.com>
|
||
|
||
* configure.ac: Add (empty) bfd_wasm32_arch target.
|
||
* configure: Regenerate
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
|
||
|
||
Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
|
||
OSA2015.
|
||
* opcodes/sparc-opc.c (asi_table): New ASIs.
|
||
|
||
2017-03-29 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
|
||
"raw" option.
|
||
(lookup_powerpc): Don't special case -1 dialect. Handle
|
||
PPC_OPCODE_RAW.
|
||
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
|
||
lookup_powerpc call, pass it on second.
|
||
|
||
2017-03-27 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 21303
|
||
* ppc-dis.c (struct ppc_mopt): Comment.
|
||
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
|
||
|
||
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
||
|
||
* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
|
||
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
|
||
F_NPS_M, F_NPS_CORE, F_NPS_ALL.
|
||
(insert_nps_misc_imm_offset): New function.
|
||
(extract_nps_misc imm_offset): New function.
|
||
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
|
||
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
|
||
|
||
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-mkopc.c (main): Remove vx2 check.
|
||
* s390-opc.txt: Remove vx2 instruction flags.
|
||
|
||
2017-03-21 Rinat Zelig <rinat@mellanox.com>
|
||
|
||
* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
|
||
* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
|
||
(insert_nps_imm_offset): New function.
|
||
(extract_nps_imm_offset): New function.
|
||
(insert_nps_imm_entry): New function.
|
||
(extract_nps_imm_entry): New function.
|
||
|
||
2017-03-17 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 21248
|
||
* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
|
||
mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
|
||
those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
|
||
|
||
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
|
||
<c.andi>: Likewise.
|
||
<c.addiw> Likewise.
|
||
|
||
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
|
||
|
||
2017-03-13 Andrew Waterman <andrew@sifive.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
|
||
<srl> Likewise.
|
||
<srai> Likewise.
|
||
<sra> Likewise.
|
||
|
||
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (opcode_modifiers): Replace S with Load.
|
||
* i386-opc.h (S): Removed.
|
||
(Load): New.
|
||
(i386_opcode_modifier): Replace s with load.
|
||
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
|
||
and {evex}. Replace S with Load.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-opc.tbl: Use CpuCET on rdsspq.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
|
||
<vsx>: Do not use PPC_OPCODE_VSX3;
|
||
|
||
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
|
||
|
||
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (REG_0F1E_MOD_3): New enum.
|
||
(MOD_0F1E_PREFIX_1): Likewise.
|
||
(MOD_0F38F5_PREFIX_2): Likewise.
|
||
(MOD_0F38F6_PREFIX_0): Likewise.
|
||
(RM_0F1E_MOD_3_REG_7): Likewise.
|
||
(PREFIX_MOD_0_0F01_REG_5): Likewise.
|
||
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
|
||
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
|
||
(PREFIX_0F1E): Likewise.
|
||
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
|
||
(PREFIX_0F38F5): Likewise.
|
||
(dis386_twobyte): Use PREFIX_0F1E.
|
||
(reg_table): Add REG_0F1E_MOD_3.
|
||
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
|
||
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
|
||
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
|
||
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
|
||
(three_byte_table): Use PREFIX_0F38F5.
|
||
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
|
||
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
|
||
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
|
||
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
|
||
PREFIX_MOD_3_0F01_REG_5_RM_2.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
|
||
(cpu_flags): Add CpuCET.
|
||
* i386-opc.h (CpuCET): New enum.
|
||
(CpuUnused): Commented out.
|
||
(i386_cpu_flags): Add cpucet.
|
||
* i386-opc.tbl: Add Intel CET instructions.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2017-03-06 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 21124
|
||
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
|
||
(extract_raq, extract_ras, extract_rbx): New functions.
|
||
(powerpc_operands): Use opposite corresponding insert function.
|
||
(Q_MASK): Define.
|
||
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
|
||
register restriction.
|
||
|
||
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* disassemble.c Include "safe-ctype.h".
|
||
(disassemble_init_for_target): Handle s390 init.
|
||
(remove_whitespace_and_extra_commas): New function.
|
||
(disassembler_options_cmp): Likewise.
|
||
* arm-dis.c: Include "libiberty.h".
|
||
(NUM_ELEM): Delete.
|
||
(regnames): Use long disassembler style names.
|
||
Add force-thumb and no-force-thumb options.
|
||
(NUM_ARM_REGNAMES): Rename from this...
|
||
(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
|
||
(get_arm_regname_num_options): Delete.
|
||
(set_arm_regname_option): Likewise.
|
||
(get_arm_regnames): Likewise.
|
||
(parse_disassembler_options): Likewise.
|
||
(parse_arm_disassembler_option): Rename from this...
|
||
(parse_arm_disassembler_options): ...to this. Make static.
|
||
Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
|
||
(print_insn): Use parse_arm_disassembler_options.
|
||
(disassembler_options_arm): New function.
|
||
(print_arm_disassembler_options): Handle updated regnames.
|
||
* ppc-dis.c: Include "libiberty.h".
|
||
(ppc_opts): Add "32" and "64" entries.
|
||
(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
|
||
(powerpc_init_dialect): Add break to switch statement.
|
||
Use new FOR_EACH_DISASSEMBLER_OPTION macro.
|
||
(disassembler_options_powerpc): New function.
|
||
(print_ppc_disassembler_options): Use ARRAY_SIZE.
|
||
Remove printing of "32" and "64".
|
||
* s390-dis.c: Include "libiberty.h".
|
||
(init_flag): Remove unneeded variable.
|
||
(struct s390_options_t): New structure type.
|
||
(options): New structure.
|
||
(init_disasm): Rename from this...
|
||
(disassemble_init_s390): ...to this. Add initializations for
|
||
current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
|
||
(print_insn_s390): Delete call to init_disasm.
|
||
(disassembler_options_s390): New function.
|
||
(print_s390_disassembler_options): Print using information from
|
||
struct 'options'.
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2017-02-28 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (PCMPESTR_Fixup): New.
|
||
(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
|
||
(prefix_table): Use PCMPESTR_Fixup.
|
||
(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
|
||
PCMPESTR_Fixup.
|
||
(vex_w_table): Delete VPCMPESTR{I,M} entries.
|
||
* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
|
||
Split 64-bit and non-64-bit variants.
|
||
* opcodes/i386-tbl.h: Re-generate.
|
||
|
||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||
|
||
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
|
||
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
|
||
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
|
||
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
|
||
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
|
||
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
|
||
(OP_SVE_V_HSD): New macros.
|
||
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
|
||
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
|
||
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
|
||
(aarch64_opcode_table): Add new SVE instructions.
|
||
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
|
||
for rotation operands. Add new SVE operands.
|
||
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
|
||
(ins_sve_quad_index): Likewise.
|
||
(ins_imm_rotate): Split into...
|
||
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
|
||
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
|
||
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
|
||
functions.
|
||
(aarch64_ins_sve_addr_ri_s4): New function.
|
||
(aarch64_ins_sve_quad_index): Likewise.
|
||
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
|
||
(ext_sve_quad_index): Likewise.
|
||
(ext_imm_rotate): Split into...
|
||
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
|
||
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
|
||
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
|
||
functions.
|
||
(aarch64_ext_sve_addr_ri_s4): New function.
|
||
(aarch64_ext_sve_quad_index): Likewise.
|
||
(aarch64_ext_sve_index): Allow quad indices.
|
||
(do_misc_decoding): Likewise.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
|
||
aarch64_field_kinds.
|
||
(OPD_F_OD_MASK): Widen by one bit.
|
||
(OPD_F_NO_ZR): Bump accordingly.
|
||
(get_operand_field_width): New function.
|
||
* aarch64-opc.c (fields): Add new SVE fields.
|
||
(operand_general_constraint_met_p): Handle new SVE operands.
|
||
(aarch64_print_operand): Likewise.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
|
||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
|
||
(aarch64_feature_compnum): ...this.
|
||
(SIMD_V8_3): Replace with...
|
||
(COMPNUM): ...this.
|
||
(CNUM_INSN): New macro.
|
||
(aarch64_opcode_table): Use it for the complex number instructions.
|
||
|
||
2017-02-24 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
|
||
|
||
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
|
||
|
||
Add support for associating SPARC ASIs with an architecture level.
|
||
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
|
||
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
|
||
decoding of SPARC ASIs.
|
||
|
||
2017-02-23 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
|
||
82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
|
||
|
||
2017-02-21 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
|
||
1 (instead of to itself). Correct typo.
|
||
|
||
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
|
||
pseudoinstructions.
|
||
|
||
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
|
||
(aarch64_sys_reg_supported_p): Handle them.
|
||
|
||
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-opc.c (UIMM6_20R): Define.
|
||
(SIMM12_20): Use above.
|
||
(SIMM12_20R): Define.
|
||
(SIMM3_5_S): Use above.
|
||
(UIMM7_A32_11R_S): Define.
|
||
(UIMM7_9_S): Use above.
|
||
(UIMM3_13R_S): Define.
|
||
(SIMM11_A32_7_S): Use above.
|
||
(SIMM9_8R): Define.
|
||
(UIMM10_A32_8_S): Use above.
|
||
(UIMM8_8R_S): Define.
|
||
(W6): Use above.
|
||
(arc_relax_opcodes): Use all above defines.
|
||
|
||
2017-02-15 Vineet Gupta <vgupta@synopsys.com>
|
||
|
||
* arc-regs.h: Distinguish some of the registers different on
|
||
ARC700 and HS38 cpus.
|
||
|
||
2017-02-14 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 21118
|
||
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
|
||
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
|
||
|
||
2017-02-11 Stafford Horne <shorne@gmail.com>
|
||
Alan Modra <amodra@gmail.com>
|
||
|
||
* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
|
||
Use insn_bytes_value and insn_int_value directly instead. Don't
|
||
free allocated memory until function exit.
|
||
|
||
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
|
||
|
||
2017-02-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 21096
|
||
* aarch64-opc.c (print_register_list): Ensure that the register
|
||
list index will fir into the tb buffer.
|
||
(print_register_offset_address): Likewise.
|
||
* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
|
||
|
||
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
|
||
|
||
PR 21056
|
||
* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
|
||
instructions when the previous fetch packet ends with a 32-bit
|
||
instruction.
|
||
|
||
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
||
|
||
* pru-opc.c: Remove vague reference to a future GDB port.
|
||
|
||
2017-01-20 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/ga.po: Updated Irish translation.
|
||
|
||
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
|
||
|
||
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
|
||
if FETCH_DATA returns 0.
|
||
(m68k_scan_mask): Likewise.
|
||
(print_insn_m68k): Update code to handle -1 return value.
|
||
|
||
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* m68k-dis.c (enum print_insn_arg_error): New.
|
||
(NEXTBYTE): Replace -3 with
|
||
PRINT_INSN_ARG_MEMORY_ERROR.
|
||
(NEXTULONG): Likewise.
|
||
(NEXTSINGLE): Likewise.
|
||
(NEXTDOUBLE): Likewise.
|
||
(NEXTDOUBLE): Likewise.
|
||
(NEXTPACKED): Likewise.
|
||
(FETCH_ARG): Likewise.
|
||
(FETCH_DATA): Update comments.
|
||
(print_insn_arg): Update comments. Replace magic numbers with
|
||
enum.
|
||
(match_insn_m68k): Likewise.
|
||
|
||
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
|
||
* i386-dis-evex.h (evex_table): Updated.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
|
||
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
||
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
|
||
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
|
||
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
|
||
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Ditto.
|
||
|
||
2017-01-12 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* msp430-dis.c (msp430_singleoperand): Return -1 if
|
||
msp430dis_opcode_signed returns false.
|
||
(msp430_doubleoperand): Likewise.
|
||
(msp430_branchinstr): Return -1 if
|
||
msp430dis_opcode_unsigned returns false.
|
||
(msp430x_calla_instr): Likewise.
|
||
(print_insn_msp430): Likewise.
|
||
|
||
2017-01-05 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 20946
|
||
* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
|
||
could not be matched.
|
||
(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
|
||
NULL.
|
||
|
||
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||
|
||
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
|
||
(aarch64_opcode_table): Use RCPC_INSN.
|
||
|
||
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
|
||
|
||
* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
|
||
extension.
|
||
* riscv-opcodes/all-opcodes: Likewise.
|
||
|
||
2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
|
||
|
||
* riscv-dis.c (print_insn_args): Add fall through comment.
|
||
|
||
2017-01-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/sr.po: New Serbian translation.
|
||
* configure.ac (ALL_LINGUAS): Add sr.
|
||
* configure: Regenerate.
|
||
|
||
2017-01-02 Alan Modra <amodra@gmail.com>
|
||
|
||
* epiphany-desc.h: Regenerate.
|
||
* epiphany-opc.h: Regenerate.
|
||
* fr30-desc.h: Regenerate.
|
||
* fr30-opc.h: Regenerate.
|
||
* frv-desc.h: Regenerate.
|
||
* frv-opc.h: Regenerate.
|
||
* ip2k-desc.h: Regenerate.
|
||
* ip2k-opc.h: Regenerate.
|
||
* iq2000-desc.h: Regenerate.
|
||
* iq2000-opc.h: Regenerate.
|
||
* lm32-desc.h: Regenerate.
|
||
* lm32-opc.h: Regenerate.
|
||
* m32c-desc.h: Regenerate.
|
||
* m32c-opc.h: Regenerate.
|
||
* m32r-desc.h: Regenerate.
|
||
* m32r-opc.h: Regenerate.
|
||
* mep-desc.h: Regenerate.
|
||
* mep-opc.h: Regenerate.
|
||
* mt-desc.h: Regenerate.
|
||
* mt-opc.h: Regenerate.
|
||
* or1k-desc.h: Regenerate.
|
||
* or1k-opc.h: Regenerate.
|
||
* xc16x-desc.h: Regenerate.
|
||
* xc16x-opc.h: Regenerate.
|
||
* xstormy16-desc.h: Regenerate.
|
||
* xstormy16-opc.h: Regenerate.
|
||
|
||
2017-01-02 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2016
|
||
|
||
Copyright (C) 2017 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|