326 lines
10 KiB
C
326 lines
10 KiB
C
/* Common target dependent code for GDB on ARM systems.
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Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef ARM_TDEP_H
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#define ARM_TDEP_H
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/* Forward declarations. */
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struct gdbarch;
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struct regset;
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/* Register numbers of various important registers. */
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enum gdb_regnum {
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ARM_A1_REGNUM = 0, /* first integer-like argument */
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ARM_A4_REGNUM = 3, /* last integer-like argument */
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ARM_AP_REGNUM = 11,
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ARM_IP_REGNUM = 12,
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ARM_SP_REGNUM = 13, /* Contains address of top of stack */
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ARM_LR_REGNUM = 14, /* address to return to from a function call */
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ARM_PC_REGNUM = 15, /* Contains program counter */
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ARM_F0_REGNUM = 16, /* first floating point register */
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ARM_F3_REGNUM = 19, /* last floating point argument register */
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ARM_F7_REGNUM = 23, /* last floating point register */
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ARM_FPS_REGNUM = 24, /* floating point status register */
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ARM_PS_REGNUM = 25, /* Contains processor status */
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ARM_WR0_REGNUM, /* WMMX data registers. */
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ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
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ARM_WC0_REGNUM, /* WMMX control registers. */
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ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
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ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
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ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
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ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
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ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
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ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
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ARM_D0_REGNUM, /* VFP double-precision registers. */
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ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
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ARM_FPSCR_REGNUM,
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ARM_NUM_REGS,
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/* Other useful registers. */
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ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
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THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
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ARM_NUM_ARG_REGS = 4,
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ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
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ARM_NUM_FP_ARG_REGS = 4,
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ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
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};
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/* Size of integer registers. */
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#define INT_REGISTER_SIZE 4
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/* Say how long FP registers are. Used for documentation purposes and
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code readability in this header. IEEE extended doubles are 80
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bits. DWORD aligned they use 96 bits. */
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#define FP_REGISTER_SIZE 12
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/* Number of machine registers. The only define actually required
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is gdbarch_num_regs. The other definitions are used for documentation
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purposes and code readability. */
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/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
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(and called PS for processor status) so the status bits can be cleared
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from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
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in PS. */
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#define NUM_FREGS 8 /* Number of floating point registers. */
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#define NUM_SREGS 2 /* Number of status registers. */
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#define NUM_GREGS 16 /* Number of general purpose registers. */
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/* Instruction condition field values. */
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#define INST_EQ 0x0
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#define INST_NE 0x1
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#define INST_CS 0x2
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#define INST_CC 0x3
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#define INST_MI 0x4
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#define INST_PL 0x5
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#define INST_VS 0x6
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#define INST_VC 0x7
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#define INST_HI 0x8
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#define INST_LS 0x9
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#define INST_GE 0xa
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#define INST_LT 0xb
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#define INST_GT 0xc
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#define INST_LE 0xd
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#define INST_AL 0xe
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#define INST_NV 0xf
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#define FLAG_N 0x80000000
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#define FLAG_Z 0x40000000
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#define FLAG_C 0x20000000
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#define FLAG_V 0x10000000
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#define CPSR_T 0x20
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#define XPSR_T 0x01000000
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/* Type of floating-point code in use by inferior. There are really 3 models
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that are traditionally supported (plus the endianness issue), but gcc can
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only generate 2 of those. The third is APCS_FLOAT, where arguments to
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functions are passed in floating-point registers.
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In addition to the traditional models, VFP adds two more.
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If you update this enum, don't forget to update fp_model_strings in
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arm-tdep.c. */
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enum arm_float_model
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{
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ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
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ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
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ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
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ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
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ARM_FLOAT_VFP, /* Full VFP calling convention. */
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ARM_FLOAT_LAST /* Keep at end. */
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};
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/* ABI used by the inferior. */
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enum arm_abi_kind
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{
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ARM_ABI_AUTO,
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ARM_ABI_APCS,
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ARM_ABI_AAPCS,
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ARM_ABI_LAST
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};
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/* Convention for returning structures. */
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enum struct_return
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{
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pcc_struct_return, /* Return "short" structures in memory. */
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reg_struct_return /* Return "short" structures in registers. */
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};
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/* Target-dependent structure in gdbarch. */
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struct gdbarch_tdep
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{
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/* The ABI for this architecture. It should never be set to
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ARM_ABI_AUTO. */
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enum arm_abi_kind arm_abi;
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enum arm_float_model fp_model; /* Floating point calling conventions. */
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int have_fpa_registers; /* Does the target report the FPA registers? */
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int have_vfp_registers; /* Does the target report the VFP registers? */
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int have_vfp_pseudos; /* Are we synthesizing the single precision
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VFP registers? */
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int have_neon_pseudos; /* Are we synthesizing the quad precision
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NEON registers? Requires
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have_vfp_pseudos. */
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int have_neon; /* Do we have a NEON unit? */
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int is_m; /* Does the target follow the "M" profile. */
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CORE_ADDR lowest_pc; /* Lowest address at which instructions
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will appear. */
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const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
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int arm_breakpoint_size; /* And its size. */
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const char *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
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int thumb_breakpoint_size; /* And its size. */
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/* If the Thumb breakpoint is an undefined instruction (which is
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affected by IT blocks) rather than a BKPT instruction (which is
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not), then we need a 32-bit Thumb breakpoint to preserve the
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instruction count in IT blocks. */
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const char *thumb2_breakpoint;
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int thumb2_breakpoint_size;
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int jb_pc; /* Offset to PC value in jump buffer.
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If this is negative, longjmp support
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will be disabled. */
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size_t jb_elt_size; /* And the size of each entry in the buf. */
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/* Convention for returning structures. */
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enum struct_return struct_return;
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/* Cached core file helpers. */
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struct regset *gregset, *fpregset;
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/* ISA-specific data types. */
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struct type *arm_ext_type;
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struct type *neon_double_type;
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struct type *neon_quad_type;
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/* Return the expected next PC if FRAME is stopped at a syscall
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instruction. */
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CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
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};
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/* Structures used for displaced stepping. */
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/* The maximum number of temporaries available for displaced instructions. */
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#define DISPLACED_TEMPS 16
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/* The maximum number of modified instructions generated for one single-stepped
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instruction, including the breakpoint (usually at the end of the instruction
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sequence) and any scratch words, etc. */
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#define DISPLACED_MODIFIED_INSNS 8
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struct displaced_step_closure
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{
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ULONGEST tmp[DISPLACED_TEMPS];
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int rd;
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int wrote_to_pc;
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union
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{
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struct
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{
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int xfersize;
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int rn; /* Writeback register. */
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unsigned int immed : 1; /* Offset is immediate. */
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unsigned int writeback : 1; /* Perform base-register writeback. */
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unsigned int restore_r4 : 1; /* Used r4 as scratch. */
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} ldst;
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struct
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{
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unsigned long dest;
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unsigned int link : 1;
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unsigned int exchange : 1;
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unsigned int cond : 4;
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} branch;
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struct
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{
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unsigned int regmask;
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int rn;
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CORE_ADDR xfer_addr;
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unsigned int load : 1;
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unsigned int user : 1;
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unsigned int increment : 1;
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unsigned int before : 1;
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unsigned int writeback : 1;
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unsigned int cond : 4;
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} block;
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struct
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{
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unsigned int immed : 1;
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} preload;
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struct
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{
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/* If non-NULL, override generic SVC handling (e.g. for a particular
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OS). */
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int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
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struct regcache *regs,
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struct displaced_step_closure *dsc);
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} svc;
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} u;
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unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
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int numinsns;
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CORE_ADDR insn_addr;
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CORE_ADDR scratch_base;
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void (*cleanup) (struct gdbarch *, struct regcache *,
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struct displaced_step_closure *);
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};
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/* Values for the WRITE_PC argument to displaced_write_reg. If the register
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write may write to the PC, specifies the way the CPSR T bit, etc. is
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modified by the instruction. */
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enum pc_write_style
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{
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BRANCH_WRITE_PC,
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BX_WRITE_PC,
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LOAD_WRITE_PC,
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ALU_WRITE_PC,
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CANNOT_WRITE_PC
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};
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extern void
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arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
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CORE_ADDR to, struct regcache *regs,
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struct displaced_step_closure *dsc);
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extern void
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arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
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CORE_ADDR to, struct displaced_step_closure *dsc);
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extern ULONGEST
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displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
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extern void
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displaced_write_reg (struct regcache *regs,
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struct displaced_step_closure *dsc, int regno,
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ULONGEST val, enum pc_write_style write_pc);
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CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
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CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
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int arm_software_single_step (struct frame_info *);
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int arm_frame_is_thumb (struct frame_info *frame);
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extern struct displaced_step_closure *
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arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
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struct regcache *);
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extern void arm_displaced_step_fixup (struct gdbarch *,
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struct displaced_step_closure *,
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CORE_ADDR, CORE_ADDR, struct regcache *);
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/* Is the instruction at the given memory address a Thumb or ARM
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instruction? */
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extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
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/* Functions exported from armbsd-tdep.h. */
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/* Return the appropriate register set for the core section identified
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by SECT_NAME and SECT_SIZE. */
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extern const struct regset *
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armbsd_regset_from_core_section (struct gdbarch *gdbarch,
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const char *sect_name, size_t sect_size);
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#endif /* arm-tdep.h */
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