152 lines
4.3 KiB
Plaintext
152 lines
4.3 KiB
Plaintext
@c Copyright (C) 2016-2018 Free Software Foundation, Inc.
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@c This is part of the GAS anual.
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@c For copying conditions, see the file as.texinfo
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@c man end
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@ifset GENERIC
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@page
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@node RISC-V-Dependent
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@chapter RISC-V Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter RISC-V Dependent Features
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@end ifclear
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@cindex RISC-V support
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@menu
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* RISC-V-Options:: RISC-V Options
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* RISC-V-Directives:: RISC-V Directives
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@end menu
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@node RISC-V-Options
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@section RISC-V Options
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The following table lists all available RISC-V specific options.
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @samp{-fpic} option, RISC-V
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@item -fpic
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@itemx -fPIC
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Generate position-independent code
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@cindex @samp{-fno-pic} option, RISC-V
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@item -fno-pic
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Don't generate position-independent code (default)
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@cindex @samp{-march=ISA} option, RISC-V
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@item -march=ISA
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Select the base isa, as specified by ISA. For example -march=rv32ima.
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@cindex @samp{-mabi=ABI} option, RISC-V
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@item -mabi=ABI
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Selects the ABI, which is either "ilp32" or "lp64", optionally followed
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by "f", "d", or "q" to indicate single-precision, double-precision, or
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quad-precision floating-point calling convention, or none to indicate
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the soft-float calling convention.
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@end table
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@c man end
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@node RISC-V-Directives
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@section RISC-V Directives
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@cindex machine directives, RISC-V
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@cindex RISC-V machine directives
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The following table lists all available RISC-V specific directives.
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@table @code
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@cindex @code{align} directive
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@item .align @var{size-log-2}
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Align to the given boundary, with the size given as log2 the number of bytes to
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align to.
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@cindex Data directives
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@item .half @var{value}
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@itemx .word @var{value}
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@itemx .dword @var{value}
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Emits a half-word, word, or double-word value at the current position.
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@cindex DTP-relative data directives
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@item .dtprelword @var{value}
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@itemx .dtpreldword @var{value}
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Emits a DTP-relative word (or double-word) at the current position. This is
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meant to be used by the compiler in shared libraries for DWARF debug info for
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thread local variables.
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@cindex BSS directive
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@item .bss
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Sets the current section to the BSS section.
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@cindex LEB128 directives
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@item .uleb128 @var{value}
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@itemx .sleb128 @var{value}
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Emits a signed or unsigned LEB128 value at the current position. This only
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accepts constant expressions, because symbol addresses can change with
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relaxation, and we don't support relocations to modify LEB128 values at link
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time.
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@cindex Option directive
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@cindex @code{option} directive
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@item .option @var{argument}
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Modifies RISC-V specific assembler options inline with the assembly code.
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This is used when particular instruction sequences must be assembled with a
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specific set of options. For example, since we relax addressing sequences to
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shorter GP-relative sequences when possible the initial load of GP must not be
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relaxed and should be emitted as something like
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@smallexample
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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@end smallexample
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in order to produce after linker relaxation the expected
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@smallexample
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auipc gp, %pcrel_hi(__global_pointer$)
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addi gp, gp, %pcrel_lo(__global_pointer$)
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@end smallexample
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instead of just
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@smallexample
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addi gp, gp, 0
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@end smallexample
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It's not expected that options are changed in this manner during regular use,
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but there are a handful of esoteric cases like the one above where users need
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to disable particular features of the assembler for particular code sequences.
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The complete list of option arguments is shown below:
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@table @code
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@item push
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@itemx pop
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Pushes or pops the current option stack. These should be used whenever
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changing an option in line with assembly code in order to ensure the user's
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command-line options are respected for the bulk of the file being assembled.
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@item rvc
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@itemx norvc
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Enables or disables the generation of compressed instructions. Instructions
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are opportunistically compressed by the RISC-V assembler when possible, but
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sometimes this behavior is not desirable.
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@item pic
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@itemx nopic
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Enables or disables position-independent code generation. Unless you really
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know what you're doing, this should only be at the top of a file.
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@item relax
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@itemx norelax
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Enables or disables relaxation. The RISC-V assembler and linker
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opportunistically relax some code sequences, but sometimes this behavior is not
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desirable.
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@end table
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@end table
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