binutils-gdb/include
Nelson Chu bd0cf5a6ba RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set.  We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information.  We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option.  Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.

	gas/
	* config/tc-riscv.c (enum riscv_csr_class): New enum.  Used to decide
	whether or not this CSR is legal in the current ISA string.
	(struct riscv_csr_extra): New structure to hold all extra information
	of CSR.
	(riscv_init_csr_hash): New function.  According to the DECLARE_CSR and
	DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
	Call hash_reg_name to insert CSR address into reg_names_hash.
	(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
	(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
	Decide whether the CSR is valid according to the csr_extra_hash.
	(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
	not a boolean.  This is same as riscv_init_csr_hash, so keep the
	consistent usage.

	* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
	* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase.  The source
	file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
	f-ext CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase.  The
	source file is `priv-reg.s`, and the ISA is rv64if, so the
	rv32-only CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.

	include/
	* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
	record riscv_csr_class.

	opcodes/
	* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.

	gdb/
	* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
	* riscv-tdep.h: Likewise.
	* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
	rv32-only CSR.
	* features/riscv/64bit-csr.xml: Regernated.

	binutils/
	* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-20 16:49:09 -08:00
..
aout Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
cgen Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
coff Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler. 2020-02-07 14:53:46 +00:00
elf Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler. 2020-02-07 14:53:46 +00:00
gdb Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
mach-o Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
opcode RISC-V: Support the ISA-dependent CSR checking. 2020-02-20 16:49:09 -08:00
som Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
vms Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
alloca-conf.h Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
ansidecl.h Update libiberty sources with changes in the gcc mainline. 2020-01-17 14:13:22 +00:00
bfdlink.h Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
binary-io.h Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
bout.h Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
ChangeLog RISC-V: Support the ISA-dependent CSR checking. 2020-02-20 16:49:09 -08:00
ChangeLog-0415
ChangeLog-2016
ChangeLog-2017
ChangeLog-2018 ChangeLog rotation 2019-01-01 21:25:40 +10:30
ChangeLog-2019 ChangeLog rotation 2020-01-01 18:12:08 +10:30
ChangeLog-9103
COPYING
COPYING3
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