385 lines
12 KiB
Plaintext
385 lines
12 KiB
Plaintext
@c Copyright 1997 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@node V850-Dependent
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@chapter v850 Dependent Features
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@cindex V850 support
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@menu
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* V850 Options:: Options
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* V850 Syntax:: Syntax
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* V850 Floating Point:: Floating Point
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* V850 Directives:: V850 Machine Directives
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* V850 Opcodes:: Opcodes
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@end menu
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@node V850 Options
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@section Options
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@cindex V850 options (none)
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@cindex options for V850 (none)
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@code{@value{AS}} supports the following additional command-line options
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for the V850 processor family:
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@cindex command line options, V850
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@cindex V850 command line options
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@table @code
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@cindex @code{-wsigned_overflow} command line option, V850
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@item -wsigned_overflow
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Causes warnings to be produced when signed immediate values overflow the
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space available for then within their opcodes. By default this option
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is disabled as it is possible to receive spurious warnings due to using
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exact bit patterns as immediate constants.
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@cindex @code{-wunsigned_overflow} command line option, V850
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@item -wunsigned_overflow
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Causes warnings to be produced when unsigned immediate values overflow
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the space available for then within their opcodes. By default this
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option is disabled as it is possible to receive spurious warnings due to
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using exact bit patterns as immediate constants.
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@cindex @code{-mv850} command line option, V850
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@item -mv850
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Specifies that the assembled code should be marked as being targeted at
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the V850 processor. This allows the linker to detect attempts to link
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such code with code assembled for other processors.
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@cindex @code{-mv850e} command line option, V850
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@item -mv850e
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Specifies that the assembled code should be marked as being targeted at
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the V850E processor. This allows the linker to detect attempts to link
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such code with code assembled for other processors.
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@cindex @code{-mv850any} command line option, V850
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@item -mv850any
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Specifies that the assembled code should be marked as being targeted at
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the V850 processor but support instructions that are specific to the
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extended variants of the process. This allows the production of
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binaries that contain target specific code, but which are also intended
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to be used in a generic fashion. For example libgcc.a contains generic
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routines used by the code produced by GCC for all versions of the v850
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architecture, together with support routines only used by the V850E
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architecture.
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@cindex @code{-mrelax} command line option, V850
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@item -mrelax
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Enables relaxation. This allows the .longcall and .longjump pseudo
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ops to be used in the assembler source code. These ops label sections
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of code which are either a long function call or a long branch. The
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assembler will then flag these sections of code and the linker will
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attempt to relax them.
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@end table
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@node V850 Syntax
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@section Syntax
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@menu
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* V850-Chars:: Special Characters
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* V850-Regs:: Register Names
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@end menu
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@node V850-Chars
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@subsection Special Characters
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@cindex line comment character, V850
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@cindex V850 line comment character
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@samp{#} is the line comment character.
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@node V850-Regs
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@subsection Register Names
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@cindex V850 register names
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@cindex register names, V850
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@code{@value{AS}} supports the following names for registers:
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@table @code
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@cindex @code{zero} register, V850
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@item general register 0
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r0, zero
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@item general register 1
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r1
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@item general register 2
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r2, hp
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@cindex @code{sp} register, V850
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@item general register 3
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r3, sp
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@cindex @code{gp} register, V850
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@item general register 4
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r4, gp
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@cindex @code{tp} register, V850
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@item general register 5
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r5, tp
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@item general register 6
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r6
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@item general register 7
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r7
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@item general register 8
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r8
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@item general register 9
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r9
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@item general register 10
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r10
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@item general register 11
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r11
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@item general register 12
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r12
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@item general register 13
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r13
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@item general register 14
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r14
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@item general register 15
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r15
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@item general register 16
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r16
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@item general register 17
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r17
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@item general register 18
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r18
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@item general register 19
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r19
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@item general register 20
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r20
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@item general register 21
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r21
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@item general register 22
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r22
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@item general register 23
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r23
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@item general register 24
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r24
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@item general register 25
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r25
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@item general register 26
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r26
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@item general register 27
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r27
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@item general register 28
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r28
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@item general register 29
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r29
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@cindex @code{ep} register, V850
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@item general register 30
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r30, ep
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@cindex @code{lp} register, V850
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@item general register 31
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r31, lp
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@cindex @code{eipc} register, V850
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@item system register 0
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eipc
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@cindex @code{eipsw} register, V850
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@item system register 1
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eipsw
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@cindex @code{fepc} register, V850
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@item system register 2
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fepc
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@cindex @code{fepsw} register, V850
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@item system register 3
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fepsw
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@cindex @code{ecr} register, V850
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@item system register 4
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ecr
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@cindex @code{psw} register, V850
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@item system register 5
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psw
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@cindex @code{ctpc} register, V850
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@item system register 16
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ctpc
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@cindex @code{ctpsw} register, V850
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@item system register 17
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ctpsw
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@cindex @code{dbpc} register, V850
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@item system register 18
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dbpc
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@cindex @code{dbpsw} register, V850
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@item system register 19
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dbpsw
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@cindex @code{ctbp} register, V850
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@item system register 20
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ctbp
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@end table
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@node V850 Floating Point
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@section Floating Point
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@cindex floating point, V850 (@sc{ieee})
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@cindex V850 floating point (@sc{ieee})
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The V850 family uses @sc{ieee} floating-point numbers.
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@node V850 Directives
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@section V850 Machine Directives
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@cindex machine directives, V850
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@cindex V850 machine directives
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@table @code
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@cindex @code{offset} directive, V850
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@item .offset @var{<expression>}
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Moves the offset into the current section to the specified amount.
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@cindex @code{section} directive, V850
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@item .section "name", <type>
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This is an extension to the standard .section directive. It sets the
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current section to be <type> and creates an alias for this section
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called "name".
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@cindex @code{.v850} directive, V850
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@item .v850
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Specifies that the assembled code should be marked as being targeted at
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the V850 processor. This allows the linker to detect attempts to link
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such code with code assembled for other processors.
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@cindex @code{.v850e} directive, V850
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@item .v850e
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Specifies that the assembled code should be marked as being targeted at
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the V850E processor. This allows the linker to detect attempts to link
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such code with code assembled for other processors.
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@end table
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@node V850 Opcodes
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@section Opcodes
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@cindex V850 opcodes
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@cindex opcodes for V850
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@code{@value{AS}} implements all the standard V850 opcodes.
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@code{@value{AS}} also implements the following pseudo ops:
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@table @code
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@cindex @code{hi0} pseudo-op, V850
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@item hi0()
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Computes the higher 16 bits of the given expression and stores it into
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the immediate operand field of the given instruction. For example:
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@samp{mulhi hi0(here - there), r5, r6}
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computes the difference between the address of labels 'here' and
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'there', takes the upper 16 bits of this difference, shifts it down 16
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bits and then mutliplies it by the lower 16 bits in register 5, putting
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the result into register 6.
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@cindex @code{lo} pseudo-op, V850
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@item lo()
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Computes the lower 16 bits of the given expression and stores it into
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the immediate operand field of the given instruction. For example:
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@samp{addi lo(here - there), r5, r6}
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computes the difference between the address of labels 'here' and
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'there', takes the lower 16 bits of this difference and adds it to
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register 5, putting the result into register 6.
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@cindex @code{hi} pseudo-op, V850
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@item hi()
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Computes the higher 16 bits of the given expression and then adds the
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value of the most significant bit of the lower 16 bits of the expression
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and stores the result into the immediate operand field of the given
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instruction. For example the following code can be used to compute the
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address of the label 'here' and store it into register 6:
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@samp{movhi hi(here), r0, r6}
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@samp{movea lo(here), r6, r6}
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The reason for this special behaviour is that movea performs a sign
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extention on its immediate operand. So for example if the address of
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'here' was 0xFFFFFFFF then without the special behaviour of the hi()
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pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
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movea instruction would takes its immediate operand, 0xFFFF, sign extend
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it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
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which is wrong (the fifth nibble is E). With the hi() pseudo op adding
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in the top bit of the lo() pseudo op, the movhi instruction actually
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stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
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stores 0xFFFFFFFF into r6 - the right value.
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@cindex @code{hilo} pseudo-op, V850
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@item hilo()
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Computes the 32 bit value of the given expression and stores it into
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the immediate operand field of the given instruction (which must be a
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mov instruction). For example:
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@samp{mov hilo(here), r6}
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computes the absolute address of label 'here' and puts the result into
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register 6.
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@cindex @code{sdaoff} pseudo-op, V850
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@item sdaoff()
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Computes the offset of the named variable from the start of the Small
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Data Area (whoes address is held in register 4, the GP register) and
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stores the result as a 16 bit signed value in the immediate operand
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field of the given instruction. For example:
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@samp{ld.w sdaoff(_a_variable)[gp],r6}
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loads the contents of the location pointed to by the label '_a_variable'
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into register 6, provided that the label is located somewhere within +/-
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32K of the address held in the GP register. [Note the linker assumes
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that the GP register contains a fixed address set to the address of the
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label called '__gp'. This can either be set up automatically by the
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linker, or specifically set by using the @samp{--defsym __gp=<value>}
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command line option].
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@cindex @code{tdaoff} pseudo-op, V850
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@item tdaoff()
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Computes the offset of the named variable from the start of the Tiny
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Data Area (whoes address is held in register 30, the EP register) and
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stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
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operand field of the given instruction. For example:
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@samp{sld.w tdaoff(_a_variable)[ep],r6}
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loads the contents of the location pointed to by the label '_a_variable'
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into register 6, provided that the label is located somewhere within +256
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bytes of the address held in the EP register. [Note the linker assumes
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that the EP register contains a fixed address set to the address of the
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label called '__ep'. This can either be set up automatically by the
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linker, or specifically set by using the @samp{--defsym __ep=<value>}
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command line option].
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@cindex @code{zdaoff} pseudo-op, V850
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@item zdaoff()
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Computes the offset of the named variable from address 0 and stores the
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result as a 16 bit signed value in the immediate operand field of the
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given instruction. For example:
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@samp{movea zdaoff(_a_variable),zero,r6}
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puts the address of the label '_a_variable' into register 6, assuming
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that the label is somewhere within the first 32K of memory. (Strictly
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speaking it also possible to access the last 32K of memory as well, as
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the offsets are signed).
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@cindex @code{ctoff} pseudo-op, V850
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@item ctoff()
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Computes the offset of the named variable from the start of the Call
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Table Area (whoes address is helg in system register 20, the CTBP
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register) and stores the result a 6 or 16 bit unsigned value in the
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immediate field of then given instruction or piece of data. For
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example:
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@samp{callt ctoff(table_func1)}
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will put the call the function whoes address is held in the call table
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at the location labeled 'table_func1'.
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@cindex @code{longcall} pseudo-op, V850
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@item .longcall @code{name}
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Indicates that the following sequence of instructions is a long call
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to function @code{name}. The linker will attempt to shorten this call
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sequence if @code{name} is within a 22bit offset of the call. Only
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valid if the @code{-mrelax} command line switch has been enabled.
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@cindex @code{longjump} pseudo-op, V850
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@item .longjump @code{name}
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Indicates that the following sequence of instructions is a long jump
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to label @code{name}. The linker will attempt to shorten this code
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sequence if @code{name} is within a 22bit offset of the jump. Only
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valid if the @code{-mrelax} command line switch has been enabled.
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@end table
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For information on the V850 instruction set, see @cite{V850
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Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.
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Ltd.
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