727 lines
17 KiB
C
727 lines
17 KiB
C
/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
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Copyright 2002 Free Software Foundation, Inc.
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Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <math.h>
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#include "libiberty.h"
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#include "dis-asm.h"
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#include "opcode/tic4x.h"
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#define C4X_DEBUG 0
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#define C4X_HASH_SIZE 11 /* 11 and above should give unique entries. */
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typedef enum
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{
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IMMED_SINT,
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IMMED_SUINT,
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IMMED_SFLOAT,
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IMMED_INT,
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IMMED_UINT,
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IMMED_FLOAT
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}
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immed_t;
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typedef enum
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{
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INDIRECT_SHORT,
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INDIRECT_LONG,
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INDIRECT_C4X
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}
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indirect_t;
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static int c4x_version = 0;
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static int c4x_dp = 0;
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static int c4x_pc_offset
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PARAMS ((unsigned int));
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static int c4x_print_char
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PARAMS ((struct disassemble_info *, char));
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static int c4x_print_str
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PARAMS ((struct disassemble_info *, char *));
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static int c4x_print_register
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PARAMS ((struct disassemble_info *, unsigned long));
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static int c4x_print_addr
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PARAMS ((struct disassemble_info *, unsigned long));
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static int c4x_print_relative
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PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
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void c4x_print_ftoa
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PARAMS ((unsigned int, FILE *, fprintf_ftype));
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static int c4x_print_direct
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PARAMS ((struct disassemble_info *, unsigned long));
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static int c4x_print_immed
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PARAMS ((struct disassemble_info *, immed_t, unsigned long));
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static int c4x_print_cond
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PARAMS ((struct disassemble_info *, unsigned int));
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static int c4x_print_indirect
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PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
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static int c4x_print_op
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PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
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static void c4x_hash_opcode
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PARAMS ((c4x_inst_t **, const c4x_inst_t *));
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static int c4x_disassemble
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PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
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int print_insn_tic4x
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PARAMS ((bfd_vma, struct disassemble_info *));
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static int
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c4x_pc_offset (op)
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unsigned int op;
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{
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/* Determine the PC offset for a C[34]x instruction.
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This could be simplified using some boolean algebra
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but at the expense of readability. */
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switch (op >> 24)
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{
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case 0x60: /* br */
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case 0x62: /* call (C4x) */
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case 0x64: /* rptb (C4x) */
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return 1;
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case 0x61: /* brd */
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case 0x63: /* laj */
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case 0x65: /* rptbd (C4x) */
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return 3;
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case 0x66: /* swi */
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case 0x67:
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return 0;
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default:
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break;
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}
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switch ((op & 0xffe00000) >> 20)
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{
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case 0x6a0: /* bB */
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case 0x720: /* callB */
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case 0x740: /* trapB */
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return 1;
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case 0x6a2: /* bBd */
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case 0x6a6: /* bBat */
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case 0x6aa: /* bBaf */
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case 0x722: /* lajB */
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case 0x748: /* latB */
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case 0x798: /* rptbd */
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return 3;
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default:
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break;
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}
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switch ((op & 0xfe200000) >> 20)
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{
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case 0x6e0: /* dbB */
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return 1;
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case 0x6e2: /* dbBd */
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return 3;
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default:
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break;
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}
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return 0;
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}
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static int
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c4x_print_char (info, ch)
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struct disassemble_info * info;
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char ch;
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{
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if (info != NULL)
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(*info->fprintf_func) (info->stream, "%c", ch);
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return 1;
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}
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static int
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c4x_print_str (info, str)
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struct disassemble_info *info;
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char *str;
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{
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if (info != NULL)
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(*info->fprintf_func) (info->stream, "%s", str);
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return 1;
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}
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static int
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c4x_print_register (info, regno)
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struct disassemble_info *info;
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unsigned long regno;
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{
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static c4x_register_t **registertable = NULL;
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unsigned int i;
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if (registertable == NULL)
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{
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registertable = (c4x_register_t **)
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xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE);
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for (i = 0; i < c3x_num_registers; i++)
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registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i];
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if (IS_CPU_C4X (c4x_version))
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{
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/* Add C4x additional registers, overwriting
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any C3x registers if necessary. */
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for (i = 0; i < c4x_num_registers; i++)
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registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i];
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}
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}
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if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX))
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return 0;
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if (info != NULL)
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(*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
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return 1;
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}
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static int
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c4x_print_addr (info, addr)
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struct disassemble_info *info;
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unsigned long addr;
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{
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if (info != NULL)
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(*info->print_address_func)(addr, info);
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return 1;
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}
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static int
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c4x_print_relative (info, pc, offset, opcode)
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struct disassemble_info *info;
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unsigned long pc;
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long offset;
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unsigned long opcode;
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{
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return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode));
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}
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static int
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c4x_print_direct (info, arg)
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struct disassemble_info *info;
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unsigned long arg;
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{
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if (info != NULL)
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{
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(*info->fprintf_func) (info->stream, "@");
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c4x_print_addr (info, arg + (c4x_dp << 16));
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}
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return 1;
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}
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/* FIXME: make the floating point stuff not rely on host
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floating point arithmetic. */
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void
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c4x_print_ftoa (val, stream, pfunc)
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unsigned int val;
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FILE *stream;
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fprintf_ftype pfunc;
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{
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int e;
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int s;
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int f;
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double num = 0.0;
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e = EXTRS (val, 31, 24); /* exponent */
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if (e != -128)
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{
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s = EXTRU (val, 23, 23); /* sign bit */
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f = EXTRU (val, 22, 0); /* mantissa */
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if (s)
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f += -2 * (1 << 23);
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else
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f += (1 << 23);
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num = f / (double)(1 << 23);
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num = ldexp (num, e);
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}
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(*pfunc)(stream, "%.9g", num);
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}
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static int
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c4x_print_immed (info, type, arg)
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struct disassemble_info *info;
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immed_t type;
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unsigned long arg;
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{
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int s;
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int f;
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int e;
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double num = 0.0;
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if (info == NULL)
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return 1;
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switch (type)
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{
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case IMMED_SINT:
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case IMMED_INT:
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(*info->fprintf_func) (info->stream, "%d", (long)arg);
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break;
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case IMMED_SUINT:
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case IMMED_UINT:
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(*info->fprintf_func) (info->stream, "%u", arg);
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break;
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case IMMED_SFLOAT:
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e = EXTRS (arg, 15, 12);
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if (e != -8)
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{
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s = EXTRU (arg, 11, 11);
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f = EXTRU (arg, 10, 0);
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if (s)
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f += -2 * (1 << 11);
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else
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f += (1 << 11);
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num = f / (double)(1 << 11);
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num = ldexp (num, e);
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}
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(*info->fprintf_func) (info->stream, "%f", num);
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break;
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case IMMED_FLOAT:
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e = EXTRS (arg, 31, 24);
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if (e != -128)
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{
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s = EXTRU (arg, 23, 23);
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f = EXTRU (arg, 22, 0);
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if (s)
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f += -2 * (1 << 23);
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else
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f += (1 << 23);
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num = f / (double)(1 << 23);
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num = ldexp (num, e);
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}
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(*info->fprintf_func) (info->stream, "%f", num);
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break;
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}
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return 1;
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}
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static int
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c4x_print_cond (info, cond)
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struct disassemble_info *info;
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unsigned int cond;
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{
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static c4x_cond_t **condtable = NULL;
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unsigned int i;
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if (condtable == NULL)
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{
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condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32);
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for (i = 0; i < num_conds; i++)
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condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i];
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}
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if (cond > 31 || condtable[cond] == NULL)
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return 0;
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if (info != NULL)
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(*info->fprintf_func) (info->stream, "%s", condtable[cond]->name);
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return 1;
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}
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static int
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c4x_print_indirect (info, type, arg)
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struct disassemble_info *info;
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indirect_t type;
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unsigned long arg;
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{
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unsigned int aregno;
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unsigned int modn;
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unsigned int disp;
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char *a;
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aregno = 0;
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modn = 0;
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disp = 1;
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switch(type)
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{
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case INDIRECT_C4X: /* *+ARn(disp) */
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disp = EXTRU (arg, 7, 3);
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aregno = EXTRU (arg, 2, 0) + REG_AR0;
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modn = 0;
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break;
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case INDIRECT_SHORT:
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disp = 1;
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aregno = EXTRU (arg, 2, 0) + REG_AR0;
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modn = EXTRU (arg, 7, 3);
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break;
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case INDIRECT_LONG:
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disp = EXTRU (arg, 7, 0);
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aregno = EXTRU (arg, 10, 8) + REG_AR0;
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modn = EXTRU (arg, 15, 11);
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if (modn > 7 && disp != 0)
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return 0;
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break;
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default:
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abort ();
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}
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if (modn > C3X_MODN_MAX)
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return 0;
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a = c4x_indirects[modn].name;
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while (*a)
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{
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switch (*a)
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{
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case 'a':
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c4x_print_register (info, aregno);
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break;
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case 'd':
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c4x_print_immed (info, IMMED_UINT, disp);
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break;
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case 'y':
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c4x_print_str (info, "ir0");
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break;
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case 'z':
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c4x_print_str (info, "ir1");
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break;
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default:
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c4x_print_char (info, *a);
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break;
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}
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a++;
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}
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return 1;
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}
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static int
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c4x_print_op (info, instruction, p, pc)
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struct disassemble_info *info;
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unsigned long instruction;
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c4x_inst_t *p;
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unsigned long pc;
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{
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int val;
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char *s;
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char *parallel = NULL;
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/* Print instruction name. */
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s = p->name;
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while (*s && parallel == NULL)
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{
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switch (*s)
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{
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case 'B':
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if (! c4x_print_cond (info, EXTRU (instruction, 20, 16)))
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return 0;
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break;
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case 'C':
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if (! c4x_print_cond (info, EXTRU (instruction, 27, 23)))
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return 0;
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break;
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case '_':
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parallel = s + 1; /* Skip past `_' in name */
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break;
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default:
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c4x_print_char (info, *s);
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break;
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}
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s++;
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}
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/* Print arguments. */
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s = p->args;
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if (*s)
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c4x_print_char (info, ' ');
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while (*s)
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{
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switch (*s)
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{
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case '*': /* indirect 0--15 */
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if (! c4x_print_indirect (info, INDIRECT_LONG,
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EXTRU (instruction, 15, 0)))
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return 0;
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break;
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case '#': /* only used for ldp, ldpk */
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c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
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break;
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case '@': /* direct 0--15 */
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c4x_print_direct (info, EXTRU (instruction, 15, 0));
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break;
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case 'A': /* address register 24--22 */
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if (! c4x_print_register (info, EXTRU (instruction, 24, 22) +
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REG_AR0))
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return 0;
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break;
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case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
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address 0--23. */
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if (IS_CPU_C4X (c4x_version))
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c4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
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p->opcode);
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else
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c4x_print_addr (info, EXTRU (instruction, 23, 0));
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break;
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case 'C': /* indirect (short C4x) 0--7 */
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if (! IS_CPU_C4X (c4x_version))
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return 0;
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if (! c4x_print_indirect (info, INDIRECT_C4X,
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EXTRU (instruction, 7, 0)))
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return 0;
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break;
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case 'D':
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/* Cockup if get here... */
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break;
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case 'E': /* register 0--7 */
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if (! c4x_print_register (info, EXTRU (instruction, 7, 0)))
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return 0;
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break;
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case 'F': /* 16-bit float immediate 0--15 */
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c4x_print_immed (info, IMMED_SFLOAT,
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EXTRU (instruction, 15, 0));
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break;
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case 'I': /* indirect (short) 0--7 */
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if (! c4x_print_indirect (info, INDIRECT_SHORT,
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EXTRU (instruction, 7, 0)))
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return 0;
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break;
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case 'J': /* indirect (short) 8--15 */
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if (! c4x_print_indirect (info, INDIRECT_SHORT,
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EXTRU (instruction, 15, 8)))
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return 0;
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break;
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case 'G': /* register 8--15 */
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if (! c4x_print_register (info, EXTRU (instruction, 15, 8)))
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return 0;
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break;
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case 'H': /* register 16--18 */
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if (! c4x_print_register (info, EXTRU (instruction, 18, 16)))
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return 0;
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break;
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case 'K': /* register 19--21 */
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if (! c4x_print_register (info, EXTRU (instruction, 21, 19)))
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return 0;
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break;
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case 'L': /* register 22--24 */
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if (! c4x_print_register (info, EXTRU (instruction, 24, 22)))
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return 0;
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break;
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case 'M': /* register 22--22 */
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c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
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break;
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case 'N': /* register 23--23 */
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c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R0);
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break;
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case 'O': /* indirect (short C4x) 8--15 */
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if (! IS_CPU_C4X (c4x_version))
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return 0;
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if (! c4x_print_indirect (info, INDIRECT_C4X,
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EXTRU (instruction, 15, 8)))
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return 0;
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break;
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case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
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c4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
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p->opcode);
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break;
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case 'Q': /* register 0--15 */
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if (! c4x_print_register (info, EXTRU (instruction, 15, 0)))
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return 0;
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break;
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case 'R': /* register 16--20 */
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if (! c4x_print_register (info, EXTRU (instruction, 20, 16)))
|
|
return 0;
|
|
break;
|
|
|
|
case 'S': /* 16-bit signed immediate 0--15 */
|
|
c4x_print_immed (info, IMMED_SINT,
|
|
EXTRS (instruction, 15, 0));
|
|
break;
|
|
|
|
case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
|
|
if (! IS_CPU_C4X (c4x_version))
|
|
return 0;
|
|
if (! c4x_print_immed (info, IMMED_SUINT,
|
|
EXTRU (instruction, 20, 16)))
|
|
return 0;
|
|
break;
|
|
|
|
case 'U': /* 16-bit unsigned int immediate 0--15 */
|
|
c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
|
|
break;
|
|
|
|
case 'V': /* 5/9-bit unsigned vector 0--4/8 */
|
|
c4x_print_immed (info, IMMED_SUINT,
|
|
IS_CPU_C4X (c4x_version) ?
|
|
EXTRU (instruction, 8, 0) :
|
|
EXTRU (instruction, 4, 0) & ~0x20);
|
|
break;
|
|
|
|
case 'W': /* 8-bit signed immediate 0--7 */
|
|
if (! IS_CPU_C4X (c4x_version))
|
|
return 0;
|
|
c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
|
|
break;
|
|
|
|
case 'X': /* expansion register 4--0 */
|
|
val = EXTRU (instruction, 4, 0) + REG_IVTP;
|
|
if (val < REG_IVTP || val > REG_TVTP)
|
|
return 0;
|
|
if (! c4x_print_register (info, val))
|
|
return 0;
|
|
break;
|
|
|
|
case 'Y': /* address register 16--20 */
|
|
val = EXTRU (instruction, 20, 16);
|
|
if (val < REG_AR0 || val > REG_SP)
|
|
return 0;
|
|
if (! c4x_print_register (info, val))
|
|
return 0;
|
|
break;
|
|
|
|
case 'Z': /* expansion register 16--20 */
|
|
val = EXTRU (instruction, 20, 16) + REG_IVTP;
|
|
if (val < REG_IVTP || val > REG_TVTP)
|
|
return 0;
|
|
if (! c4x_print_register (info, val))
|
|
return 0;
|
|
break;
|
|
|
|
case '|': /* Parallel instruction */
|
|
c4x_print_str (info, " || ");
|
|
c4x_print_str (info, parallel);
|
|
c4x_print_char (info, ' ');
|
|
break;
|
|
|
|
case ';':
|
|
c4x_print_char (info, ',');
|
|
break;
|
|
|
|
default:
|
|
c4x_print_char (info, *s);
|
|
break;
|
|
}
|
|
s++;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
c4x_hash_opcode (optable, inst)
|
|
c4x_inst_t **optable;
|
|
const c4x_inst_t *inst;
|
|
{
|
|
int j;
|
|
int opcode = inst->opcode >> (32 - C4X_HASH_SIZE);
|
|
int opmask = inst->opmask >> (32 - C4X_HASH_SIZE);
|
|
|
|
/* Use a C4X_HASH_SIZE bit index as a hash index. We should
|
|
have unique entries so there's no point having a linked list
|
|
for each entry? */
|
|
for (j = opcode; j < opmask; j++)
|
|
if ((j & opmask) == opcode)
|
|
{
|
|
#if C4X_DEBUG
|
|
/* We should only have collisions for synonyms like
|
|
ldp for ldi. */
|
|
if (optable[j] != NULL)
|
|
printf("Collision at index %d, %s and %s\n",
|
|
j, optable[j]->name, inst->name);
|
|
#endif
|
|
optable[j] = (void *)inst;
|
|
}
|
|
}
|
|
|
|
/* Disassemble the instruction in 'instruction'.
|
|
'pc' should be the address of this instruction, it will
|
|
be used to print the target address if this is a relative jump or call
|
|
the disassembled instruction is written to 'info'.
|
|
The function returns the length of this instruction in words. */
|
|
|
|
static int
|
|
c4x_disassemble (pc, instruction, info)
|
|
unsigned long pc;
|
|
unsigned long instruction;
|
|
struct disassemble_info *info;
|
|
{
|
|
static c4x_inst_t **optable = NULL;
|
|
c4x_inst_t *p;
|
|
int i;
|
|
|
|
c4x_version = info->mach;
|
|
|
|
if (optable == NULL)
|
|
{
|
|
optable = (c4x_inst_t **)
|
|
xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE));
|
|
/* Install opcodes in reverse order so that preferred
|
|
forms overwrite synonyms. */
|
|
for (i = c3x_num_insts - 1; i >= 0; i--)
|
|
c4x_hash_opcode (optable, &c3x_insts[i]);
|
|
if (IS_CPU_C4X (c4x_version))
|
|
{
|
|
for (i = c4x_num_insts - 1; i >= 0; i--)
|
|
c4x_hash_opcode (optable, &c4x_insts[i]);
|
|
}
|
|
}
|
|
|
|
/* See if we can pick up any loading of the DP register... */
|
|
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
|
|
c4x_dp = EXTRU (instruction, 15, 0);
|
|
|
|
p = optable[instruction >> (32 - C4X_HASH_SIZE)];
|
|
if (p != NULL && ((instruction & p->opmask) == p->opcode)
|
|
&& c4x_print_op (NULL, instruction, p, pc))
|
|
c4x_print_op (info, instruction, p, pc);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
|
|
|
/* Return size of insn in words. */
|
|
return 1;
|
|
}
|
|
|
|
/* The entry point from objdump and gdb. */
|
|
int
|
|
print_insn_tic4x (memaddr, info)
|
|
bfd_vma memaddr;
|
|
struct disassemble_info *info;
|
|
{
|
|
int status;
|
|
unsigned long pc;
|
|
unsigned long op;
|
|
bfd_byte buffer[4];
|
|
|
|
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
|
|
pc = memaddr;
|
|
op = bfd_getl32 (buffer);
|
|
info->bytes_per_line = 4;
|
|
info->bytes_per_chunk = 4;
|
|
info->octets_per_byte = 4;
|
|
info->display_endian = BFD_ENDIAN_LITTLE;
|
|
return c4x_disassemble (pc, op, info) * 4;
|
|
}
|