b4e87f2c1e
We currently use a padding NOP after a Thumb to Arm interworking veneer (BX pc). The NOP is never executed but may result in a performance penalty on some cores. For this reason this patch changes the NOPs after Thumb to Arm veneers into B .-2 and adds a note to this in the source code for future reference. bfd/ChangeLog: * elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub, elf32_arm_stub_long_branch_v4t_thumb_thumb, elf32_arm_stub_long_branch_v4t_thumb_arm, elf32_arm_stub_short_branch_v4t_thumb_arm, elf32_arm_stub_long_branch_v4t_thumb_arm_pic, elf32_arm_stub_long_branch_v4t_thumb_thumb_pic, elf32_arm_stub_long_branch_v4t_thumb_tls_pic): Change nop to branch to previous instruction. ld/ChangeLog: * testsuite/ld-arm/cortex-a8-fix-b-plt.d: Update Testcase. * testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * testsuite/ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * testsuite/ld-arm/farcall-cond-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-mixed-app.d: Likewise. * testsuite/ld-arm/farcall-mixed-app2.d: Likewise. * testsuite/ld-arm/farcall-mixed-lib-v4t.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * testsuite/ld-arm/fix-arm1176-on.d: Likewise. * testsuite/ld-arm/ifunc-10.dd: Likewise. * testsuite/ld-arm/ifunc-2.dd: Likewise. * testsuite/ld-arm/ifunc-4.dd: Likewise. * testsuite/ld-arm/ifunc-6.dd: Likewise. * testsuite/ld-arm/ifunc-8.dd: Likewise. * testsuite/ld-arm/jump-reloc-veneers-long.d: Likewise. * testsuite/ld-arm/mixed-app.d: Likewise. * testsuite/ld-arm/thumb2-b-interwork.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise. * testsuite/ld-arm/tls-thumb1.d: Likewise.
120 lines
3.3 KiB
Makefile
120 lines
3.3 KiB
Makefile
tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm
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architecture: arm.*, flags 0x00000150:
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HAS_SYMS, DYNAMIC, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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.* <.plt>:
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.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
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.*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
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.*: e08fe00e add lr, pc, lr
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.*: e5bef008 ldr pc, \[lr, #8\]!
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.*: .* .word .*
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.* <app_func@plt>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]! ; .*
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.* <app_func_weak@plt>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
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.* <lib_func3@plt>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
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.* <lib_func4@plt>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
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Disassembly of section .text:
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.* <lib_func1>:
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.*: e1a0c00d mov ip, sp
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.*: e92dd800 push {fp, ip, lr, pc}
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.*: ebffff.. bl .* <app_func@plt\+0x.*>
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.*: ebffff.. bl .* <app_func_weak@plt\+0x.*>
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.*: ebffff.. bl .* <lib_func3@plt\+0x.*>
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.*: ebffff.. bl .* <lib_func4@plt\+0x.*>
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.*: e89d6800 ldm sp, {fp, sp, lr}
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.*: e12fff1e bx lr
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...
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.* <__real_lib_func2>:
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.*: f000 f8.. bl .* <__app_func_from_thumb>
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.*: f000 f8.. bl .* <__app_func_weak_from_thumb>
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.*: f000 f8.. bl .* <__lib_func3_from_thumb>
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.*: f000 f8.. bl .* <__lib_func4_from_thumb>
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.*: 4770 bx lr
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#...
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.* <__app_func_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: feffff.. .word 0xfeffff..
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.* <__lib_func4_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: feffff.. .word 0xfeffff..
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.* <__app_func_weak_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: feffff.. .word 0xfeffff..
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.* <__lib_func3_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: feffff.. .word 0xfeffff..
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...
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.* <__real_lib_func3>:
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.*: f000 f80(e|6) bl .* <__app_func_from_thumb>
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.*: f000 f80(4|c) bl .* <__app_func_weak_from_thumb>
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.*: 4770 bx lr
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#...
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.* <__app_func_weak_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: fdffff34 .word 0xfdffff34
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.* <__app_func_from_thumb>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
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.*: e08cf00f add pc, ip, pc
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.*: fdffff14 .word 0xfdffff14
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.* <lib_func3>:
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.*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func3\+0xc>
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.*: e08cc00f add ip, ip, pc
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.*: e12fff1c bx ip
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.*: ffffffc5 .word 0xffffffc5
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.* <lib_func2>:
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.*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
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.*: e08cc00f add ip, ip, pc
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.*: e12fff1c bx ip
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.*: feffff55 .word 0xfeffff55
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