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Nelson Chu 08ccfccf0e RISC-V: Support debug and float CSR as the unprivileged ones. 
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec.  For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec.  User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly.  Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them.  However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.

	gas/
	* config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
	checking into riscv_csr_address.
	(riscv_csr_version_check): Likewise.
	(riscv_csr_address): New function.  Return the suitable CSR address
	after checking the ISA dependency and versions.  Issue warnings	if
	we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
	CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
	priv spec versions for them.
	(reg_csr_lookup_internal): Call riscv_csr_address to find the
	suitable CSR address.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
	priv spec warnings here.  These warnings are added by accident.
	Remove them and only focus on the ISA dependency warnings.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
	dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
	than the privileged ones.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Support the unprivileged CSR.  The versions
	of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
	* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.

	opcodes/
	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
	unprivileged CSR can also be initialized.
 		2020-06-30 09:54:55 +08:00
..
align-1.l Fix riscv malloc error on small alignment after norvc. 2017-11-29 10:36:46 -08:00
align-1.s Fix riscv malloc error on small alignment after norvc. 2017-11-29 10:36:46 -08:00
attribute-01.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-02.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-03.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-04.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-04.s RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
attribute-05.d [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
attribute-05.s [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
attribute-06.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-06.s RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
attribute-07.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-07.s RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
attribute-08.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-08.s RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
attribute-09.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-10.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-11.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-11.s RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-12.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-13.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-14.s RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-14a.d RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-14b.d RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-14c.d RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-14d.d RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-14e.d RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 2020-06-23 09:38:12 +08:00
attribute-empty.d Don't emit vendor attribute section if there is no attribute to emit. 2019-01-16 13:37:35 -08:00
attribute-unknown.d RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 2020-06-05 12:14:44 +08:00
attribute-unknown.s RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
auipc-parsing.d RISC-V: Don't segfault for two regs in auipc or lui. 2018-12-10 16:40:46 -08:00
auipc-parsing.l RISC-V: Fix lui argument parsing. 2019-05-30 15:23:10 -07:00
auipc-parsing.s RISC-V: Fix lui argument parsing. 2019-05-30 15:23:10 -07:00
auipc-x0.d RISC-V: Disassemble x0 based addresses as 0. 2018-01-09 16:40:06 -08:00
auipc-x0.s RISC-V: Disassemble x0 based addresses as 0. 2018-01-09 16:40:06 -08:00
bge.d RISC-V: bge[u] should get higher priority than ble[u]. 2018-09-17 11:43:08 -07:00
bge.s RISC-V: bge[u] should get higher priority than ble[u]. 2018-09-17 11:43:08 -07:00
c-add-addi.d RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. 2020-02-19 14:51:07 -08:00
c-add-addi.s RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. 2020-02-19 14:51:07 -08:00
c-addi4spn-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-addi4spn-fail.l RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi4spn-fail.s RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi16sp-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-addi16sp-fail.l RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi16sp-fail.s RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-fld-fsd-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-fld-fsd-fail.l RISC-V: Correct the requirement of compressed floating point instructions 2018-08-31 12:23:05 -07:00
c-fld-fsd-fail.s RISC-V: Correct the requirement of compressed floating point instructions 2018-08-31 12:23:05 -07:00
c-ld.d Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-ld.s Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-lui-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-lui-fail.l RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 2017-10-24 08:02:46 -07:00
c-lui-fail.s RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 2017-10-24 08:02:46 -07:00
c-lw.d Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-lw.s Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-nonzero-imm.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-nonzero-imm.l RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-nonzero-imm.s RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-nonzero-reg.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
c-nonzero-reg.l RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-nonzero-reg.s RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-zero-imm-64.d RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-zero-imm-64.s RISC-V: Add compressed instruction hints, and a few misc cleanups. 2017-12-20 13:37:44 -08:00
c-zero-imm.d RISC-V: Add missing hint instructions from RV128I. 2018-05-08 15:46:19 -07:00
c-zero-imm.s RISC-V: Add missing hint instructions from RV128I. 2018-05-08 15:46:19 -07:00
c-zero-reg.d RISC-V: Add missing hint instructions from RV128I. 2018-05-08 15:46:19 -07:00
c-zero-reg.s RISC-V: Add missing hint instructions from RV128I. 2018-05-08 15:46:19 -07:00
cie-rtn-col-1.d gas: Check for overflow on return column in version 1 CIE DWARF 2019-11-28 00:03:05 +00:00
cie-rtn-col-3.d gas: Check for overflow on return column in version 1 CIE DWARF 2019-11-28 00:03:05 +00:00
cie-rtn-col.s gas: Check for overflow on return column in version 1 CIE DWARF 2019-11-28 00:03:05 +00:00
csr-dw-regnums.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
csr-dw-regnums.s RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
default-cie-version.d gas/riscv: Produce version 3 DWARF CIE by default 2019-11-28 00:03:05 +00:00
default-cie-version.s gas/riscv: Produce version 3 DWARF CIE by default 2019-11-28 00:03:05 +00:00
eh-relocs.d RISC-V: Fix riscv g++ testsuite EH failures. 2017-11-07 09:13:52 -08:00
eh-relocs.s RISC-V: Fix riscv g++ testsuite EH failures. 2017-11-07 09:13:52 -08:00
empty.l RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 13:14:59 -08:00
empty.s RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
fence-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
fence-fail.l RISC-V: Reject empty rouding mode and fence operand. 2018-08-23 13:26:48 -07:00
fence-fail.s RISC-V: Reject empty rouding mode and fence operand. 2018-08-23 13:26:48 -07:00
fence-tso.d RISC-V: Add fence.tso instruction 2018-10-02 08:26:32 -07:00
fence-tso.s RISC-V: Add fence.tso instruction 2018-10-02 08:26:32 -07:00
fmv.x.d Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. 2017-09-27 16:21:36 +01:00
fmv.x.s Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. 2017-09-27 16:21:36 +01:00
fsxxi.d Add missing RISC-V fsrmi and fsflagsi instructions. 2017-12-13 14:59:42 -08:00
fsxxi.s Add missing RISC-V fsrmi and fsflagsi instructions. 2017-12-13 14:59:42 -08:00
insn.d RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive. 2019-11-12 16:13:00 -08:00
insn.s Kito's 5-part patch set to improve .insn support. 2019-07-05 15:19:11 +08:00
li32.d RISC-V: Improve li expansion for better code density. 2019-08-25 19:16:43 -07:00
li32.s RISC-V: Improve li expansion for better code density. 2019-08-25 19:16:43 -07:00
li64.d RISC-V: Improve li expansion for better code density. 2019-08-25 19:16:43 -07:00
li64.s RISC-V: Improve li expansion for better code density. 2019-08-25 19:16:43 -07:00
lla32.d RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
lla32.s RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
lla64-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
lla64-fail.l RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
lla64-fail.s RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
lla64.d RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
lla64.s RISC-V: Accept constant operands in la and lla 2018-06-20 07:24:25 +02:00
march-fail-rv32ef.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32ef.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32i.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32i.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32iam.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32iam.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32ic.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32ic.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32icx2p.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32icx2p.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32imc.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv32imc.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv64I.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv64I.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv64e.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-rv64e.l RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-fail-s-with-version.d RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-fail-s-with-version.l RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-fail-s.d RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-fail-s.l RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-fail-sx.d RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-fail-sx.l RISC-V: Change -march parsing. 2020-01-22 16:45:04 -08:00
march-ok-g2.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-g2_p1.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-g2p0.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-i2p0.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-i2p0m2_a2f2.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-nse-with-version.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
march-ok-two-nse.d RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
no-relax-align-2.d RISC-V: Fix .align handling when .option norelax. 2018-05-24 10:35:59 -07:00
no-relax-align-2.s RISC-V: Fix .align handling when .option norelax. 2018-05-24 10:35:59 -07:00
no-relax-align.d RISC-V: Fix .align handling when .option norelax. 2018-05-24 10:35:59 -07:00
no-relax-align.s RISC-V: Fix .align handling when .option norelax. 2018-05-24 10:35:59 -07:00
no-relax-reloc.d RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 17:11:37 -08:00
no-relax-reloc.s RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 17:11:37 -08:00
priv-reg-fail-fext.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-fext.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-nonexistent.d RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-fail-nonexistent.l RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-fail-nonexistent.s RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-fail-read-only-01.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-read-only-01.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-read-only-01.s [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
priv-reg-fail-read-only-02.d [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
priv-reg-fail-read-only-02.l RISC-V: Support the read-only CSR checking. 2020-02-20 16:49:09 -08:00
priv-reg-fail-read-only-02.s RISC-V: Support the read-only CSR checking. 2020-02-20 16:49:09 -08:00
priv-reg-fail-rv32-only.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-rv32-only.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-version-1p9p1.d [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
priv-reg-fail-version-1p9p1.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-version-1p10.d [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
priv-reg-fail-version-1p10.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-fail-version-1p11.d [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 2020-05-20 17:22:48 +01:00
priv-reg-fail-version-1p11.l RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-pseudo-noalias.d RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-pseudo.d RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-pseudo.s RISC-V: Update CSR to privileged spec 1.11. 2020-03-30 12:24:53 -07:00
priv-reg-version-1p9p1.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-version-1p10.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg-version-1p11.d RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
priv-reg.s RISC-V: Support debug and float CSR as the unprivileged ones. 2020-06-30 09:54:55 +08:00
relax-reloc.d RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 17:11:37 -08:00
relax-reloc.s RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 17:11:37 -08:00
riscv.exp Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
rouding-fail.d gas run_dump_test rename stderr and error-output 2018-09-15 16:24:18 +09:30
rouding-fail.l RISC-V: Reject empty rouding mode and fence operand. 2018-08-23 13:26:48 -07:00
rouding-fail.s RISC-V: Reject empty rouding mode and fence operand. 2018-08-23 13:26:48 -07:00
t_insns.d
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t_insns.s
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tprel-add.d RISC-V: Fix 4-arg add parsing. 2018-12-07 12:31:05 -08:00
tprel-add.l RISC-V: Fix 4-arg add parsing. 2018-12-07 12:31:05 -08:00
tprel-add.s RISC-V: Fix 4-arg add parsing. 2018-12-07 12:31:05 -08:00