313 lines
8.5 KiB
C
313 lines
8.5 KiB
C
/* The CRIS interrupt framework for GDB, the GNU Debugger.
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Copyright 2006-2015 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "hw-main.h"
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/* DEVICE
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CRIS cpu virtual device (very rudimental; generic enough for all
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currently used CRIS versions).
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DESCRIPTION
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Implements the external CRIS functionality. This includes the
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delivery of interrupts generated from other devices.
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PROPERTIES
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vec-for-int = <int-a> <vec-a> <int-b> <vec-b> ...
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These are the translations to interrupt vector for values appearing
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on the "int" port, as pairs of the value and the corresponding
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vector. Defaults to no translation. All values that may appear on
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the "int" port must be defined, or the device aborts.
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multiple-int = ("abort" | "ignore_previous" | <vector>)
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If multiple interrupt values are dispatched, this property decides
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what to do. The value is either a number corresponding to the
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vector to use, or the string "abort" to cause a hard abort, or the
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string "ignore_previous", to silently use the new vector instead.
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The default is "abort".
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PORTS
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int (input)
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Interrupt port. An event with a non-zero value on this port causes
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an interrupt. If, after an event but before the interrupt has been
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properly dispatched, a non-zero value appears that is different
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after mapping than the previous, then the property multiple_int
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decides what to do.
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FIXME: reg port so internal registers can be read. Requires
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chip-specific versions, though. Ports "nmi" and "reset".
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BUGS
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When delivering an interrupt, this code assumes that there is only
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one processor (number 0).
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This code does not attempt to be efficient at handling pending
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interrupts. It simply schedules the interrupt delivery handler
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every instruction cycle until all pending interrupts go away.
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It also works around a bug in sim_events_process when doing so.
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*/
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/* Keep this an enum for simple addition of "reset" and "nmi". */
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enum
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{
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INT_PORT,
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};
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static const struct hw_port_descriptor cris_ports[] =
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{
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{ "int", INT_PORT, 0, input_port },
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{ NULL, 0, 0, 0 }
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};
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struct cris_vec_tr
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{
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unsigned32 portval, vec;
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};
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enum cris_multiple_ints
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{
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cris_multint_abort,
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cris_multint_ignore_previous,
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cris_multint_vector
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};
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struct cris_hw
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{
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struct hw_event *pending_handler;
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unsigned32 pending_vector;
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struct cris_vec_tr *int_to_vec;
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enum cris_multiple_ints multi_int_action;
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unsigned32 multiple_int_vector;
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};
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/* An event function, calling the actual CPU-model-specific
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interrupt-delivery function. */
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static void
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deliver_cris_interrupt (struct hw *me, void *data)
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{
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struct cris_hw *crishw = hw_data (me);
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SIM_DESC simulator = hw_system (me);
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sim_cpu *cpu = STATE_CPU (simulator, 0);
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unsigned int intno = crishw->pending_vector;
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if (CPU_CRIS_DELIVER_INTERRUPT (cpu) (cpu, CRIS_INT_INT, intno))
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{
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crishw->pending_vector = 0;
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crishw->pending_handler = NULL;
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return;
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}
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{
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/* Bug workaround: at time T with a pending number of cycles N to
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process, if re-scheduling an event at time T+M, M < N,
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sim_events_process gets stuck at T (updating the "time" to
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before the event rather than after the event, or somesuch).
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Hacking this locally is thankfully easy: if we see the same
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simulation time, increase the number of cycles. Do this every
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time we get here, until a new time is seen (supposedly unstuck
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re-delivery). (Fixing in SIM/GDB source will hopefully then
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also be easier, having a tangible test-case.) */
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static signed64 last_events_time = 0;
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static signed64 delta = 1;
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signed64 this_events_time = hw_event_queue_time (me);
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if (this_events_time == last_events_time)
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delta++;
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else
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{
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delta = 1;
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last_events_time = this_events_time;
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}
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crishw->pending_handler
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= hw_event_queue_schedule (me, delta, deliver_cris_interrupt, NULL);
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}
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}
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/* A port-event function for events arriving to an interrupt port. */
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static void
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cris_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int intparam)
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{
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struct cris_hw *crishw = hw_data (me);
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unsigned32 vec;
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/* A few placeholders; only the INT port is implemented. */
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switch (my_port)
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{
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case INT_PORT:
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HW_TRACE ((me, "INT value=0x%x", intparam));
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break;
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default:
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hw_abort (me, "bad switch");
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break;
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}
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if (intparam == 0)
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return;
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if (crishw->int_to_vec != NULL)
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{
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unsigned int i;
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for (i = 0; crishw->int_to_vec[i].portval != 0; i++)
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if (crishw->int_to_vec[i].portval == intparam)
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break;
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if (crishw->int_to_vec[i].portval == 0)
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hw_abort (me, "unsupported value for int port: 0x%x", intparam);
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vec = crishw->int_to_vec[i].vec;
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}
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else
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vec = (unsigned32) intparam;
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if (crishw->pending_vector != 0)
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{
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if (vec == crishw->pending_vector)
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return;
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switch (crishw->multi_int_action)
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{
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case cris_multint_abort:
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hw_abort (me, "int 0x%x (0x%x) while int 0x%x hasn't been delivered",
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vec, intparam, crishw->pending_vector);
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break;
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case cris_multint_ignore_previous:
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break;
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case cris_multint_vector:
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vec = crishw->multiple_int_vector;
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break;
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default:
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hw_abort (me, "bad switch");
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}
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}
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crishw->pending_vector = vec;
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/* Schedule our event handler *now*. */
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if (crishw->pending_handler == NULL)
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crishw->pending_handler
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= hw_event_queue_schedule (me, 0, deliver_cris_interrupt, NULL);
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}
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/* Instance initializer function. */
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static void
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cris_finish (struct hw *me)
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{
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struct cris_hw *crishw;
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const struct hw_property *vec_for_int;
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const struct hw_property *multiple_int;
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crishw = HW_ZALLOC (me, struct cris_hw);
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set_hw_data (me, crishw);
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set_hw_ports (me, cris_ports);
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set_hw_port_event (me, cris_port_event);
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vec_for_int = hw_find_property (me, "vec-for-int");
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if (vec_for_int != NULL)
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{
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unsigned32 vecsize;
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unsigned32 i;
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if (hw_property_type (vec_for_int) != array_property)
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hw_abort (me, "property \"vec-for-int\" has the wrong type");
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vecsize = hw_property_sizeof_array (vec_for_int) / sizeof (signed_cell);
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if ((vecsize % 2) != 0)
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hw_abort (me, "translation vector does not consist of even pairs");
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crishw->int_to_vec
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= hw_malloc (me, (vecsize/2 + 1) * sizeof (crishw->int_to_vec[0]));
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for (i = 0; i < vecsize/2; i++)
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{
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signed_cell portval_sc;
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signed_cell vec_sc;
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if (!hw_find_integer_array_property (me, "vec-for-int", i*2,
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&portval_sc)
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|| !hw_find_integer_array_property (me, "vec-for-int", i*2 + 1,
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&vec_sc)
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|| portval_sc < 0
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|| vec_sc < 0)
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hw_abort (me, "no valid vector translation pair %u", i);
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crishw->int_to_vec[i].portval = (unsigned32) portval_sc;
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crishw->int_to_vec[i].vec = (unsigned32) vec_sc;
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}
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crishw->int_to_vec[i].portval = 0;
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crishw->int_to_vec[i].vec = 0;
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}
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multiple_int = hw_find_property (me, "multiple-int");
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if (multiple_int != NULL)
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{
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if (hw_property_type (multiple_int) == integer_property)
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{
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crishw->multiple_int_vector
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= hw_find_integer_property (me, "multiple-int");
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crishw->multi_int_action = cris_multint_vector;
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}
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else
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{
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const char *action = hw_find_string_property (me, "multiple-int");
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if (action == NULL)
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hw_abort (me, "property \"multiple-int\" has the wrong type");
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if (strcmp (action, "abort") == 0)
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crishw->multi_int_action = cris_multint_abort;
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else if (strcmp (action, "ignore_previous") == 0)
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crishw->multi_int_action = cris_multint_ignore_previous;
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else
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hw_abort (me, "property \"multiple-int\" must be one of <vector number>\n"
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"\"abort\" and \"ignore_previous\", not \"%s\"", action);
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}
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}
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else
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crishw->multi_int_action = cris_multint_abort;
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}
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const struct hw_descriptor dv_cris_descriptor[] = {
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{ "cris", cris_finish, },
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{ NULL },
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};
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