354 lines
10 KiB
C
354 lines
10 KiB
C
/* The common simulator framework for GDB, the GNU Debugger.
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Copyright 2002, 2007, 2008, 2009 Free Software Foundation, Inc.
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Contributed by Andrew Cagney and Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_CORE_H
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#define SIM_CORE_H
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/* core signals (error conditions)
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Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
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details. */
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typedef enum {
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sim_core_unmapped_signal,
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sim_core_unaligned_signal,
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nr_sim_core_signals,
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} sim_core_signals;
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/* Type of SIM_CORE_SIGNAL handler. */
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typedef void (SIM_CORE_SIGNAL_FN)
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(SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
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address_word addr, transfer_type transfer, sim_core_signals sig);
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extern SIM_CORE_SIGNAL_FN sim_core_signal;
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/* basic types */
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typedef struct _sim_core_mapping sim_core_mapping;
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struct _sim_core_mapping {
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/* common */
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int level;
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int space;
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unsigned_word base;
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unsigned_word bound;
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unsigned_word nr_bytes;
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unsigned mask;
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/* memory map */
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void *free_buffer;
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void *buffer;
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/* callback map */
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#if (WITH_HW)
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struct hw *device;
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#else
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device *device;
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#endif
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/* tracing */
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int trace;
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/* growth */
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sim_core_mapping *next;
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};
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typedef struct _sim_core_map sim_core_map;
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struct _sim_core_map {
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sim_core_mapping *first;
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};
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typedef struct _sim_core_common {
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sim_core_map map[nr_maps];
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} sim_core_common;
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/* Main core structure */
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typedef struct _sim_core sim_core;
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struct _sim_core {
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sim_core_common common;
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address_word byte_xor; /* apply xor universally */
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};
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/* Per CPU distributed component of the core. At present this is
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mostly a clone of the global core data structure. */
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typedef struct _sim_cpu_core {
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sim_core_common common;
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address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
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} sim_cpu_core;
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/* Install the "core" module. */
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extern SIM_RC sim_core_install (SIM_DESC sd);
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/* Create a memory region within the core.
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CPU - when non NULL, specifes the single processor that the memory
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space is to be attached to. (INIMPLEMENTED).
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LEVEL - specifies the ordering of the memory region. Lower regions
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are searched first. Within a level, memory regions can not
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overlap.
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MAPMASK - Bitmask specifying the memory maps that the region is to
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be attached to. Typically the enums sim-basics.h:access_* are used.
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ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
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translated into ADDRESS_SPACE:OFFSET before being passed to the
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client device.
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MODULO - when the simulator has been configured WITH_MODULO support
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and is greater than zero, specifies that accesses to the region
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[ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
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.. ADDR+MODULO). The modulo value must be a power of two.
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DEVICE - When non NULL, indicates that this is a callback memory
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space and specified device's memory callback handler should be
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called.
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OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
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data read & written to the region. Normally a more efficient
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internal structure is used. It is assumed that buffer is allocated
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such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
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(OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
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hook that allows clients to do nasty things that the interface doesn't
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accomodate. */
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extern void sim_core_attach
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(SIM_DESC sd,
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sim_cpu *cpu,
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int level,
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unsigned mapmask,
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int address_space,
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address_word addr,
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address_word nr_bytes,
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unsigned modulo,
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#if (WITH_HW)
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struct hw *client,
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#else
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device *client,
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#endif
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void *optional_buffer);
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/* Delete a memory section within the core.
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*/
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extern void sim_core_detach
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(SIM_DESC sd,
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sim_cpu *cpu,
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int level,
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int address_space,
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address_word addr);
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/* Variable sized read/write
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Transfer a variable sized block of raw data between the host and
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target. Should any problems occur, the number of bytes
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successfully transfered is returned.
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No host/target byte endian conversion is performed. No xor-endian
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conversion is performed.
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If CPU argument, when non NULL, specifies the processor specific
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address map that is to be used in the transfer. */
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extern unsigned sim_core_read_buffer
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(SIM_DESC sd,
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sim_cpu *cpu,
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unsigned map,
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void *buffer,
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address_word addr,
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unsigned nr_bytes);
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extern unsigned sim_core_write_buffer
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(SIM_DESC sd,
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sim_cpu *cpu,
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unsigned map,
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const void *buffer,
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address_word addr,
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unsigned nr_bytes);
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/* Configure the core's XOR endian transfer mode. Only applicable
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when WITH_XOR_ENDIAN is enabled.
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Targets suporting XOR endian, shall notify the core of any changes
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in state via this call.
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The CPU argument, when non NULL, specifes the single processor that
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the xor-endian configuration is to be applied to. */
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extern void sim_core_set_xor
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(SIM_DESC sd,
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sim_cpu *cpu,
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int is_xor);
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/* XOR version of variable sized read/write.
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Transfer a variable sized block of raw data between the host and
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target. Should any problems occur, the number of bytes
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successfully transfered is returned.
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No host/target byte endian conversion is performed. If applicable
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(WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
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performed.
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If CPU argument, when non NULL, specifies the processor specific
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address map that is to be used in the transfer. */
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extern unsigned sim_core_xor_read_buffer
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(SIM_DESC sd,
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sim_cpu *cpu,
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unsigned map,
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void *buffer,
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address_word addr,
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unsigned nr_bytes);
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extern unsigned sim_core_xor_write_buffer
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(SIM_DESC sd,
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sim_cpu *cpu,
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unsigned map,
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const void *buffer,
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address_word addr,
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unsigned nr_bytes);
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/* Fixed sized, processor oriented, read/write.
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Transfer a fixed amout of memory between the host and target. The
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data transfered is translated from/to host to/from target byte
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order (including xor endian). Should the transfer fail, the
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operation shall abort (no return).
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ALIGNED assumes yhat the specified ADDRESS is correctly alligned
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for an N byte transfer (no alignment checks are made). Passing an
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incorrectly aligned ADDRESS is erroneous.
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UNALIGNED checks/modifies the ADDRESS according to the requirements
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of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
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taken should the check fail.
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MISSALIGNED transfers the data regardless.
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Misaligned xor-endian accesses are broken into a sequence of
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transfers each <= WITH_XOR_ENDIAN bytes */
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#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
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INLINE_SIM_CORE\
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(void) sim_core_write_##ALIGNMENT##_##N \
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(sim_cpu *cpu, \
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sim_cia cia, \
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unsigned map, \
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address_word addr, \
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unsigned_##M val);
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DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
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DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
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DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
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DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
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DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
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#define sim_core_write_unaligned_1 sim_core_write_aligned_1
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DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
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DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
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DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
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DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
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DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
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DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
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DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
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DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
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#define sim_core_write_1 sim_core_write_aligned_1
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#define sim_core_write_2 sim_core_write_aligned_2
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#define sim_core_write_4 sim_core_write_aligned_4
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#define sim_core_write_8 sim_core_write_aligned_8
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#define sim_core_write_16 sim_core_write_aligned_16
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#define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
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#define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
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#define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
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#undef DECLARE_SIM_CORE_WRITE_N
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#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
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INLINE_SIM_CORE\
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(unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
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(sim_cpu *cpu, \
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sim_cia cia, \
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unsigned map, \
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address_word addr);
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DECLARE_SIM_CORE_READ_N(aligned,1,1)
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DECLARE_SIM_CORE_READ_N(aligned,2,2)
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DECLARE_SIM_CORE_READ_N(aligned,4,4)
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DECLARE_SIM_CORE_READ_N(aligned,8,8)
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DECLARE_SIM_CORE_READ_N(aligned,16,16)
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#define sim_core_read_unaligned_1 sim_core_read_aligned_1
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DECLARE_SIM_CORE_READ_N(unaligned,2,2)
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DECLARE_SIM_CORE_READ_N(unaligned,4,4)
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DECLARE_SIM_CORE_READ_N(unaligned,8,8)
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DECLARE_SIM_CORE_READ_N(unaligned,16,16)
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DECLARE_SIM_CORE_READ_N(misaligned,3,4)
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DECLARE_SIM_CORE_READ_N(misaligned,5,8)
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DECLARE_SIM_CORE_READ_N(misaligned,6,8)
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DECLARE_SIM_CORE_READ_N(misaligned,7,8)
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#define sim_core_read_1 sim_core_read_aligned_1
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#define sim_core_read_2 sim_core_read_aligned_2
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#define sim_core_read_4 sim_core_read_aligned_4
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#define sim_core_read_8 sim_core_read_aligned_8
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#define sim_core_read_16 sim_core_read_aligned_16
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#define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
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#define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
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#define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
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#undef DECLARE_SIM_CORE_READ_N
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#if (WITH_DEVICES)
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/* TODO: create sim/common/device.h */
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/* These are defined with each particular cpu. */
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void device_error (device *me, char* message, ...);
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int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
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int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
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#endif
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#endif
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