c3d65c1ced
* doc/binutils.texi (objdump): Document -Mppcps. gas/ * config/tc-ppc.c (parse_cpu): Handle "750cl". (pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7". (md_show_usage): Document -m750cl. (md_assemble): Handle two delimiters in succession (eg. `),'). * doc/c-ppc.texi (PowerPC-Opts): Document -m750cl. * testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests. * testsuite/gas/ppc/ppc750ps.s: New file. * testsuite/gas/ppc/ppc750ps.d: Likewise. include/opcode/ * ppc.h (PPC_OPCODE_PPCPS): New. opcodes/ * ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New. (XOPS, XOPS_MASK, XW, XW_MASK): Likewise. (PPCPS): Likewise. (powerpc_opcodes): Add all pair singles instructions. * ppc-dis.c (powerpc_dialect): Handle "ppcps". (print_ppc_disassembler_options): Document -Mppcps.
378 lines
12 KiB
C
378 lines
12 KiB
C
/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
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Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/ppc.h"
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/* This file provides several disassembler functions, all of which use
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the disassembler interface defined in dis-asm.h. Several functions
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
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/* Determine which set of machines to disassemble for. PPC403/601 or
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BookE. For convenience, also disassemble instructions supported
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by the AltiVec vector unit. */
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static int
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powerpc_dialect (struct disassemble_info *info)
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{
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int dialect = PPC_OPCODE_PPC;
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if (BFD_DEFAULT_TARGET_SIZE == 64)
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dialect |= PPC_OPCODE_64;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "ppcps") != NULL)
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dialect |= PPC_OPCODE_PPCPS;
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "booke") != NULL)
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
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else if ((info->mach == bfd_mach_ppc_e500)
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|| (info->disassembler_options
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&& strstr (info->disassembler_options, "e500") != NULL))
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dialect |= (PPC_OPCODE_BOOKE
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| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
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| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_RFMCI);
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "efs") != NULL)
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dialect |= PPC_OPCODE_EFS;
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "e300") != NULL)
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dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "440") != NULL)
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
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| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
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else
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dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power4") != NULL)
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dialect |= PPC_OPCODE_POWER4;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power5") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "cell") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power6") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "any") != NULL)
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dialect |= PPC_OPCODE_ANY;
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if (info->disassembler_options)
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{
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if (strstr (info->disassembler_options, "32") != NULL)
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dialect &= ~PPC_OPCODE_64;
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else if (strstr (info->disassembler_options, "64") != NULL)
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dialect |= PPC_OPCODE_64;
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}
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info->private_data = (char *) 0 + dialect;
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return dialect;
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}
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/* Print a big endian PowerPC instruction. */
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int
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print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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int dialect = (char *) info->private_data - (char *) 0;
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return print_insn_powerpc (memaddr, info, 1, dialect);
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}
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/* Print a little endian PowerPC instruction. */
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int
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print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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int dialect = (char *) info->private_data - (char *) 0;
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return print_insn_powerpc (memaddr, info, 0, dialect);
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}
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/* Print a POWER (RS/6000) instruction. */
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int
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print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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}
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/* Extract the operand value from the PowerPC or POWER instruction. */
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static long
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operand_value_powerpc (const struct powerpc_operand *operand,
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unsigned long insn, int dialect)
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{
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long value;
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int invalid;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, dialect, &invalid);
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else
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{
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value = (insn >> operand->shift) & operand->bitm;
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
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{
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/* BITM is always some number of zeros followed by some
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number of ones, followed by some numer of zeros. */
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unsigned long top = operand->bitm;
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/* top & -top gives the rightmost 1 bit, so this
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fills in any trailing zeros. */
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top |= (top & -top) - 1;
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top &= ~(top >> 1);
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value = (value ^ top) - top;
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}
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}
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return value;
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}
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/* Determine whether the optional operand(s) should be printed. */
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static int
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skip_optional_operands (const unsigned char *opindex,
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unsigned long insn, int dialect)
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{
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const struct powerpc_operand *operand;
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for (; *opindex != 0; opindex++)
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{
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operand = &powerpc_operands[*opindex];
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if ((operand->flags & PPC_OPERAND_NEXT) != 0
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|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& operand_value_powerpc (operand, insn, dialect) != 0))
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return 0;
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}
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return 1;
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}
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/* Print a PowerPC or POWER instruction. */
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static int
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print_insn_powerpc (bfd_vma memaddr,
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struct disassemble_info *info,
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int bigendian,
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int dialect)
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{
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bfd_byte buffer[4];
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int status;
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unsigned long insn;
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const struct powerpc_opcode *opcode;
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const struct powerpc_opcode *opcode_end;
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unsigned long op;
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if (dialect == 0)
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dialect = powerpc_dialect (info);
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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if (bigendian)
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insn = bfd_getb32 (buffer);
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else
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insn = bfd_getl32 (buffer);
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/* Get the major opcode of the instruction. */
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op = PPC_OP (insn);
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/* Find the first match in the opcode table. We could speed this up
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a bit by doing a binary search on the major opcode. */
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opcode_end = powerpc_opcodes + powerpc_num_opcodes;
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again:
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for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
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{
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unsigned long table_op;
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const unsigned char *opindex;
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const struct powerpc_operand *operand;
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int invalid;
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int need_comma;
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int need_paren;
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int skip_optional;
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table_op = PPC_OP (opcode->opcode);
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if (op < table_op)
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break;
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if (op > table_op)
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continue;
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if ((insn & opcode->mask) != opcode->opcode
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|| (opcode->flags & dialect) == 0)
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continue;
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/* Make two passes over the operands. First see if any of them
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have extraction functions, and, if they do, make sure the
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instruction is valid. */
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invalid = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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operand = powerpc_operands + *opindex;
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if (operand->extract)
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(*operand->extract) (insn, dialect, &invalid);
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}
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if (invalid)
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continue;
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/* The instruction is valid. */
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
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else
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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/* Now extract and print the operands. */
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need_comma = 0;
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need_paren = 0;
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skip_optional = -1;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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long value;
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operand = powerpc_operands + *opindex;
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/* Operands that are marked FAKE are simply ignored. We
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already made sure that the extract function considered
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the instruction to be valid. */
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if ((operand->flags & PPC_OPERAND_FAKE) != 0)
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continue;
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/* If all of the optional operands have the value zero,
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then don't print any of them. */
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
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{
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if (skip_optional < 0)
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skip_optional = skip_optional_operands (opindex, insn,
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dialect);
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if (skip_optional)
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continue;
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}
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value = operand_value_powerpc (operand, insn, dialect);
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if (need_comma)
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{
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(*info->fprintf_func) (info->stream, ",");
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need_comma = 0;
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}
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/* Print the operand as directed by the flags. */
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if ((operand->flags & PPC_OPERAND_GPR) != 0
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|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
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(*info->fprintf_func) (info->stream, "r%ld", value);
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else if ((operand->flags & PPC_OPERAND_FPR) != 0)
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(*info->fprintf_func) (info->stream, "f%ld", value);
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else if ((operand->flags & PPC_OPERAND_VR) != 0)
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(*info->fprintf_func) (info->stream, "v%ld", value);
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else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
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(*info->print_address_func) (memaddr + value, info);
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else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
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(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
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else if ((operand->flags & PPC_OPERAND_CR) == 0
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|| (dialect & PPC_OPCODE_PPC) == 0)
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(*info->fprintf_func) (info->stream, "%ld", value);
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else
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{
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if (operand->bitm == 7)
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(*info->fprintf_func) (info->stream, "cr%ld", value);
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else
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{
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static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
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int cr;
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int cc;
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cr = value >> 2;
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if (cr != 0)
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(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
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cc = value & 3;
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(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
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}
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}
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if (need_paren)
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{
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(*info->fprintf_func) (info->stream, ")");
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need_paren = 0;
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}
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if ((operand->flags & PPC_OPERAND_PARENS) == 0)
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need_comma = 1;
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else
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{
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(*info->fprintf_func) (info->stream, "(");
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need_paren = 1;
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}
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}
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/* We have found and printed an instruction; return. */
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return 4;
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}
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if ((dialect & PPC_OPCODE_ANY) != 0)
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{
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dialect = ~PPC_OPCODE_ANY;
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goto again;
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}
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/* We could not find a match. */
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(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
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return 4;
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}
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void
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print_ppc_disassembler_options (FILE *stream)
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{
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fprintf (stream, "\n\
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The following PPC specific disassembler options are supported for use with\n\
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the -M switch:\n");
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fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n");
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fprintf (stream, " e300 Disassemble the e300 instructions\n");
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fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
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fprintf (stream, " 440 Disassemble the 440 instructions\n");
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fprintf (stream, " efs Disassemble the EFS instructions\n");
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fprintf (stream, " ppcps Disassemble the PowerPC paired singles instructions\n");
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fprintf (stream, " power4 Disassemble the Power4 instructions\n");
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fprintf (stream, " power5 Disassemble the Power5 instructions\n");
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fprintf (stream, " power6 Disassemble the Power6 instructions\n");
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fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
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fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
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}
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