6a25bee8d0
Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU. (rx_bfield): Add prototype. (rx_post): Likewise. * config/rx-parse.y: Add v3 instructions and Double FPU registers. (DSIZE): Define. (POST): Define. (rx_check_v3): New. check v3 type. (rx_check_dfpu): New. check have double support. (double_condition_table): New. dcmp<cond> contiditon. (check_condition): Multiple condition support. (rx_lex): RXv3 instructions support. Add parse dcmp<cond> instruction and Double FPU registers. (immediate): Disable optimize in dmov #imm case. (displacement): Add double displacement in dmov instraction. * config/tc-rx.c (rx_use_conventional_section_names): Invert default value in rx-*-linux target. (cpu_type): Add additional ELF flags. (cpu_type_list): Add RXv3. (md_parse_option): Refer elf_flags from cpu_type_list. (md_show_usage): Add rxv3 and rxv3-dfpu. (rx_bytesT): Add post byte. (rx_bfield): New. generate bfmov / bfmovz "imm" field. (rx_post): New. Set instruction post byte. (md_assemble): Add post byte. doc/c-rx.texi: Add cpu types. * testsuite/gas/rx/Xtod.d: New. * testsuite/gas/rx/Xtod.sm: New. * testsuite/gas/rx/bfmov.d: New. * testsuite/gas/rx/bfmov.sm: New. * testsuite/gas/rx/dabs.d: New. * testsuite/gas/rx/dabs.sm: New. * testsuite/gas/rx/dadd.d: New. * testsuite/gas/rx/dadd.sm: New. * testsuite/gas/rx/dcmp.d: New. * testsuite/gas/rx/dcmp.sm: New. * testsuite/gas/rx/ddiv.d: New. * testsuite/gas/rx/ddiv.sm: New. * testsuite/gas/rx/dmov.d: New. * testsuite/gas/rx/dmov.sm: New. * testsuite/gas/rx/dmul.d: New. * testsuite/gas/rx/dmul.sm: New. * testsuite/gas/rx/dneg.d: New. * testsuite/gas/rx/dneg.sm: New. * testsuite/gas/rx/dpopm.d: New. * testsuite/gas/rx/dpopm.sm: New. * testsuite/gas/rx/dpushm.d: New. * testsuite/gas/rx/dpushm.sm: New. * testsuite/gas/rx/dround.d: New. * testsuite/gas/rx/dround.sm: New. * testsuite/gas/rx/dsqrt.d: New. * testsuite/gas/rx/dsqrt.sm: New. * testsuite/gas/rx/dsub.d: New. * testsuite/gas/rx/dsub.sm: New. * testsuite/gas/rx/dtoX.d: New. * testsuite/gas/rx/dtoX.sm: New. * testsuite/gas/rx/macros.inc: Add double FPU registers. * testsuite/gas/rx/mvfdc.d: New. * testsuite/gas/rx/mvfdc.sm: New. * testsuite/gas/rx/mvfdr.d: New. * testsuite/gas/rx/mvfdr.sm: New. * testsuite/gas/rx/mvtdc.d: New. * testsuite/gas/rx/mvtdc.sm: New. * testsuite/gas/rx/rstr.d: New. * testsuite/gas/rx/rstr.sm: New. * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option. * testsuite/gas/rx/save.d: New. * testsuite/gas/rx/save.sm: New. * testsuite/gas/rx/xor.d: New. * testsuite/gas/rx/xor.sm: Add pattern.
254 lines
8.5 KiB
Plaintext
254 lines
8.5 KiB
Plaintext
@c Copyright (C) 2008-2019 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node RX-Dependent
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@chapter RX Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter RX Dependent Features
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@end ifclear
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@cindex RX support
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@menu
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* RX-Opts:: RX Assembler Command-line Options
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* RX-Modifiers:: Symbolic Operand Modifiers
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* RX-Directives:: Assembler Directives
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* RX-Float:: Floating Point
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* RX-Syntax:: Syntax
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@end menu
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@node RX-Opts
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@section RX Options
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@cindex options, RX
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@cindex RX options
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The Renesas RX port of @code{@value{AS}} has a few target specific
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command-line options:
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@table @code
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@cindex @samp{-m32bit-doubles}
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@item -m32bit-doubles
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This option controls the ABI and indicates to use a 32-bit float ABI.
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It has no effect on the assembled instructions, but it does influence
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the behaviour of the @samp{.double} pseudo-op.
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This is the default.
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@cindex @samp{-m64bit-doubles}
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@item -m64bit-doubles
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This option controls the ABI and indicates to use a 64-bit float ABI.
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It has no effect on the assembled instructions, but it does influence
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the behaviour of the @samp{.double} pseudo-op.
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@cindex @samp{-mbig-endian}
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@item -mbig-endian
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This option controls the ABI and indicates to use a big-endian data
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ABI. It has no effect on the assembled instructions, but it does
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influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int},
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@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops.
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@cindex @samp{-mlittle-endian}
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@item -mlittle-endian
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This option controls the ABI and indicates to use a little-endian data
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ABI. It has no effect on the assembled instructions, but it does
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influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int},
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@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops.
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This is the default.
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@cindex @samp{-muse-conventional-section-names}
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@item -muse-conventional-section-names
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This option controls the default names given to the code (.text),
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initialised data (.data) and uninitialised data sections (.bss).
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@cindex @samp{-muse-renesas-section-names}
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@item -muse-renesas-section-names
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This option controls the default names given to the code (.P),
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initialised data (.D_1) and uninitialised data sections (.B_1).
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This is the default.
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@cindex @samp{-msmall-data-limit}
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@item -msmall-data-limit
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This option tells the assembler that the small data limit feature of
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the RX port of GCC is being used. This results in the assembler
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generating an undefined reference to a symbol called @code{__gp} for
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use by the relocations that are needed to support the small data limit
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feature. This option is not enabled by default as it would otherwise
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pollute the symbol table.
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@cindex @samp{-mpid}
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@item -mpid
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This option tells the assembler that the position independent data of the
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RX port of GCC is being used. This results in the assembler
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generating an undefined reference to a symbol called @code{__pid_base},
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and also setting the RX_PID flag bit in the e_flags field of the ELF
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header of the object file.
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@cindex @samp{-mint-register}
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@item -mint-register=@var{num}
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This option tells the assembler how many registers have been reserved
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for use by interrupt handlers. This is needed in order to compute the
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correct values for the @code{%gpreg} and @code{%pidreg} meta registers.
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@cindex @samp{-mgcc-abi}
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@item -mgcc-abi
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This option tells the assembler that the old GCC ABI is being used by
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the assembled code. With this version of the ABI function arguments
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that are passed on the stack are aligned to a 32-bit boundary.
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@cindex @samp{-mrx-abi}
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@item -mrx-abi
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This option tells the assembler that the official RX ABI is being used
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by the assembled code. With this version of the ABI function
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arguments that are passed on the stack are aligned to their natural
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alignments. This option is the default.
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@cindex @samp{-mcpu=}
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@item -mcpu=@var{name}
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This option tells the assembler the target CPU type. Currently the
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@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610}, @code{rxv2},
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@code{rxv3} and @code{rxv3-dfpu} are recognised as valid cpu names.
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Attempting to assemble an instructionnot supported by the indicated
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cpu type will result in an error message being generated.
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@cindex @samp{-mno-allow-string-insns}
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@item -mno-allow-string-insns
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This option tells the assembler to mark the object file that it is
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building as one that does not use the string instructions
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@code{SMOVF}, @code{SCMPU}, @code{SMOVB}, @code{SMOVU}, @code{SUNTIL}
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@code{SWHILE} or the @code{RMPA} instruction. In addition the mark
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tells the linker to complain if an attempt is made to link the binary
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with another one that does use any of these instructions.
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Note - the inverse of this option, @code{-mallow-string-insns}, is
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not needed. The assembler automatically detects the use of the
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the instructions in the source code and labels the resulting
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object file appropriately. If no string instructions are detected
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then the object file is labelled as being one that can be linked with
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either string-using or string-banned object files.
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@end table
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@node RX-Modifiers
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@section Symbolic Operand Modifiers
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@cindex RX modifiers
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@cindex syntax, RX
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@cindex %gp
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The assembler supports one modifier when using symbol addresses
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in RX instruction operands. The general syntax is the following:
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@smallexample
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%gp(symbol)
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@end smallexample
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The modifier returns the offset from the @var{__gp} symbol to the
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specified symbol as a 16-bit value. The intent is that this offset
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should be used in a register+offset move instruction when generating
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references to small data. Ie, like this:
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@smallexample
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mov.W %gp(_foo)[%gpreg], r1
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@end smallexample
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The assembler also supports two meta register names which can be used
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to refer to registers whose values may not be known to the
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programmer. These meta register names are:
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@table @code
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@cindex @samp{%gpreg}
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@item %gpreg
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The small data address register.
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@cindex @samp{%pidreg}
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@item %pidreg
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The PID base address register.
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@end table
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Both registers normally have the value r13, but this can change if
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some registers have been reserved for use by interrupt handlers or if
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both the small data limit and position independent data features are
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being used at the same time.
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@node RX-Directives
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@section Assembler Directives
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@cindex assembler directives, RX
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@cindex RX assembler directives
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The RX version of @code{@value{AS}} has the following specific
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assembler directives:
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@table @code
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@item .3byte
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@cindex assembler directive .3byte, RX
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@cindex RX assembler directive .3byte
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Inserts a 3-byte value into the output file at the current location.
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@item .fetchalign
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@cindex assembler directive .fetchalign, RX
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@cindex RX assembler directive .fetchalign
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If the next opcode following this directive spans a fetch line
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boundary (8 byte boundary), the opcode is aligned to that boundary.
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If the next opcode does not span a fetch line, this directive has no
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effect. Note that one or more labels may be between this directive
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and the opcode; those labels are aligned as well. Any inserted bytes
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due to alignment will form a NOP opcode.
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@end table
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@node RX-Float
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@section Floating Point
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@cindex floating point, RX
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@cindex RX floating point
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The floating point formats generated by directives are these.
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@table @code
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@cindex @code{float} directive, RX
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@item .float
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@code{Single} precision (32-bit) floating point constants.
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@cindex @code{double} directive, RX
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@item .double
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If the @option{-m64bit-doubles} command-line option has been specified
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then then @code{double} directive generates @code{double} precision
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(64-bit) floating point constants, otherwise it generates
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@code{single} precision (32-bit) floating point constants. To force
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the generation of 64-bit floating point constants used the @code{dc.d}
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directive instead.
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@end table
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@node RX-Syntax
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@section Syntax for the RX
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@menu
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* RX-Chars:: Special Characters
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@end menu
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@node RX-Chars
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@subsection Special Characters
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@cindex line comment character, RX
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@cindex RX line comment character
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The presence of a @samp{;} appearing anywhere on a line indicates the
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start of a comment that extends to the end of that line.
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If a @samp{#} appears as the first character of a line then the whole
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line is treated as a comment, but in this case the line can also be a
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logical line number directive (@pxref{Comments}) or a preprocessor
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control command (@pxref{Preprocessing}).
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@cindex line separator, RX
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@cindex statement separator, RX
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@cindex RX line separator
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The @samp{!} character can be used to separate statements on the same
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line.
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