164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/* Blackfin Event Vector Table (EVT) model.
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Copyright (C) 2010-2020 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_cec.h"
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#include "dv-bfin_evt.h"
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struct bfin_evt
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{
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bu32 base;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 evt[16];
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};
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#define mmr_base() offsetof(struct bfin_evt, evt[0])
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#define mmr_offset(mmr) (offsetof(struct bfin_evt, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8",
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"EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_evt_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_evt *evt = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_4 (source);
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mmr_off = addr - evt->base;
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HW_TRACE_WRITE ();
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evt->evt[mmr_off / 4] = value;
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return nr_bytes;
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}
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static unsigned
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bfin_evt_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_evt *evt = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - evt->base;
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HW_TRACE_READ ();
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value = evt->evt[mmr_off / 4];
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dv_store_4 (dest, value);
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return nr_bytes;
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}
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static void
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attach_bfin_evt_regs (struct hw *me, struct bfin_evt *evt)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_EVT_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_EVT_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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evt->base = attach_address;
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}
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static void
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bfin_evt_finish (struct hw *me)
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{
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struct bfin_evt *evt;
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evt = HW_ZALLOC (me, struct bfin_evt);
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set_hw_data (me, evt);
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set_hw_io_read_buffer (me, bfin_evt_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_evt_io_write_buffer);
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attach_bfin_evt_regs (me, evt);
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}
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const struct hw_descriptor dv_bfin_evt_descriptor[] =
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{
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{"bfin_evt", bfin_evt_finish,},
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{NULL, NULL},
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};
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#define EVT_STATE(cpu) DV_STATE_CACHED (cpu, evt)
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void
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cec_set_evt (SIM_CPU *cpu, int ivg, bu32 handler_addr)
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{
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if (ivg > IVG15 || ivg < 0)
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sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
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EVT_STATE (cpu)->evt[ivg] = handler_addr;
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}
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bu32
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cec_get_evt (SIM_CPU *cpu, int ivg)
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{
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if (ivg > IVG15 || ivg < 0)
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sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
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return EVT_STATE (cpu)->evt[ivg];
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}
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bu32
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cec_get_reset_evt (SIM_CPU *cpu)
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{
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/* XXX: This should tail into the model to get via BMODE pins. */
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return 0xef000000;
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}
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