916 lines
19 KiB
C
916 lines
19 KiB
C
/* rl78.c --- opcode semantics for stand-alone RL78 simulator.
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Copyright (C) 2008-2012 Free Software Foundation, Inc.
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Contributed by Red Hat, Inc.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <signal.h>
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#include <setjmp.h>
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#include <time.h>
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#include "opcode/rl78.h"
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#include "cpu.h"
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#include "mem.h"
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extern int skip_init;
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static int opcode_pc = 0;
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jmp_buf decode_jmp_buf;
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#define DO_RETURN(x) longjmp (decode_jmp_buf, x)
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#define tprintf if (trace) printf
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#define WILD_JUMP_CHECK(new_pc) \
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do { \
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if (new_pc == 0 || new_pc > 0xfffff) \
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{ \
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pc = opcode_pc; \
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fprintf (stderr, "Wild jump to 0x%x from 0x%x!\n", new_pc, pc); \
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DO_RETURN (RL78_MAKE_HIT_BREAK ()); \
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} \
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} while (0)
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typedef struct {
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unsigned long dpc;
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} RL78_Data;
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static int
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rl78_get_byte (void *vdata)
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{
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RL78_Data *rl78_data = (RL78_Data *)vdata;
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int rv = mem_get_pc (rl78_data->dpc);
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rl78_data->dpc ++;
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return rv;
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}
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static int
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op_addr (const RL78_Opcode_Operand *o, int for_data)
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{
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int v = o->addend;
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if (o->reg != RL78_Reg_None)
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v += get_reg (o->reg);
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if (o->reg2 != RL78_Reg_None)
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v += get_reg (o->reg2);
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if (o->use_es)
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v |= (get_reg (RL78_Reg_ES) & 0xf) << 16;
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else if (for_data)
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v |= 0xf0000;
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v &= 0xfffff;
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return v;
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}
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static int
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get_op (const RL78_Opcode_Decoded *rd, int i, int for_data)
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{
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int v, r;
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const RL78_Opcode_Operand *o = rd->op + i;
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switch (o->type)
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{
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case RL78_Operand_None:
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/* condition code does this. */
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v = 0;
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break;
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case RL78_Operand_Immediate:
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tprintf (" #");
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v = o->addend;
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break;
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case RL78_Operand_Register:
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tprintf (" %s=", reg_names[o->reg]);
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v = get_reg (o->reg);
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break;
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case RL78_Operand_Bit:
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tprintf (" %s.%d=", reg_names[o->reg], o->bit_number);
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v = get_reg (o->reg);
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v = (v & (1 << o->bit_number)) ? 1 : 0;
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break;
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case RL78_Operand_Indirect:
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v = op_addr (o, for_data);
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tprintf (" [0x%x]=", v);
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if (rd->size == RL78_Word)
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v = mem_get_hi (v);
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else
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v = mem_get_qi (v);
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break;
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case RL78_Operand_BitIndirect:
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v = op_addr (o, for_data);
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tprintf (" [0x%x].%d=", v, o->bit_number);
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v = (mem_get_qi (v) & (1 << o->bit_number)) ? 1 : 0;
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break;
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case RL78_Operand_PreDec:
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r = get_reg (o->reg);
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tprintf (" [--%s]", reg_names[o->reg]);
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if (rd->size == RL78_Word)
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{
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r -= 2;
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v = mem_get_hi (r | 0xf0000);
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}
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else
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{
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r -= 1;
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v = mem_get_qi (r | 0xf0000);
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}
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set_reg (o->reg, r);
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break;
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case RL78_Operand_PostInc:
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tprintf (" [%s++]", reg_names[o->reg]);
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r = get_reg (o->reg);
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if (rd->size == RL78_Word)
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{
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v = mem_get_hi (r | 0xf0000);
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r += 2;
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}
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else
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{
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v = mem_get_qi (r | 0xf0000);
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r += 1;
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}
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set_reg (o->reg, r);
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break;
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default:
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abort ();
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}
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tprintf ("%d", v);
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return v;
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}
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static void
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put_op (const RL78_Opcode_Decoded *rd, int i, int for_data, int v)
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{
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int r, a;
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const RL78_Opcode_Operand *o = rd->op + i;
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tprintf (" -> ");
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switch (o->type)
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{
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case RL78_Operand_Register:
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tprintf ("%s", reg_names[o->reg]);
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set_reg (o->reg, v);
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break;
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case RL78_Operand_Bit:
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tprintf ("%s.%d", reg_names[o->reg], o->bit_number);
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r = get_reg (o->reg);
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if (v)
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r |= (1 << o->bit_number);
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else
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r &= ~(1 << o->bit_number);
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set_reg (o->reg, r);
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break;
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case RL78_Operand_Indirect:
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r = op_addr (o, for_data);
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tprintf ("[0x%x]", r);
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if (rd->size == RL78_Word)
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mem_put_hi (r, v);
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else
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mem_put_qi (r, v);
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break;
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case RL78_Operand_BitIndirect:
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a = op_addr (o, for_data);
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tprintf ("[0x%x].%d", a, o->bit_number);
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r = mem_get_qi (a);
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if (v)
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r |= (1 << o->bit_number);
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else
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r &= ~(1 << o->bit_number);
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mem_put_qi (a, r);
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break;
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case RL78_Operand_PreDec:
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r = get_reg (o->reg);
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tprintf ("[--%s]", reg_names[o->reg]);
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if (rd->size == RL78_Word)
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{
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r -= 2;
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set_reg (o->reg, r);
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mem_put_hi (r | 0xf0000, v);
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}
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else
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{
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r -= 1;
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set_reg (o->reg, r);
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mem_put_qi (r | 0xf0000, v);
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}
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break;
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case RL78_Operand_PostInc:
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tprintf ("[%s++]", reg_names[o->reg]);
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r = get_reg (o->reg);
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if (rd->size == RL78_Word)
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{
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mem_put_hi (r | 0xf0000, v);
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r += 2;
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}
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else
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{
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mem_put_qi (r | 0xf0000, v);
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r += 1;
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}
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set_reg (o->reg, r);
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break;
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default:
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abort ();
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}
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tprintf ("\n");
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}
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static void
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op_flags (int before, int after, int mask, RL78_Size size)
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{
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int vmask, cmask, amask, avmask;
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if (size == RL78_Word)
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{
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cmask = 0x10000;
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vmask = 0xffff;
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amask = 0x100;
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avmask = 0x0ff;
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}
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else
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{
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cmask = 0x100;
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vmask = 0xff;
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amask = 0x10;
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avmask = 0x0f;
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}
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int psw = get_reg (RL78_Reg_PSW);
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psw &= ~mask;
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if (mask & RL78_PSW_CY)
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{
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if ((after & cmask) != (before & cmask))
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psw |= RL78_PSW_CY;
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}
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if (mask & RL78_PSW_AC)
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{
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if ((after & amask) != (before & amask)
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&& (after & avmask) < (before & avmask))
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psw |= RL78_PSW_AC;
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}
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if (mask & RL78_PSW_Z)
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{
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if (! (after & vmask))
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psw |= RL78_PSW_Z;
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}
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set_reg (RL78_Reg_PSW, psw);
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}
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#define FLAGS(before,after) if (opcode.flags) op_flags (before, after, opcode.flags, opcode.size)
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#define PD(x) put_op (&opcode, 0, 1, x)
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#define PS(x) put_op (&opcode, 1, 1, x)
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#define GD() get_op (&opcode, 0, 1)
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#define GS() get_op (&opcode, 1, 1)
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#define GPC() gpc (&opcode, 0)
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static int
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gpc (RL78_Opcode_Decoded *opcode, int idx)
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{
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int a = get_op (opcode, 0, 1);
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if (opcode->op[idx].type == RL78_Operand_Register)
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a =(a & 0x0ffff) | ((get_reg (RL78_Reg_CS) & 0x0f) << 16);
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else
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a &= 0xfffff;
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return a;
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}
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static int
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get_carry (void)
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{
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return (get_reg (RL78_Reg_PSW) & RL78_PSW_CY) ? 1 : 0;
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}
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static void
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set_carry (int c)
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{
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int p = get_reg (RL78_Reg_PSW);
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tprintf ("set_carry (%d)\n", c ? 1 : 0);
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if (c)
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p |= RL78_PSW_CY;
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else
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p &= ~RL78_PSW_CY;
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set_reg (RL78_Reg_PSW, p);
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}
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/* We simulate timer TM00 in interval mode, no clearing, with
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interrupts. I.e. it's a cycle counter. */
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unsigned int counts_per_insn[0x100000];
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int pending_clocks = 0;
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long long total_clocks = 0;
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#define TCR0 0xf0180
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#define MK1 0xfffe6
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static void
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process_clock_tick (void)
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{
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unsigned short cnt;
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unsigned short ivect;
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unsigned short mask;
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unsigned char psw;
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int save_trace;
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save_trace = trace;
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trace = 0;
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pending_clocks ++;
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counts_per_insn[opcode_pc] += pending_clocks;
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total_clocks += pending_clocks;
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while (pending_clocks)
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{
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pending_clocks --;
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cnt = mem_get_hi (TCR0);
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cnt --;
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mem_put_hi (TCR0, cnt);
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if (cnt != 0xffff)
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continue;
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/* overflow. */
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psw = get_reg (RL78_Reg_PSW);
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ivect = mem_get_hi (0x0002c);
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mask = mem_get_hi (MK1);
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if ((psw & RL78_PSW_IE)
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&& (ivect != 0)
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&& !(mask & 0x0010))
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{
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unsigned short sp = get_reg (RL78_Reg_SP);
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set_reg (RL78_Reg_SP, sp - 4);
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sp --;
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mem_put_qi (sp | 0xf0000, psw);
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sp -= 3;
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mem_put_psi (sp | 0xf0000, pc);
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psw &= ~RL78_PSW_IE;
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set_reg (RL78_Reg_PSW, psw);
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pc = ivect;
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/* Spec says 9-14 clocks */
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pending_clocks += 9;
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}
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}
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trace = save_trace;
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}
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void
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dump_counts_per_insn (const char * filename)
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{
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int i;
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FILE *f;
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f = fopen (filename, "w");
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if (!f)
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{
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perror (filename);
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return;
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}
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for (i = 0; i < 0x100000; i ++)
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{
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if (counts_per_insn[i])
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fprintf (f, "%05x %d\n", i, counts_per_insn[i]);
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}
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fclose (f);
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}
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static void
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CLOCKS (int n)
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{
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pending_clocks += n - 1;
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}
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int
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decode_opcode (void)
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{
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RL78_Data rl78_data;
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RL78_Opcode_Decoded opcode;
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int opcode_size;
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int a, b, v, v2;
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unsigned int u, u2;
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int obits;
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rl78_data.dpc = pc;
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opcode_size = rl78_decode_opcode (pc, &opcode,
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rl78_get_byte, &rl78_data);
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opcode_pc = pc;
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pc += opcode_size;
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trace_register_words = opcode.size == RL78_Word ? 1 : 0;
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/* Used by shfit/rotate instructions */
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obits = opcode.size == RL78_Word ? 16 : 8;
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switch (opcode.id)
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{
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case RLO_add:
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tprintf ("ADD: ");
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a = GS ();
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b = GD ();
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v = a + b;
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FLAGS (b, v);
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PD (v);
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if (opcode.op[0].type == RL78_Operand_Indirect)
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CLOCKS (2);
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break;
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case RLO_addc:
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tprintf ("ADDC: ");
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a = GS ();
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b = GD ();
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v = a + b + get_carry ();
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FLAGS (b, v);
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PD (v);
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if (opcode.op[0].type == RL78_Operand_Indirect)
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CLOCKS (2);
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break;
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case RLO_and:
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tprintf ("AND: ");
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a = GS ();
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b = GD ();
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v = a & b;
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FLAGS (b, v);
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PD (v);
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if (opcode.op[0].type == RL78_Operand_Indirect)
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CLOCKS (2);
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break;
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case RLO_branch_cond:
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case RLO_branch_cond_clear:
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tprintf ("BRANCH_COND: ");
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if (!condition_true (opcode.op[1].condition, GS ()))
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{
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tprintf (" false\n");
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if (opcode.op[1].condition == RL78_Condition_T
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|| opcode.op[1].condition == RL78_Condition_F)
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CLOCKS (3);
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else
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CLOCKS (2);
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break;
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}
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if (opcode.id == RLO_branch_cond_clear)
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PS (0);
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tprintf (" ");
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if (opcode.op[1].condition == RL78_Condition_T
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|| opcode.op[1].condition == RL78_Condition_F)
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CLOCKS (3); /* note: adds two clocks, total 5 clocks */
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else
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CLOCKS (2); /* note: adds one clock, total 4 clocks */
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case RLO_branch:
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tprintf ("BRANCH: ");
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v = GPC ();
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WILD_JUMP_CHECK (v);
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pc = v;
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tprintf (" => 0x%05x\n", pc);
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CLOCKS (3);
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break;
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case RLO_break:
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tprintf ("BRK: ");
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CLOCKS (5);
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if (rl78_in_gdb)
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DO_RETURN (RL78_MAKE_HIT_BREAK ());
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else
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DO_RETURN (RL78_MAKE_EXITED (1));
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break;
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case RLO_call:
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tprintf ("CALL: ");
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a = get_reg (RL78_Reg_SP);
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set_reg (RL78_Reg_SP, a - 4);
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mem_put_psi ((a - 4) | 0xf0000, pc);
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v = GPC ();
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WILD_JUMP_CHECK (v);
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pc = v;
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#if 0
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/* Enable this code to dump the arguments for each call. */
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if (trace)
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{
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int i;
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skip_init ++;
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for (i = 0; i < 8; i ++)
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printf (" %02x", mem_get_qi (0xf0000 | (a + i)) & 0xff);
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skip_init --;
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}
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#endif
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tprintf ("\n");
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CLOCKS (3);
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break;
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case RLO_cmp:
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tprintf ("CMP: ");
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a = GD ();
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b = GS ();
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v = a - b;
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FLAGS (b, v);
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tprintf (" (%d)\n", v);
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break;
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case RLO_divhu:
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a = get_reg (RL78_Reg_AX);
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b = get_reg (RL78_Reg_DE);
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tprintf (" %d / %d = ", a, b);
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if (b == 0)
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{
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tprintf ("%d rem %d\n", 0xffff, a);
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set_reg (RL78_Reg_AX, 0xffff);
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set_reg (RL78_Reg_DE, a);
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}
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else
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{
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v = a / b;
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|
a = a % b;
|
|
tprintf ("%d rem %d\n", v, a);
|
|
set_reg (RL78_Reg_AX, v);
|
|
set_reg (RL78_Reg_DE, a);
|
|
}
|
|
CLOCKS (9);
|
|
break;
|
|
|
|
case RLO_divwu:
|
|
{
|
|
unsigned long bcax, hlde, quot, rem;
|
|
bcax = get_reg (RL78_Reg_AX) + 65536 * get_reg (RL78_Reg_BC);
|
|
hlde = get_reg (RL78_Reg_DE) + 65536 * get_reg (RL78_Reg_HL);
|
|
|
|
tprintf (" %lu / %lu = ", bcax, hlde);
|
|
if (hlde == 0)
|
|
{
|
|
tprintf ("%lu rem %lu\n", 0xffffLU, bcax);
|
|
set_reg (RL78_Reg_AX, 0xffffLU);
|
|
set_reg (RL78_Reg_BC, 0xffffLU);
|
|
set_reg (RL78_Reg_DE, bcax);
|
|
set_reg (RL78_Reg_HL, bcax >> 16);
|
|
}
|
|
else
|
|
{
|
|
quot = bcax / hlde;
|
|
rem = bcax % hlde;
|
|
tprintf ("%lu rem %lu\n", quot, rem);
|
|
set_reg (RL78_Reg_AX, quot);
|
|
set_reg (RL78_Reg_BC, quot >> 16);
|
|
set_reg (RL78_Reg_DE, rem);
|
|
set_reg (RL78_Reg_HL, rem >> 16);
|
|
}
|
|
}
|
|
CLOCKS (17);
|
|
break;
|
|
|
|
case RLO_halt:
|
|
tprintf ("HALT.\n");
|
|
DO_RETURN (RL78_MAKE_EXITED (get_reg (RL78_Reg_A)));
|
|
|
|
case RLO_mov:
|
|
tprintf ("MOV: ");
|
|
a = GS ();
|
|
FLAGS (a, a);
|
|
PD (a);
|
|
break;
|
|
|
|
#define MACR 0xffff0
|
|
case RLO_mach:
|
|
tprintf ("MACH:");
|
|
a = sign_ext (get_reg (RL78_Reg_AX), 16);
|
|
b = sign_ext (get_reg (RL78_Reg_BC), 16);
|
|
v = sign_ext (mem_get_si (MACR), 32);
|
|
tprintf ("%08x %d + %d * %d = ", v, v, a, b);
|
|
v2 = sign_ext (v + a * b, 32);
|
|
tprintf ("%08x %d\n", v2, v2);
|
|
mem_put_si (MACR, v2);
|
|
a = get_reg (RL78_Reg_PSW);
|
|
v ^= v2;
|
|
if (v & (1<<31))
|
|
a |= RL78_PSW_CY;
|
|
else
|
|
a &= ~RL78_PSW_CY;
|
|
if (v2 & (1 << 31))
|
|
a |= RL78_PSW_AC;
|
|
else
|
|
a &= ~RL78_PSW_AC;
|
|
set_reg (RL78_Reg_PSW, a);
|
|
CLOCKS (3);
|
|
break;
|
|
|
|
case RLO_machu:
|
|
tprintf ("MACHU:");
|
|
a = get_reg (RL78_Reg_AX);
|
|
b = get_reg (RL78_Reg_BC);
|
|
u = mem_get_si (MACR);
|
|
tprintf ("%08x %u + %u * %u = ", u, u, a, b);
|
|
u2 = (u + (unsigned)a * (unsigned)b) & 0xffffffffUL;
|
|
tprintf ("%08x %u\n", u2, u2);
|
|
mem_put_si (MACR, u2);
|
|
a = get_reg (RL78_Reg_PSW);
|
|
if (u2 < u)
|
|
a |= RL78_PSW_CY;
|
|
else
|
|
a &= ~RL78_PSW_CY;
|
|
a &= ~RL78_PSW_AC;
|
|
set_reg (RL78_Reg_PSW, a);
|
|
CLOCKS (3);
|
|
break;
|
|
|
|
case RLO_mulu:
|
|
tprintf ("MULU:");
|
|
a = get_reg (RL78_Reg_A);
|
|
b = get_reg (RL78_Reg_X);
|
|
v = a * b;
|
|
tprintf (" %d * %d = %d\n", a, b, v);
|
|
set_reg (RL78_Reg_AX, v);
|
|
break;
|
|
|
|
case RLO_mulh:
|
|
tprintf ("MUL:");
|
|
a = sign_ext (get_reg (RL78_Reg_AX), 16);
|
|
b = sign_ext (get_reg (RL78_Reg_BC), 16);
|
|
v = a * b;
|
|
tprintf (" %d * %d = %d\n", a, b, v);
|
|
set_reg (RL78_Reg_BC, v >> 16);
|
|
set_reg (RL78_Reg_AX, v);
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
case RLO_mulhu:
|
|
tprintf ("MULHU:");
|
|
a = get_reg (RL78_Reg_AX);
|
|
b = get_reg (RL78_Reg_BC);
|
|
v = a * b;
|
|
tprintf (" %d * %d = %d\n", a, b, v);
|
|
set_reg (RL78_Reg_BC, v >> 16);
|
|
set_reg (RL78_Reg_AX, v);
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
case RLO_nop:
|
|
tprintf ("NOP.\n");
|
|
break;
|
|
|
|
case RLO_or:
|
|
tprintf ("OR:");
|
|
a = GS ();
|
|
b = GD ();
|
|
v = a | b;
|
|
FLAGS (b, v);
|
|
PD (v);
|
|
if (opcode.op[0].type == RL78_Operand_Indirect)
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
case RLO_ret:
|
|
tprintf ("RET: ");
|
|
a = get_reg (RL78_Reg_SP);
|
|
v = mem_get_psi (a | 0xf0000);
|
|
WILD_JUMP_CHECK (v);
|
|
pc = v;
|
|
set_reg (RL78_Reg_SP, a + 4);
|
|
#if 0
|
|
/* Enable this code to dump the return values for each return. */
|
|
if (trace)
|
|
{
|
|
int i;
|
|
skip_init ++;
|
|
for (i = 0; i < 8; i ++)
|
|
printf (" %02x", mem_get_qi (0xffef0 + i) & 0xff);
|
|
skip_init --;
|
|
}
|
|
#endif
|
|
tprintf ("\n");
|
|
CLOCKS (6);
|
|
break;
|
|
|
|
case RLO_reti:
|
|
tprintf ("RETI: ");
|
|
a = get_reg (RL78_Reg_SP);
|
|
v = mem_get_psi (a | 0xf0000);
|
|
WILD_JUMP_CHECK (v);
|
|
pc = v;
|
|
b = mem_get_qi ((a + 3) | 0xf0000);
|
|
set_reg (RL78_Reg_PSW, b);
|
|
set_reg (RL78_Reg_SP, a + 4);
|
|
tprintf ("\n");
|
|
break;
|
|
|
|
case RLO_rol:
|
|
tprintf ("ROL:"); /* d <<= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b << 1;
|
|
v |= (b >> (obits - 1)) & 1;
|
|
set_carry ((b >> (obits - 1)) & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_rolc:
|
|
tprintf ("ROLC:"); /* d <<= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b << 1;
|
|
v |= get_carry ();
|
|
set_carry ((b >> (obits - 1)) & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_ror:
|
|
tprintf ("ROR:"); /* d >>= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b >> 1;
|
|
v |= (b & 1) << (obits - 1);
|
|
set_carry (b & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_rorc:
|
|
tprintf ("RORC:"); /* d >>= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b >> 1;
|
|
v |= (get_carry () << (obits - 1));
|
|
set_carry (b & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_sar:
|
|
tprintf ("SAR:"); /* d >>= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b >> 1;
|
|
v |= b & (1 << (obits - 1));
|
|
set_carry (b & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_sel:
|
|
tprintf ("SEL:");
|
|
a = GS ();
|
|
b = get_reg (RL78_Reg_PSW);
|
|
b &= ~(RL78_PSW_RBS1 | RL78_PSW_RBS0);
|
|
if (a & 1)
|
|
b |= RL78_PSW_RBS0;
|
|
if (a & 2)
|
|
b |= RL78_PSW_RBS1;
|
|
set_reg (RL78_Reg_PSW, b);
|
|
tprintf ("\n");
|
|
break;
|
|
|
|
case RLO_shl:
|
|
tprintf ("SHL%d:", obits); /* d <<= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b << 1;
|
|
tprintf ("b = 0x%x & 0x%x\n", b, 1<<(obits - 1));
|
|
set_carry (b & (1<<(obits - 1)));
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_shr:
|
|
tprintf ("SHR:"); /* d >>= s */
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b;
|
|
while (a --)
|
|
{
|
|
v = b >> 1;
|
|
set_carry (b & 1);
|
|
b = v;
|
|
}
|
|
PD (v);
|
|
break;
|
|
|
|
case RLO_skip:
|
|
tprintf ("SKIP: ");
|
|
if (!condition_true (opcode.op[1].condition, GS ()))
|
|
{
|
|
tprintf (" false\n");
|
|
break;
|
|
}
|
|
|
|
rl78_data.dpc = pc;
|
|
opcode_size = rl78_decode_opcode (pc, &opcode,
|
|
rl78_get_byte, &rl78_data);
|
|
pc += opcode_size;
|
|
tprintf (" skipped: %s\n", opcode.syntax);
|
|
break;
|
|
|
|
case RLO_stop:
|
|
tprintf ("STOP.\n");
|
|
DO_RETURN (RL78_MAKE_EXITED (get_reg (RL78_Reg_A)));
|
|
DO_RETURN (RL78_MAKE_HIT_BREAK ());
|
|
|
|
case RLO_sub:
|
|
tprintf ("SUB: ");
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b - a;
|
|
FLAGS (b, v);
|
|
PD (v);
|
|
tprintf ("%d (0x%x) - %d (0x%x) = %d (0x%x)\n", b, b, a, a, v, v);
|
|
if (opcode.op[0].type == RL78_Operand_Indirect)
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
case RLO_subc:
|
|
tprintf ("SUBC: ");
|
|
a = GS ();
|
|
b = GD ();
|
|
v = b - a - get_carry ();
|
|
FLAGS (b, v);
|
|
PD (v);
|
|
if (opcode.op[0].type == RL78_Operand_Indirect)
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
case RLO_xch:
|
|
tprintf ("XCH: ");
|
|
a = GS ();
|
|
b = GD ();
|
|
PD (a);
|
|
PS (b);
|
|
break;
|
|
|
|
case RLO_xor:
|
|
tprintf ("XOR:");
|
|
a = GS ();
|
|
b = GD ();
|
|
v = a ^ b;
|
|
FLAGS (b, v);
|
|
PD (v);
|
|
if (opcode.op[0].type == RL78_Operand_Indirect)
|
|
CLOCKS (2);
|
|
break;
|
|
|
|
default:
|
|
tprintf ("Unknown opcode?\n");
|
|
DO_RETURN (RL78_MAKE_HIT_BREAK ());
|
|
}
|
|
|
|
if (timer_enabled)
|
|
process_clock_tick ();
|
|
|
|
return RL78_MAKE_STEPPED ();
|
|
}
|