316 lines
9.3 KiB
C
316 lines
9.3 KiB
C
/* Print TI TMS320C80 (MVP) instructions
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Copyright (C) 1996-2014 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "opcode/tic80.h"
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#include "dis-asm.h"
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static int length;
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/* Print an integer operand. Try to be somewhat smart about the
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format by assuming that small positive or negative integers are
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probably loop increment values, structure offsets, or similar
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values that are more meaningful printed as signed decimal values.
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Larger numbers are probably better printed as hex values. */
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static void
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print_operand_integer (struct disassemble_info *info, long value)
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{
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if ((value > 9999 || value < -9999))
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(*info->fprintf_func) (info->stream, "%#lx", value);
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else
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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/* FIXME: depends upon sizeof (long) == sizeof (float) and
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also upon host floating point format matching target
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floating point format. */
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static void
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print_operand_float (struct disassemble_info *info, long value)
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{
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union { float f; long l; } fval;
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fval.l = value;
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(*info->fprintf_func) (info->stream, "%g", fval.f);
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}
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static void
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print_operand_control_register (struct disassemble_info *info, long value)
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{
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const char *tmp;
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tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR);
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if (tmp != NULL)
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(*info->fprintf_func) (info->stream, "%s", tmp);
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else
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(*info->fprintf_func) (info->stream, "%#lx", value);
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}
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static void
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print_operand_condition_code (struct disassemble_info *info, long value)
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{
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const char *tmp;
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tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC);
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if (tmp != NULL)
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(*info->fprintf_func) (info->stream, "%s", tmp);
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else
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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static void
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print_operand_bitnum (struct disassemble_info *info, long value)
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{
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int bitnum;
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const char *tmp;
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bitnum = ~value & 0x1F;
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tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM);
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if (tmp != NULL)
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(*info->fprintf_func) (info->stream, "%s", tmp);
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else
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(*info->fprintf_func) (info->stream, "%d", bitnum);
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}
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/* Print the operand as directed by the flags. */
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#define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17)))
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#define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15)))
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#define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11)))
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static void
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print_operand (struct disassemble_info *info,
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long value,
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unsigned long insn,
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const struct tic80_operand *operand,
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bfd_vma memaddr)
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{
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if ((operand->flags & TIC80_OPERAND_GPR) != 0)
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{
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(*info->fprintf_func) (info->stream, "r%ld", value);
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if (M_SI (insn, operand) || M_LI (insn, operand))
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{
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(*info->fprintf_func) (info->stream, ":m");
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}
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}
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else if ((operand->flags & TIC80_OPERAND_FPA) != 0)
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(*info->fprintf_func) (info->stream, "a%ld", value);
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else if ((operand->flags & TIC80_OPERAND_PCREL) != 0)
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(*info->print_address_func) (memaddr + 4 * value, info);
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else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0)
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(*info->print_address_func) (value, info);
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else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0)
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print_operand_bitnum (info, value);
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else if ((operand->flags & TIC80_OPERAND_CC) != 0)
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print_operand_condition_code (info, value);
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else if ((operand->flags & TIC80_OPERAND_CR) != 0)
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print_operand_control_register (info, value);
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else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0)
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print_operand_float (info, value);
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else if ((operand->flags & TIC80_OPERAND_BITFIELD))
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(*info->fprintf_func) (info->stream, "%#lx", value);
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else
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print_operand_integer (info, value);
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/* If this is a scaled operand, then print the modifier. */
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if (R_SCALED (insn, operand))
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(*info->fprintf_func) (info->stream, ":s");
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}
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/* Get the next 32 bit word from the instruction stream and convert it
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into internal format in the unsigned long INSN, for which we are
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passed the address. Return 0 on success, -1 on error. */
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static int
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fill_instruction (struct disassemble_info *info,
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bfd_vma memaddr,
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unsigned long *insnp)
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{
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bfd_byte buffer[4];
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int status;
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/* Get the bits for the next 32 bit word and put in buffer. */
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status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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/* Read was successful, so increment count of bytes read and convert
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the bits into internal format. */
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length += 4;
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if (info->endian == BFD_ENDIAN_LITTLE)
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*insnp = bfd_getl32 (buffer);
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else if (info->endian == BFD_ENDIAN_BIG)
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*insnp = bfd_getb32 (buffer);
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else
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/* FIXME: Should probably just default to one or the other. */
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abort ();
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return 0;
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}
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/* We have chosen an opcode table entry. */
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static int
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print_one_instruction (struct disassemble_info *info,
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bfd_vma memaddr,
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unsigned long insn,
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const struct tic80_opcode *opcode)
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{
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const struct tic80_operand *operand;
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long value;
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int status;
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const unsigned char *opindex;
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int close_paren;
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(*info->fprintf_func) (info->stream, "%-10s", opcode->name);
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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operand = tic80_operands + *opindex;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, NULL);
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else if (operand->bits == 32)
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{
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status = fill_instruction (info, memaddr, (unsigned long *) &value);
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if (status == -1)
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return status;
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}
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else
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{
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if ((operand->flags & TIC80_OPERAND_SIGNED) != 0
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&& (value & (1 << (operand->bits - 1))) != 0)
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value -= 1 << operand->bits;
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}
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/* If this operand is enclosed in parenthesis, then print
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the open paren, otherwise just print the regular comma
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separator, except for the first operand. */
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if ((operand->flags & TIC80_OPERAND_PARENS) == 0)
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{
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close_paren = 0;
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if (opindex != opcode->operands)
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(*info->fprintf_func) (info->stream, ",");
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}
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else
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{
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close_paren = 1;
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(*info->fprintf_func) (info->stream, "(");
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}
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print_operand (info, value, insn, operand, memaddr);
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/* If we printed an open paren before printing this operand, close
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it now. The flag gets reset on each loop. */
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if (close_paren)
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(*info->fprintf_func) (info->stream, ")");
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}
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return length;
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}
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/* There are no specific bits that tell us for certain whether a vector
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instruction opcode contains one or two instructions. However since
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a destination register of r0 is illegal, we can check for nonzero
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values in both destination register fields. Only opcodes that have
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two valid instructions will have non-zero in both. */
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#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
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static int
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print_instruction (struct disassemble_info *info,
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bfd_vma memaddr,
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unsigned long insn,
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const struct tic80_opcode *vec_opcode)
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{
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const struct tic80_opcode *opcode;
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const struct tic80_opcode *opcode_end;
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/* Find the first opcode match in the opcodes table. For vector
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opcodes (vec_opcode != NULL) find the first match that is not the
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previously found match. FIXME: there should be faster ways to
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search (hash table or binary search), but don't worry too much
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about it until other TIc80 support is finished. */
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opcode_end = tic80_opcodes + tic80_num_opcodes;
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for (opcode = tic80_opcodes; opcode < opcode_end; opcode++)
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{
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if ((insn & opcode->mask) == opcode->opcode &&
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opcode != vec_opcode)
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break;
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}
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if (opcode == opcode_end)
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{
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/* No match found, just print the bits as a .word directive. */
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(*info->fprintf_func) (info->stream, ".word %#08lx", insn);
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}
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else
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{
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/* Match found, decode the instruction. */
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length = print_one_instruction (info, memaddr, insn, opcode);
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if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn))
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{
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/* There is another instruction to print from the same opcode.
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Print the separator and then find and print the other
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instruction. */
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(*info->fprintf_func) (info->stream, " || ");
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length = print_instruction (info, memaddr, insn, opcode);
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}
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}
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return length;
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}
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int
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print_insn_tic80 (bfd_vma memaddr, struct disassemble_info *info)
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{
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unsigned long insn;
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int status;
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length = 0;
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info->bytes_per_line = 8;
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status = fill_instruction (info, memaddr, &insn);
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if (status != -1)
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status = print_instruction (info, memaddr, insn, NULL);
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return status;
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}
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