341 lines
11 KiB
C
341 lines
11 KiB
C
/* Target-dependent code for PowerPC systems running NetBSD.
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Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
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Contributed by Wasabi Systems, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "target.h"
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#include "breakpoint.h"
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#include "value.h"
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#include "osabi.h"
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#include "ppc-tdep.h"
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#include "ppcnbsd-tdep.h"
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#include "nbsd-tdep.h"
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#include "tramp-frame.h"
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#include "trad-frame.h"
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#include "gdb_assert.h"
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#include "solib-svr4.h"
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#define REG_FIXREG_OFFSET(x) ((x) * 4)
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#define REG_LR_OFFSET (32 * 4)
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#define REG_CR_OFFSET (33 * 4)
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#define REG_XER_OFFSET (34 * 4)
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#define REG_CTR_OFFSET (35 * 4)
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#define REG_PC_OFFSET (36 * 4)
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#define SIZEOF_STRUCT_REG (37 * 4)
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#define FPREG_FPR_OFFSET(x) ((x) * 8)
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#define FPREG_FPSCR_OFFSET (32 * 8)
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#define SIZEOF_STRUCT_FPREG (33 * 8)
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void
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ppcnbsd_supply_reg (char *regs, int regno)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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int i;
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for (i = 0; i < ppc_num_gprs; i++)
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{
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if (regno == tdep->ppc_gp0_regnum + i || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_gp0_regnum + i,
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regs + REG_FIXREG_OFFSET (i));
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}
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if (regno == tdep->ppc_lr_regnum || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_lr_regnum,
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regs + REG_LR_OFFSET);
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if (regno == tdep->ppc_cr_regnum || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_cr_regnum,
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regs + REG_CR_OFFSET);
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if (regno == tdep->ppc_xer_regnum || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_xer_regnum,
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regs + REG_XER_OFFSET);
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if (regno == tdep->ppc_ctr_regnum || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_ctr_regnum,
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regs + REG_CTR_OFFSET);
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if (regno == PC_REGNUM || regno == -1)
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regcache_raw_supply (current_regcache, PC_REGNUM,
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regs + REG_PC_OFFSET);
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}
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void
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ppcnbsd_fill_reg (char *regs, int regno)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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int i;
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for (i = 0; i < ppc_num_gprs; i++)
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{
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if (regno == tdep->ppc_gp0_regnum + i || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_gp0_regnum + i,
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regs + REG_FIXREG_OFFSET (i));
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}
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if (regno == tdep->ppc_lr_regnum || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_lr_regnum,
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regs + REG_LR_OFFSET);
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if (regno == tdep->ppc_cr_regnum || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_cr_regnum,
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regs + REG_CR_OFFSET);
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if (regno == tdep->ppc_xer_regnum || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_xer_regnum,
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regs + REG_XER_OFFSET);
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if (regno == tdep->ppc_ctr_regnum || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_ctr_regnum,
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regs + REG_CTR_OFFSET);
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if (regno == PC_REGNUM || regno == -1)
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regcache_raw_collect (current_regcache, PC_REGNUM, regs + REG_PC_OFFSET);
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}
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void
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ppcnbsd_supply_fpreg (char *fpregs, int regno)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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int i;
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/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
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point registers. Traditionally, GDB's register set has still
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listed the floating point registers for such machines, so this
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code is harmless. However, the new E500 port actually omits the
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floating point registers entirely from the register set --- they
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don't even have register numbers assigned to them.
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It's not clear to me how best to update this code, so this assert
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will alert the first person to encounter the NetBSD/E500
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combination to the problem. */
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gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
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for (i = 0; i < ppc_num_fprs; i++)
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{
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if (regno == tdep->ppc_fp0_regnum + i || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_fp0_regnum + i,
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fpregs + FPREG_FPR_OFFSET (i));
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}
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if (regno == tdep->ppc_fpscr_regnum || regno == -1)
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regcache_raw_supply (current_regcache, tdep->ppc_fpscr_regnum,
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fpregs + FPREG_FPSCR_OFFSET);
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}
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void
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ppcnbsd_fill_fpreg (char *fpregs, int regno)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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int i;
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/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
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point registers. Traditionally, GDB's register set has still
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listed the floating point registers for such machines, so this
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code is harmless. However, the new E500 port actually omits the
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floating point registers entirely from the register set --- they
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don't even have register numbers assigned to them.
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It's not clear to me how best to update this code, so this assert
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will alert the first person to encounter the NetBSD/E500
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combination to the problem. */
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gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
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for (i = 0; i < ppc_num_fprs; i++)
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{
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if (regno == tdep->ppc_fp0_regnum + i || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + i,
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fpregs + FPREG_FPR_OFFSET (i));
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}
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if (regno == tdep->ppc_fpscr_regnum || regno == -1)
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regcache_raw_collect (current_regcache, tdep->ppc_fpscr_regnum,
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fpregs + FPREG_FPSCR_OFFSET);
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}
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static void
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fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which,
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CORE_ADDR ignore)
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{
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char *regs, *fpregs;
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/* We get everything from one section. */
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if (which != 0)
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return;
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regs = core_reg_sect;
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fpregs = core_reg_sect + SIZEOF_STRUCT_REG;
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/* Integer registers. */
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ppcnbsd_supply_reg (regs, -1);
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/* Floating point registers. */
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ppcnbsd_supply_fpreg (fpregs, -1);
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}
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static void
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fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, int which,
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CORE_ADDR ignore)
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{
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switch (which)
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{
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case 0: /* Integer registers. */
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if (core_reg_size != SIZEOF_STRUCT_REG)
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warning (_("Wrong size register set in core file."));
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else
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ppcnbsd_supply_reg (core_reg_sect, -1);
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break;
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case 2: /* Floating point registers. */
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if (core_reg_size != SIZEOF_STRUCT_FPREG)
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warning (_("Wrong size FP register set in core file."));
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else
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ppcnbsd_supply_fpreg (core_reg_sect, -1);
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break;
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default:
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/* Don't know what kind of register request this is; just ignore it. */
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break;
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}
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}
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static struct core_fns ppcnbsd_core_fns =
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{
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bfd_target_unknown_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_core_registers, /* core_read_registers */
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NULL /* next */
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};
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static struct core_fns ppcnbsd_elfcore_fns =
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{
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bfd_target_elf_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_elfcore_registers, /* core_read_registers */
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NULL /* next */
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};
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/* NetBSD is confused. It appears that 1.5 was using the correct SVr4
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convention but, 1.6 switched to the below broken convention. For
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the moment use the broken convention. Ulgh!. */
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static enum return_value_convention
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ppcnbsd_return_value (struct gdbarch *gdbarch, struct type *valtype,
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struct regcache *regcache, gdb_byte *readbuf,
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const gdb_byte *writebuf)
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{
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if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
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|| TYPE_CODE (valtype) == TYPE_CODE_UNION)
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&& !((TYPE_LENGTH (valtype) == 16 || TYPE_LENGTH (valtype) == 8)
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&& TYPE_VECTOR (valtype))
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&& !(TYPE_LENGTH (valtype) == 1
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|| TYPE_LENGTH (valtype) == 2
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|| TYPE_LENGTH (valtype) == 4
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|| TYPE_LENGTH (valtype) == 8))
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return RETURN_VALUE_STRUCT_CONVENTION;
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else
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return ppc_sysv_abi_broken_return_value (gdbarch, valtype, regcache,
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readbuf, writebuf);
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}
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static void
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ppcnbsd_sigtramp_cache_init (const struct tramp_frame *self,
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struct frame_info *next_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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CORE_ADDR base;
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CORE_ADDR offset;
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int i;
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struct gdbarch *gdbarch = get_frame_arch (next_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
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offset = base + 0x18 + 2 * tdep->wordsize;
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for (i = 0; i < ppc_num_gprs; i++)
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{
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int regnum = i + tdep->ppc_gp0_regnum;
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trad_frame_set_reg_addr (this_cache, regnum, offset);
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offset += tdep->wordsize;
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}
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trad_frame_set_reg_addr (this_cache, tdep->ppc_lr_regnum, offset);
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offset += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_cr_regnum, offset);
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offset += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_xer_regnum, offset);
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offset += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_ctr_regnum, offset);
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offset += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, PC_REGNUM, offset); /* SRR0? */
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offset += tdep->wordsize;
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/* Construct the frame ID using the function start. */
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trad_frame_set_id (this_cache, frame_id_build (base, func));
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}
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/* Given the NEXT frame, examine the instructions at and around this
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frame's resume address (aka PC) to see of they look like a signal
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trampoline. Return the address of the trampolines first
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instruction, or zero if it isn't a signal trampoline. */
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static const struct tramp_frame ppcnbsd_sigtramp = {
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SIGTRAMP_FRAME,
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4, /* insn size */
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{ /* insn */
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{ 0x38610018, -1 }, /* addi r3,r1,24 */
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{ 0x38000127, -1 }, /* li r0,295 */
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{ 0x44000002, -1 }, /* sc */
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{ 0x38000001, -1 }, /* li r0,1 */
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{ 0x44000002, -1 }, /* sc */
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{ TRAMP_SENTINEL_INSN, -1 }
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},
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ppcnbsd_sigtramp_cache_init
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};
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static void
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ppcnbsd_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch)
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{
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/* For NetBSD, this is an on again, off again thing. Some systems
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do use the broken struct convention, and some don't. */
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set_gdbarch_return_value (gdbarch, ppcnbsd_return_value);
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
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nbsd_ilp32_solib_svr4_fetch_link_map_offsets);
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tramp_frame_prepend_unwinder (gdbarch, &ppcnbsd_sigtramp);
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}
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void
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_initialize_ppcnbsd_tdep (void)
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{
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gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_NETBSD_ELF,
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ppcnbsd_init_abi);
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deprecated_add_core_fns (&ppcnbsd_core_fns);
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deprecated_add_core_fns (&ppcnbsd_elfcore_fns);
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}
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