4390 lines
111 KiB
C
4390 lines
111 KiB
C
/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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Modifications to add arch. v4 support by <jsmith@cygnus.com>.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "armdefs.h"
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#include "armemu.h"
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#include "armos.h"
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static ARMword GetDPRegRHS (ARMul_State * state, ARMword instr);
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static ARMword GetDPSRegRHS (ARMul_State * state, ARMword instr);
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static void WriteR15 (ARMul_State * state, ARMword src);
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static void WriteSR15 (ARMul_State * state, ARMword src);
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static void WriteR15Branch (ARMul_State * state, ARMword src);
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static ARMword GetLSRegRHS (ARMul_State * state, ARMword instr);
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static ARMword GetLS7RHS (ARMul_State * state, ARMword instr);
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static unsigned LoadWord (ARMul_State * state, ARMword instr,
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ARMword address);
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static unsigned LoadHalfWord (ARMul_State * state, ARMword instr,
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ARMword address, int signextend);
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static unsigned LoadByte (ARMul_State * state, ARMword instr, ARMword address,
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int signextend);
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static unsigned StoreWord (ARMul_State * state, ARMword instr,
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ARMword address);
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static unsigned StoreHalfWord (ARMul_State * state, ARMword instr,
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ARMword address);
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static unsigned StoreByte (ARMul_State * state, ARMword instr,
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ARMword address);
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static void LoadMult (ARMul_State * state, ARMword address, ARMword instr,
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ARMword WBBase);
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static void StoreMult (ARMul_State * state, ARMword address, ARMword instr,
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ARMword WBBase);
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static void LoadSMult (ARMul_State * state, ARMword address, ARMword instr,
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ARMword WBBase);
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static void StoreSMult (ARMul_State * state, ARMword address, ARMword instr,
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ARMword WBBase);
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static unsigned Multiply64 (ARMul_State * state, ARMword instr,
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int signextend, int scc);
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static unsigned MultiplyAdd64 (ARMul_State * state, ARMword instr,
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int signextend, int scc);
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#define LUNSIGNED (0) /* unsigned operation */
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#define LSIGNED (1) /* signed operation */
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#define LDEFAULT (0) /* default : do nothing */
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#define LSCC (1) /* set condition codes on result */
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#ifdef NEED_UI_LOOP_HOOK
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/* How often to run the ui_loop update, when in use */
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#define UI_LOOP_POLL_INTERVAL 0x32000
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/* Counter for the ui_loop_hook update */
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static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
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/* Actual hook to call to run through gdb's gui event loop */
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extern int (*ui_loop_hook) (int);
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#endif /* NEED_UI_LOOP_HOOK */
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extern int stop_simulator;
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/***************************************************************************\
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* short-hand macros for LDR/STR *
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\***************************************************************************/
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/* store post decrement writeback */
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#define SHDOWNWB() \
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lhs = LHS ; \
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if (StoreHalfWord(state, instr, lhs)) \
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LSBase = lhs - GetLS7RHS(state, instr) ;
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/* store post increment writeback */
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#define SHUPWB() \
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lhs = LHS ; \
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if (StoreHalfWord(state, instr, lhs)) \
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LSBase = lhs + GetLS7RHS(state, instr) ;
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/* store pre decrement */
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#define SHPREDOWN() \
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(void)StoreHalfWord(state, instr, LHS - GetLS7RHS(state, instr)) ;
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/* store pre decrement writeback */
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#define SHPREDOWNWB() \
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temp = LHS - GetLS7RHS(state, instr) ; \
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if (StoreHalfWord(state, instr, temp)) \
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LSBase = temp ;
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/* store pre increment */
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#define SHPREUP() \
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(void)StoreHalfWord(state, instr, LHS + GetLS7RHS(state, instr)) ;
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/* store pre increment writeback */
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#define SHPREUPWB() \
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temp = LHS + GetLS7RHS(state, instr) ; \
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if (StoreHalfWord(state, instr, temp)) \
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LSBase = temp ;
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/* Load post decrement writeback. */
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#define LHPOSTDOWN() \
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{ \
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int done = 1; \
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lhs = LHS; \
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temp = lhs - GetLS7RHS (state, instr); \
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\
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switch (BITS (5, 6)) \
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{ \
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case 1: /* H */ \
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if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
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LSBase = temp; \
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break; \
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case 2: /* SB */ \
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if (LoadByte (state, instr, lhs, LSIGNED)) \
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LSBase = temp; \
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break; \
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case 3: /* SH */ \
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if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
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LSBase = temp; \
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break; \
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case 0: /* SWP handled elsewhere. */ \
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default: \
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done = 0; \
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break; \
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} \
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if (done) \
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break; \
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}
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/* Load post increment writeback. */
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#define LHPOSTUP() \
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{ \
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int done = 1; \
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lhs = LHS; \
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temp = lhs + GetLS7RHS (state, instr); \
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\
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switch (BITS (5, 6)) \
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{ \
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case 1: /* H */ \
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if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
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LSBase = temp; \
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break; \
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case 2: /* SB */ \
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if (LoadByte (state, instr, lhs, LSIGNED)) \
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LSBase = temp; \
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break; \
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case 3: /* SH */ \
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if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
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LSBase = temp; \
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break; \
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case 0: /* SWP handled elsewhere. */ \
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default: \
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done = 0; \
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break; \
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} \
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if (done) \
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break; \
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}
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/* load pre decrement */
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#define LHPREDOWN() \
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{ \
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int done = 1 ; \
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temp = LHS - GetLS7RHS(state,instr) ; \
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switch (BITS(5,6)) { \
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case 1: /* H */ \
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(void)LoadHalfWord(state,instr,temp,LUNSIGNED) ; \
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break ; \
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case 2: /* SB */ \
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(void)LoadByte(state,instr,temp,LSIGNED) ; \
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break ; \
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case 3: /* SH */ \
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(void)LoadHalfWord(state,instr,temp,LSIGNED) ; \
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break ; \
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case 0: /* SWP handled elsewhere */ \
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default: \
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done = 0 ; \
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break ; \
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} \
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if (done) \
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break ; \
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}
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/* load pre decrement writeback */
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#define LHPREDOWNWB() \
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{ \
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int done = 1 ; \
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temp = LHS - GetLS7RHS(state, instr) ; \
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switch (BITS(5,6)) { \
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case 1: /* H */ \
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if (LoadHalfWord(state,instr,temp,LUNSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 2: /* SB */ \
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if (LoadByte(state,instr,temp,LSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 3: /* SH */ \
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if (LoadHalfWord(state,instr,temp,LSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 0: /* SWP handled elsewhere */ \
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default: \
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done = 0 ; \
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break ; \
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} \
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if (done) \
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break ; \
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}
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/* load pre increment */
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#define LHPREUP() \
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{ \
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int done = 1 ; \
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temp = LHS + GetLS7RHS(state,instr) ; \
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switch (BITS(5,6)) { \
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case 1: /* H */ \
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(void)LoadHalfWord(state,instr,temp,LUNSIGNED) ; \
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break ; \
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case 2: /* SB */ \
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(void)LoadByte(state,instr,temp,LSIGNED) ; \
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break ; \
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case 3: /* SH */ \
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(void)LoadHalfWord(state,instr,temp,LSIGNED) ; \
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break ; \
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case 0: /* SWP handled elsewhere */ \
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default: \
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done = 0 ; \
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break ; \
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} \
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if (done) \
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break ; \
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}
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/* load pre increment writeback */
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#define LHPREUPWB() \
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{ \
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int done = 1 ; \
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temp = LHS + GetLS7RHS(state, instr) ; \
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switch (BITS(5,6)) { \
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case 1: /* H */ \
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if (LoadHalfWord(state,instr,temp,LUNSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 2: /* SB */ \
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if (LoadByte(state,instr,temp,LSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 3: /* SH */ \
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if (LoadHalfWord(state,instr,temp,LSIGNED)) \
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LSBase = temp ; \
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break ; \
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case 0: /* SWP handled elsewhere */ \
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default: \
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done = 0 ; \
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break ; \
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} \
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if (done) \
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break ; \
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}
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/***************************************************************************\
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* EMULATION of ARM6 *
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\***************************************************************************/
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/* The PC pipeline value depends on whether ARM or Thumb instructions
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are being executed: */
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ARMword isize;
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#ifdef MODE32
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ARMword
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ARMul_Emulate32 (register ARMul_State * state)
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{
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#else
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ARMword
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ARMul_Emulate26 (register ARMul_State * state)
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{
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#endif
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register ARMword instr, /* the current instruction */
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dest = 0, /* almost the DestBus */
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temp, /* ubiquitous third hand */
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pc = 0; /* the address of the current instruction */
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ARMword lhs, rhs; /* almost the ABus and BBus */
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ARMword decoded = 0, loaded = 0; /* instruction pipeline */
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/***************************************************************************\
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* Execute the next instruction *
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\***************************************************************************/
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if (state->NextInstr < PRIMEPIPE)
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{
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decoded = state->decoded;
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loaded = state->loaded;
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pc = state->pc;
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}
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do
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{ /* just keep going */
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isize = INSN_SIZE;
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switch (state->NextInstr)
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{
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case SEQ:
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state->Reg[15] += isize; /* Advance the pipeline, and an S cycle */
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pc += isize;
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instr = decoded;
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decoded = loaded;
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loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
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break;
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case NONSEQ:
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state->Reg[15] += isize; /* Advance the pipeline, and an N cycle */
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pc += isize;
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instr = decoded;
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decoded = loaded;
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loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
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NORMALCYCLE;
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break;
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case PCINCEDSEQ:
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pc += isize; /* Program counter advanced, and an S cycle */
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instr = decoded;
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decoded = loaded;
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loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
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NORMALCYCLE;
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break;
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case PCINCEDNONSEQ:
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pc += isize; /* Program counter advanced, and an N cycle */
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instr = decoded;
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decoded = loaded;
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loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
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NORMALCYCLE;
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break;
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case RESUME: /* The program counter has been changed */
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pc = state->Reg[15];
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#ifndef MODE32
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pc = pc & R15PCBITS;
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#endif
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state->Reg[15] = pc + (isize * 2);
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state->Aborted = 0;
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instr = ARMul_ReLoadInstr (state, pc, isize);
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decoded = ARMul_ReLoadInstr (state, pc + isize, isize);
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loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize);
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NORMALCYCLE;
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break;
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default: /* The program counter has been changed */
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pc = state->Reg[15];
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#ifndef MODE32
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pc = pc & R15PCBITS;
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#endif
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state->Reg[15] = pc + (isize * 2);
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state->Aborted = 0;
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instr = ARMul_LoadInstrN (state, pc, isize);
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decoded = ARMul_LoadInstrS (state, pc + (isize), isize);
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loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
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NORMALCYCLE;
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break;
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}
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if (state->EventSet)
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ARMul_EnvokeEvent (state);
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#if 0
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/* Enable this for a helpful bit of debugging when tracing is needed. */
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fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
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if (instr == 0)
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abort ();
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#endif
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if (state->Exception)
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{ /* Any exceptions */
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if (state->NresetSig == LOW)
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{
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ARMul_Abort (state, ARMul_ResetV);
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break;
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}
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else if (!state->NfiqSig && !FFLAG)
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{
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ARMul_Abort (state, ARMul_FIQV);
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break;
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}
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else if (!state->NirqSig && !IFLAG)
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{
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ARMul_Abort (state, ARMul_IRQV);
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break;
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}
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}
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if (state->CallDebug > 0)
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{
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instr = ARMul_Debug (state, pc, instr);
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if (state->Emulate < ONCE)
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{
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state->NextInstr = RESUME;
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break;
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}
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if (state->Debug)
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{
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fprintf (stderr, "At %08lx Instr %08lx Mode %02lx\n", pc, instr,
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state->Mode);
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(void) fgetc (stdin);
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}
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}
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else if (state->Emulate < ONCE)
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{
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state->NextInstr = RESUME;
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break;
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}
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state->NumInstrs++;
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#ifdef MODET
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/* Provide Thumb instruction decoding. If the processor is in Thumb
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mode, then we can simply decode the Thumb instruction, and map it
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to the corresponding ARM instruction (by directly loading the
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instr variable, and letting the normal ARM simulator
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execute). There are some caveats to ensure that the correct
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pipelined PC value is used when executing Thumb code, and also for
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dealing with the BL instruction. */
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if (TFLAG)
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{ /* check if in Thumb mode */
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ARMword new;
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switch (ARMul_ThumbDecode (state, pc, instr, &new))
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{
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case t_undefined:
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ARMul_UndefInstr (state, instr); /* This is a Thumb instruction */
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goto donext;
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case t_branch: /* already processed */
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goto donext;
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case t_decoded: /* ARM instruction available */
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instr = new; /* so continue instruction decoding */
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break;
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}
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}
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#endif
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/***************************************************************************\
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* Check the condition codes *
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\***************************************************************************/
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if ((temp = TOPBITS (28)) == AL)
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goto mainswitch; /* vile deed in the need for speed */
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switch ((int) TOPBITS (28))
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{ /* check the condition code */
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case AL:
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temp = TRUE;
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break;
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case NV:
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if (state->is_v5)
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{
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if (BITS (25, 27) == 5) /* BLX(1) */
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{
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ARMword dest;
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state->Reg[14] = pc + 4;
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dest = pc + 8 + 1; /* Force entry into Thumb mode. */
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if (BIT (23))
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dest += (NEGBRANCH + (BIT (24) << 1));
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else
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dest += POSBRANCH + (BIT (24) << 1);
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WriteR15Branch (state, dest);
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goto donext;
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}
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else if ((instr & 0xFC70F000) == 0xF450F000)
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/* The PLD instruction. Ignored. */
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goto donext;
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else
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/* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */
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ARMul_UndefInstr (state, instr);
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}
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temp = FALSE;
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break;
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case EQ:
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temp = ZFLAG;
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break;
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case NE:
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temp = !ZFLAG;
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break;
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case VS:
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temp = VFLAG;
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break;
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case VC:
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temp = !VFLAG;
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break;
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case MI:
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temp = NFLAG;
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break;
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case PL:
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temp = !NFLAG;
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break;
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case CS:
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temp = CFLAG;
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break;
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case CC:
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temp = !CFLAG;
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break;
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case HI:
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temp = (CFLAG && !ZFLAG);
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break;
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case LS:
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temp = (!CFLAG || ZFLAG);
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break;
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case GE:
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temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
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break;
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case LT:
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temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
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break;
|
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case GT:
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temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
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break;
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case LE:
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temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
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break;
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} /* cc check */
|
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|
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/***************************************************************************\
|
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* Actual execution of instructions begins here *
|
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\***************************************************************************/
|
|
|
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if (temp)
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{ /* if the condition codes don't match, stop here */
|
|
mainswitch:
|
|
|
|
if (state->is_XScale)
|
|
{
|
|
if (BIT (20) == 0 && BITS (25, 27) == 0)
|
|
{
|
|
if (BITS (4, 7) == 0xD)
|
|
{
|
|
/* XScale Load Consecutive insn. */
|
|
ARMword temp = GetLS7RHS (state, instr);
|
|
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
|
|
ARMword addr = BIT (24) ? temp2 : temp;
|
|
|
|
if (BIT (12))
|
|
ARMul_UndefInstr (state, instr);
|
|
else if (addr & 7)
|
|
/* Alignment violation. */
|
|
ARMul_Abort (state, ARMul_DataAbortV);
|
|
else
|
|
{
|
|
int wb = BIT (24) && BIT (21);
|
|
|
|
state->Reg[BITS (12, 15)] =
|
|
ARMul_LoadWordN (state, addr);
|
|
state->Reg[BITS (12, 15) + 1] =
|
|
ARMul_LoadWordN (state, addr + 4);
|
|
if (wb)
|
|
LSBase = addr;
|
|
}
|
|
|
|
goto donext;
|
|
}
|
|
else if (BITS (4, 7) == 0xF)
|
|
{
|
|
/* XScale Store Consecutive insn. */
|
|
ARMword temp = GetLS7RHS (state, instr);
|
|
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
|
|
ARMword addr = BIT (24) ? temp2 : temp;
|
|
|
|
if (BIT (12))
|
|
ARMul_UndefInstr (state, instr);
|
|
else if (addr & 7)
|
|
/* Alignment violation. */
|
|
ARMul_Abort (state, ARMul_DataAbortV);
|
|
else
|
|
{
|
|
ARMul_StoreWordN (state, addr,
|
|
state->Reg[BITS (12, 15)]);
|
|
ARMul_StoreWordN (state, addr + 4,
|
|
state->Reg[BITS (12, 15) + 1]);
|
|
|
|
if (BIT (21))
|
|
LSBase = addr;
|
|
}
|
|
|
|
goto donext;
|
|
}
|
|
}
|
|
}
|
|
|
|
switch ((int) BITS (20, 27))
|
|
{
|
|
|
|
/***************************************************************************\
|
|
* Data Processing Register RHS Instructions *
|
|
\***************************************************************************/
|
|
|
|
case 0x00: /* AND reg and MUL */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, no write-back, down, post indexed */
|
|
SHDOWNWB ();
|
|
break;
|
|
}
|
|
/* TODO: CHECK: should 0xD and 0xF generate undefined intruction aborts? */
|
|
#endif
|
|
if (BITS (4, 7) == 9)
|
|
{ /* MUL */
|
|
rhs = state->Reg[MULRHSReg];
|
|
if (MULLHSReg == MULDESTReg)
|
|
{
|
|
UNDEF_MULDestEQOp1;
|
|
state->Reg[MULDESTReg] = 0;
|
|
}
|
|
else if (MULDESTReg != 15)
|
|
state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs;
|
|
else
|
|
{
|
|
UNDEF_MULPCDest;
|
|
}
|
|
for (dest = 0, temp = 0; dest < 32; dest++)
|
|
if (rhs & (1L << dest))
|
|
temp = dest; /* mult takes this many/2 I cycles */
|
|
ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
|
|
}
|
|
else
|
|
{ /* AND reg */
|
|
rhs = DPRegRHS;
|
|
dest = LHS & rhs;
|
|
WRITEDEST (dest);
|
|
}
|
|
break;
|
|
|
|
case 0x01: /* ANDS reg and MULS */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, no write-back, down, post indexed */
|
|
LHPOSTDOWN ();
|
|
/* fall through to rest of decoding */
|
|
}
|
|
#endif
|
|
if (BITS (4, 7) == 9)
|
|
{ /* MULS */
|
|
rhs = state->Reg[MULRHSReg];
|
|
if (MULLHSReg == MULDESTReg)
|
|
{
|
|
UNDEF_MULDestEQOp1;
|
|
state->Reg[MULDESTReg] = 0;
|
|
CLEARN;
|
|
SETZ;
|
|
}
|
|
else if (MULDESTReg != 15)
|
|
{
|
|
dest = state->Reg[MULLHSReg] * rhs;
|
|
ARMul_NegZero (state, dest);
|
|
state->Reg[MULDESTReg] = dest;
|
|
}
|
|
else
|
|
{
|
|
UNDEF_MULPCDest;
|
|
}
|
|
for (dest = 0, temp = 0; dest < 32; dest++)
|
|
if (rhs & (1L << dest))
|
|
temp = dest; /* mult takes this many/2 I cycles */
|
|
ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
|
|
}
|
|
else
|
|
{ /* ANDS reg */
|
|
rhs = DPSRegRHS;
|
|
dest = LHS & rhs;
|
|
WRITESDEST (dest);
|
|
}
|
|
break;
|
|
|
|
case 0x02: /* EOR reg and MLA */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, write-back, down, post indexed */
|
|
SHDOWNWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
if (BITS (4, 7) == 9)
|
|
{ /* MLA */
|
|
rhs = state->Reg[MULRHSReg];
|
|
if (MULLHSReg == MULDESTReg)
|
|
{
|
|
UNDEF_MULDestEQOp1;
|
|
state->Reg[MULDESTReg] = state->Reg[MULACCReg];
|
|
}
|
|
else if (MULDESTReg != 15)
|
|
state->Reg[MULDESTReg] =
|
|
state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
|
|
else
|
|
{
|
|
UNDEF_MULPCDest;
|
|
}
|
|
for (dest = 0, temp = 0; dest < 32; dest++)
|
|
if (rhs & (1L << dest))
|
|
temp = dest; /* mult takes this many/2 I cycles */
|
|
ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
|
|
}
|
|
else
|
|
{
|
|
rhs = DPRegRHS;
|
|
dest = LHS ^ rhs;
|
|
WRITEDEST (dest);
|
|
}
|
|
break;
|
|
|
|
case 0x03: /* EORS reg and MLAS */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, write-back, down, post-indexed */
|
|
LHPOSTDOWN ();
|
|
/* fall through to rest of the decoding */
|
|
}
|
|
#endif
|
|
if (BITS (4, 7) == 9)
|
|
{ /* MLAS */
|
|
rhs = state->Reg[MULRHSReg];
|
|
if (MULLHSReg == MULDESTReg)
|
|
{
|
|
UNDEF_MULDestEQOp1;
|
|
dest = state->Reg[MULACCReg];
|
|
ARMul_NegZero (state, dest);
|
|
state->Reg[MULDESTReg] = dest;
|
|
}
|
|
else if (MULDESTReg != 15)
|
|
{
|
|
dest =
|
|
state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
|
|
ARMul_NegZero (state, dest);
|
|
state->Reg[MULDESTReg] = dest;
|
|
}
|
|
else
|
|
{
|
|
UNDEF_MULPCDest;
|
|
}
|
|
for (dest = 0, temp = 0; dest < 32; dest++)
|
|
if (rhs & (1L << dest))
|
|
temp = dest; /* mult takes this many/2 I cycles */
|
|
ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
|
|
}
|
|
else
|
|
{ /* EORS Reg */
|
|
rhs = DPSRegRHS;
|
|
dest = LHS ^ rhs;
|
|
WRITESDEST (dest);
|
|
}
|
|
break;
|
|
|
|
case 0x04: /* SUB reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, no write-back, down, post indexed */
|
|
SHDOWNWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS - rhs;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x05: /* SUBS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, no write-back, down, post indexed */
|
|
LHPOSTDOWN ();
|
|
/* fall through to the rest of the instruction decoding */
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs - rhs;
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x06: /* RSB reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, write-back, down, post indexed */
|
|
SHDOWNWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = rhs - LHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x07: /* RSBS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, write-back, down, post indexed */
|
|
LHPOSTDOWN ();
|
|
/* fall through to remainder of instruction decoding */
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = rhs - lhs;
|
|
if ((rhs >= lhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, rhs, lhs, dest);
|
|
ARMul_SubOverflow (state, rhs, lhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x08: /* ADD reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, no write-back, up, post indexed */
|
|
SHUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32 = 64 */
|
|
ARMul_Icycles (state,
|
|
Multiply64 (state, instr, LUNSIGNED,
|
|
LDEFAULT), 0L);
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS + rhs;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x09: /* ADDS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, no write-back, up, post indexed */
|
|
LHPOSTUP ();
|
|
/* fall through to remaining instruction decoding */
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
Multiply64 (state, instr, LUNSIGNED, LSCC),
|
|
0L);
|
|
break;
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs + rhs;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x0a: /* ADC reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, write-back, up, post-indexed */
|
|
SHUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
MultiplyAdd64 (state, instr, LUNSIGNED,
|
|
LDEFAULT), 0L);
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS + rhs + CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x0b: /* ADCS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, write-back, up, post indexed */
|
|
LHPOSTUP ();
|
|
/* fall through to remaining instruction decoding */
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
MultiplyAdd64 (state, instr, LUNSIGNED,
|
|
LSCC), 0L);
|
|
break;
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs + rhs + CFLAG;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x0c: /* SBC reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, no write-back, up post indexed */
|
|
SHUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
Multiply64 (state, instr, LSIGNED, LDEFAULT),
|
|
0L);
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS - rhs - !CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x0d: /* SBCS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, no write-back, up, post indexed */
|
|
LHPOSTUP ();
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
Multiply64 (state, instr, LSIGNED, LSCC),
|
|
0L);
|
|
break;
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs - rhs - !CFLAG;
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x0e: /* RSC reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, write-back, up, post indexed */
|
|
SHUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
MultiplyAdd64 (state, instr, LSIGNED,
|
|
LDEFAULT), 0L);
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = rhs - LHS - !CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x0f: /* RSCS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, write-back, up, post indexed */
|
|
LHPOSTUP ();
|
|
/* fall through to remaining instruction decoding */
|
|
}
|
|
#endif
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0x9)
|
|
{ /* MULL */
|
|
/* 32x32=64 */
|
|
ARMul_Icycles (state,
|
|
MultiplyAdd64 (state, instr, LSIGNED, LSCC),
|
|
0L);
|
|
break;
|
|
}
|
|
#endif
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = rhs - lhs - !CFLAG;
|
|
if ((rhs >= lhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, rhs, lhs, dest);
|
|
ARMul_SubOverflow (state, rhs, lhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x10: /* TST reg and MRS CPSR and SWP word */
|
|
if (state->is_v5e)
|
|
{
|
|
if (BIT (4) == 0 && BIT (7) == 1)
|
|
{
|
|
/* ElSegundo SMLAxy insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (8, 11)];
|
|
ARMword Rn = state->Reg[BITS (12, 15)];
|
|
|
|
if (BIT (5))
|
|
op1 >>= 16;
|
|
if (BIT (6))
|
|
op2 >>= 16;
|
|
op1 &= 0xFFFF;
|
|
op2 &= 0xFFFF;
|
|
if (op1 & 0x8000)
|
|
op1 -= 65536;
|
|
if (op2 & 0x8000)
|
|
op2 -= 65536;
|
|
op1 *= op2;
|
|
|
|
if (AddOverflow (op1, Rn, op1 + Rn))
|
|
SETS;
|
|
state->Reg[BITS (16, 19)] = op1 + Rn;
|
|
break;
|
|
}
|
|
|
|
if (BITS (4, 11) == 5)
|
|
{
|
|
/* ElSegundo QADD insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (16, 19)];
|
|
ARMword result = op1 + op2;
|
|
if (AddOverflow (op1, op2, result))
|
|
{
|
|
result = POS (result) ? 0x80000000 : 0x7fffffff;
|
|
SETS;
|
|
}
|
|
state->Reg[BITS (12, 15)] = result;
|
|
break;
|
|
}
|
|
}
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, no write-back, down, pre indexed */
|
|
SHPREDOWN ();
|
|
break;
|
|
}
|
|
#endif
|
|
if (BITS (4, 11) == 9)
|
|
{ /* SWP */
|
|
UNDEF_SWPPC;
|
|
temp = LHS;
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (VECTORACCESS (temp) || ADDREXCEPT (temp))
|
|
{
|
|
INTERNALABORT (temp);
|
|
(void) ARMul_LoadWordN (state, temp);
|
|
(void) ARMul_LoadWordN (state, temp);
|
|
}
|
|
else
|
|
#endif
|
|
dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]);
|
|
if (temp & 3)
|
|
DEST = ARMul_Align (state, temp, dest);
|
|
else
|
|
DEST = dest;
|
|
if (state->abortSig || state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
}
|
|
}
|
|
else if ((BITS (0, 11) == 0) && (LHSReg == 15))
|
|
{ /* MRS CPSR */
|
|
UNDEF_MRSPC;
|
|
DEST = ECC | EINT | EMODE;
|
|
}
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x11: /* TSTP reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, no write-back, down, pre indexed */
|
|
LHPREDOWN ();
|
|
/* continue with remaining instruction decode */
|
|
}
|
|
#endif
|
|
if (DESTReg == 15)
|
|
{ /* TSTP reg */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
rhs = DPRegRHS;
|
|
temp = LHS & rhs;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
}
|
|
else
|
|
{ /* TST reg */
|
|
rhs = DPSRegRHS;
|
|
dest = LHS & rhs;
|
|
ARMul_NegZero (state, dest);
|
|
}
|
|
break;
|
|
|
|
case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6) */
|
|
if (state->is_v5)
|
|
{
|
|
if (BITS (4, 7) == 3)
|
|
{
|
|
/* BLX(2) */
|
|
ARMword temp;
|
|
|
|
if (TFLAG)
|
|
temp = (pc + 2) | 1;
|
|
else
|
|
temp = pc + 4;
|
|
|
|
WriteR15Branch (state, state->Reg[RHSReg]);
|
|
state->Reg[14] = temp;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (state->is_v5e)
|
|
{
|
|
if (BIT (4) == 0 && BIT (7) == 1
|
|
&& (BIT (5) == 0 || BITS (12, 15) == 0))
|
|
{
|
|
/* ElSegundo SMLAWy/SMULWy insn. */
|
|
unsigned long long op1 = state->Reg[BITS (0, 3)];
|
|
unsigned long long op2 = state->Reg[BITS (8, 11)];
|
|
unsigned long long result;
|
|
|
|
if (BIT (6))
|
|
op2 >>= 16;
|
|
if (op1 & 0x80000000)
|
|
op1 -= 1ULL << 32;
|
|
op2 &= 0xFFFF;
|
|
if (op2 & 0x8000)
|
|
op2 -= 65536;
|
|
result = (op1 * op2) >> 16;
|
|
|
|
if (BIT (5) == 0)
|
|
{
|
|
ARMword Rn = state->Reg[BITS (12, 15)];
|
|
|
|
if (AddOverflow (result, Rn, result + Rn))
|
|
SETS;
|
|
result += Rn;
|
|
}
|
|
state->Reg[BITS (16, 19)] = result;
|
|
break;
|
|
}
|
|
|
|
if (BITS (4, 11) == 5)
|
|
{
|
|
/* ElSegundo QSUB insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (16, 19)];
|
|
ARMword result = op1 - op2;
|
|
|
|
if (SubOverflow (op1, op2, result))
|
|
{
|
|
result = POS (result) ? 0x80000000 : 0x7fffffff;
|
|
SETS;
|
|
}
|
|
|
|
state->Reg[BITS (12, 15)] = result;
|
|
break;
|
|
}
|
|
}
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, write-back, down, pre indexed */
|
|
SHPREDOWNWB ();
|
|
break;
|
|
}
|
|
if (BITS (4, 27) == 0x12FFF1)
|
|
{
|
|
/* BX */
|
|
WriteR15Branch (state, state->Reg[RHSReg]);
|
|
break;
|
|
}
|
|
#endif
|
|
if (state->is_v5)
|
|
{
|
|
if (BITS (4, 7) == 0x7)
|
|
{
|
|
ARMword value;
|
|
extern int SWI_vector_installed;
|
|
|
|
/* Hardware is allowed to optionally override this
|
|
instruction and treat it as a breakpoint. Since
|
|
this is a simulator not hardware, we take the position
|
|
that if a SWI vector was not installed, then an Abort
|
|
vector was probably not installed either, and so
|
|
normally this instruction would be ignored, even if an
|
|
Abort is generated. This is a bad thing, since GDB
|
|
uses this instruction for its breakpoints (at least in
|
|
Thumb mode it does). So intercept the instruction here
|
|
and generate a breakpoint SWI instead. */
|
|
if (! SWI_vector_installed)
|
|
ARMul_OSHandleSWI (state, SWI_Breakpoint);
|
|
else
|
|
|
|
/* BKPT - normally this will cause an abort, but for the
|
|
XScale if bit 31 in register 10 of coprocessor 14 is
|
|
clear, then this is treated as a no-op. */
|
|
if (state->is_XScale)
|
|
{
|
|
if (read_cp14_reg (10) & (1UL << 31))
|
|
{
|
|
ARMword value;
|
|
|
|
value = read_cp14_reg (10);
|
|
value &= ~0x1c;
|
|
value |= 0xc;
|
|
|
|
write_cp14_reg (10, value);
|
|
write_cp15_reg (5, 0, 0, 0x200); /* Set FSR. */
|
|
write_cp15_reg (6, 0, 0, pc); /* Set FAR. */
|
|
}
|
|
else
|
|
break;
|
|
}
|
|
|
|
ARMul_Abort (state, ARMul_PrefetchAbortV);
|
|
break;
|
|
}
|
|
}
|
|
if (DESTReg == 15)
|
|
{
|
|
/* MSR reg to CPSR */
|
|
UNDEF_MSRPC;
|
|
temp = DPRegRHS;
|
|
#ifdef MODET
|
|
/* Don't allow TBIT to be set by MSR. */
|
|
temp &= ~ TBIT;
|
|
#endif
|
|
ARMul_FixCPSR (state, instr, temp);
|
|
}
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x13: /* TEQP reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, write-back, down, pre indexed */
|
|
LHPREDOWNWB ();
|
|
/* continue with remaining instruction decode */
|
|
}
|
|
#endif
|
|
if (DESTReg == 15)
|
|
{ /* TEQP reg */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
rhs = DPRegRHS;
|
|
temp = LHS ^ rhs;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
}
|
|
else
|
|
{ /* TEQ Reg */
|
|
rhs = DPSRegRHS;
|
|
dest = LHS ^ rhs;
|
|
ARMul_NegZero (state, dest);
|
|
}
|
|
break;
|
|
|
|
case 0x14: /* CMP reg and MRS SPSR and SWP byte */
|
|
if (state->is_v5e)
|
|
{
|
|
if (BIT (4) == 0 && BIT (7) == 1)
|
|
{
|
|
/* ElSegundo SMLALxy insn. */
|
|
unsigned long long op1 = state->Reg[BITS (0, 3)];
|
|
unsigned long long op2 = state->Reg[BITS (8, 11)];
|
|
unsigned long long dest;
|
|
unsigned long long result;
|
|
|
|
if (BIT (5))
|
|
op1 >>= 16;
|
|
if (BIT (6))
|
|
op2 >>= 16;
|
|
op1 &= 0xFFFF;
|
|
if (op1 & 0x8000)
|
|
op1 -= 65536;
|
|
op2 &= 0xFFFF;
|
|
if (op2 & 0x8000)
|
|
op2 -= 65536;
|
|
|
|
dest = (unsigned long long) state->Reg[BITS (16, 19)] << 32;
|
|
dest |= state->Reg[BITS (12, 15)];
|
|
dest += op1 * op2;
|
|
state->Reg[BITS (12, 15)] = dest;
|
|
state->Reg[BITS (16, 19)] = dest >> 32;
|
|
break;
|
|
}
|
|
|
|
if (BITS (4, 11) == 5)
|
|
{
|
|
/* ElSegundo QDADD insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (16, 19)];
|
|
ARMword op2d = op2 + op2;
|
|
ARMword result;
|
|
|
|
if (AddOverflow (op2, op2, op2d))
|
|
{
|
|
SETS;
|
|
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
|
|
}
|
|
|
|
result = op1 + op2d;
|
|
if (AddOverflow (op1, op2d, result))
|
|
{
|
|
SETS;
|
|
result = POS (result) ? 0x80000000 : 0x7fffffff;
|
|
}
|
|
|
|
state->Reg[BITS (12, 15)] = result;
|
|
break;
|
|
}
|
|
}
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, no write-back, down, pre indexed */
|
|
SHPREDOWN ();
|
|
break;
|
|
}
|
|
#endif
|
|
if (BITS (4, 11) == 9)
|
|
{ /* SWP */
|
|
UNDEF_SWPPC;
|
|
temp = LHS;
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (VECTORACCESS (temp) || ADDREXCEPT (temp))
|
|
{
|
|
INTERNALABORT (temp);
|
|
(void) ARMul_LoadByte (state, temp);
|
|
(void) ARMul_LoadByte (state, temp);
|
|
}
|
|
else
|
|
#endif
|
|
DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]);
|
|
if (state->abortSig || state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
}
|
|
}
|
|
else if ((BITS (0, 11) == 0) && (LHSReg == 15))
|
|
{ /* MRS SPSR */
|
|
UNDEF_MRSPC;
|
|
DEST = GETSPSR (state->Bank);
|
|
}
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x15: /* CMPP reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, no write-back, down, pre indexed */
|
|
LHPREDOWN ();
|
|
/* continue with remaining instruction decode */
|
|
}
|
|
#endif
|
|
if (DESTReg == 15)
|
|
{ /* CMPP reg */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
rhs = DPRegRHS;
|
|
temp = LHS - rhs;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
}
|
|
else
|
|
{ /* CMP reg */
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs - rhs;
|
|
ARMul_NegZero (state, dest);
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x16: /* CMN reg and MSR reg to SPSR */
|
|
if (state->is_v5e)
|
|
{
|
|
if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0)
|
|
{
|
|
/* ElSegundo SMULxy insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (8, 11)];
|
|
ARMword Rn = state->Reg[BITS (12, 15)];
|
|
|
|
if (BIT (5))
|
|
op1 >>= 16;
|
|
if (BIT (6))
|
|
op2 >>= 16;
|
|
op1 &= 0xFFFF;
|
|
op2 &= 0xFFFF;
|
|
if (op1 & 0x8000)
|
|
op1 -= 65536;
|
|
if (op2 & 0x8000)
|
|
op2 -= 65536;
|
|
|
|
state->Reg[BITS (16, 19)] = op1 * op2;
|
|
break;
|
|
}
|
|
|
|
if (BITS (4, 11) == 5)
|
|
{
|
|
/* ElSegundo QDSUB insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
ARMword op2 = state->Reg[BITS (16, 19)];
|
|
ARMword op2d = op2 + op2;
|
|
ARMword result;
|
|
|
|
if (AddOverflow (op2, op2, op2d))
|
|
{
|
|
SETS;
|
|
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
|
|
}
|
|
|
|
result = op1 - op2d;
|
|
if (SubOverflow (op1, op2d, result))
|
|
{
|
|
SETS;
|
|
result = POS (result) ? 0x80000000 : 0x7fffffff;
|
|
}
|
|
|
|
state->Reg[BITS (12, 15)] = result;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (state->is_v5)
|
|
{
|
|
if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF)
|
|
{
|
|
/* ARM5 CLZ insn. */
|
|
ARMword op1 = state->Reg[BITS (0, 3)];
|
|
int result = 32;
|
|
|
|
if (op1)
|
|
for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1)
|
|
result++;
|
|
|
|
state->Reg[BITS (12, 15)] = result;
|
|
break;
|
|
}
|
|
}
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, write-back, down, pre indexed */
|
|
SHPREDOWNWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
if (DESTReg == 15)
|
|
{ /* MSR */
|
|
UNDEF_MSRPC;
|
|
ARMul_FixSPSR (state, instr, DPRegRHS);
|
|
}
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x17: /* CMNP reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, write-back, down, pre indexed */
|
|
LHPREDOWNWB ();
|
|
/* continue with remaining instruction decoding */
|
|
}
|
|
#endif
|
|
if (DESTReg == 15)
|
|
{
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
rhs = DPRegRHS;
|
|
temp = LHS + rhs;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
break;
|
|
}
|
|
else
|
|
{ /* CMN reg */
|
|
lhs = LHS;
|
|
rhs = DPRegRHS;
|
|
dest = lhs + rhs;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x18: /* ORR reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, no write-back, up, pre indexed */
|
|
SHPREUP ();
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS | rhs;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x19: /* ORRS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, no write-back, up, pre indexed */
|
|
LHPREUP ();
|
|
/* continue with remaining instruction decoding */
|
|
}
|
|
#endif
|
|
rhs = DPSRegRHS;
|
|
dest = LHS | rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x1a: /* MOV reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 11) == 0xB)
|
|
{
|
|
/* STRH register offset, write-back, up, pre indexed */
|
|
SHPREUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
dest = DPRegRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x1b: /* MOVS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 11) & 0xF9) == 0x9)
|
|
{
|
|
/* LDR register offset, write-back, up, pre indexed */
|
|
LHPREUPWB ();
|
|
/* continue with remaining instruction decoding */
|
|
}
|
|
#endif
|
|
dest = DPSRegRHS;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x1c: /* BIC reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, no write-back, up, pre indexed */
|
|
SHPREUP ();
|
|
break;
|
|
}
|
|
#endif
|
|
rhs = DPRegRHS;
|
|
dest = LHS & ~rhs;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x1d: /* BICS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, no write-back, up, pre indexed */
|
|
LHPREUP ();
|
|
/* continue with instruction decoding */
|
|
}
|
|
#endif
|
|
rhs = DPSRegRHS;
|
|
dest = LHS & ~rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x1e: /* MVN reg */
|
|
#ifdef MODET
|
|
if (BITS (4, 7) == 0xB)
|
|
{
|
|
/* STRH immediate offset, write-back, up, pre indexed */
|
|
SHPREUPWB ();
|
|
break;
|
|
}
|
|
#endif
|
|
dest = ~DPRegRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x1f: /* MVNS reg */
|
|
#ifdef MODET
|
|
if ((BITS (4, 7) & 0x9) == 0x9)
|
|
{
|
|
/* LDR immediate offset, write-back, up, pre indexed */
|
|
LHPREUPWB ();
|
|
/* continue instruction decoding */
|
|
}
|
|
#endif
|
|
dest = ~DPSRegRHS;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Data Processing Immediate RHS Instructions *
|
|
\***************************************************************************/
|
|
|
|
case 0x20: /* AND immed */
|
|
dest = LHS & DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x21: /* ANDS immed */
|
|
DPSImmRHS;
|
|
dest = LHS & rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x22: /* EOR immed */
|
|
dest = LHS ^ DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x23: /* EORS immed */
|
|
DPSImmRHS;
|
|
dest = LHS ^ rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x24: /* SUB immed */
|
|
dest = LHS - DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x25: /* SUBS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = lhs - rhs;
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x26: /* RSB immed */
|
|
dest = DPImmRHS - LHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x27: /* RSBS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = rhs - lhs;
|
|
if ((rhs >= lhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, rhs, lhs, dest);
|
|
ARMul_SubOverflow (state, rhs, lhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x28: /* ADD immed */
|
|
dest = LHS + DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x29: /* ADDS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = lhs + rhs;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x2a: /* ADC immed */
|
|
dest = LHS + DPImmRHS + CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x2b: /* ADCS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = lhs + rhs + CFLAG;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x2c: /* SBC immed */
|
|
dest = LHS - DPImmRHS - !CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x2d: /* SBCS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = lhs - rhs - !CFLAG;
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x2e: /* RSC immed */
|
|
dest = DPImmRHS - LHS - !CFLAG;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x2f: /* RSCS immed */
|
|
lhs = LHS;
|
|
rhs = DPImmRHS;
|
|
dest = rhs - lhs - !CFLAG;
|
|
if ((rhs >= lhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, rhs, lhs, dest);
|
|
ARMul_SubOverflow (state, rhs, lhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x30: /* TST immed */
|
|
UNDEF_Test;
|
|
break;
|
|
|
|
case 0x31: /* TSTP immed */
|
|
if (DESTReg == 15)
|
|
{ /* TSTP immed */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
temp = LHS & DPImmRHS;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
DPSImmRHS; /* TST immed */
|
|
dest = LHS & rhs;
|
|
ARMul_NegZero (state, dest);
|
|
}
|
|
break;
|
|
|
|
case 0x32: /* TEQ immed and MSR immed to CPSR */
|
|
if (DESTReg == 15)
|
|
{ /* MSR immed to CPSR */
|
|
ARMul_FixCPSR (state, instr, DPImmRHS);
|
|
}
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x33: /* TEQP immed */
|
|
if (DESTReg == 15)
|
|
{ /* TEQP immed */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
temp = LHS ^ DPImmRHS;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
DPSImmRHS; /* TEQ immed */
|
|
dest = LHS ^ rhs;
|
|
ARMul_NegZero (state, dest);
|
|
}
|
|
break;
|
|
|
|
case 0x34: /* CMP immed */
|
|
UNDEF_Test;
|
|
break;
|
|
|
|
case 0x35: /* CMPP immed */
|
|
if (DESTReg == 15)
|
|
{ /* CMPP immed */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
temp = LHS - DPImmRHS;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
lhs = LHS; /* CMP immed */
|
|
rhs = DPImmRHS;
|
|
dest = lhs - rhs;
|
|
ARMul_NegZero (state, dest);
|
|
if ((lhs >= rhs) || ((rhs | lhs) >> 31))
|
|
{
|
|
ARMul_SubCarry (state, lhs, rhs, dest);
|
|
ARMul_SubOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x36: /* CMN immed and MSR immed to SPSR */
|
|
if (DESTReg == 15) /* MSR */
|
|
ARMul_FixSPSR (state, instr, DPImmRHS);
|
|
else
|
|
{
|
|
UNDEF_Test;
|
|
}
|
|
break;
|
|
|
|
case 0x37: /* CMNP immed */
|
|
if (DESTReg == 15)
|
|
{ /* CMNP immed */
|
|
#ifdef MODE32
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
#else
|
|
temp = LHS + DPImmRHS;
|
|
SETR15PSR (temp);
|
|
#endif
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
lhs = LHS; /* CMN immed */
|
|
rhs = DPImmRHS;
|
|
dest = lhs + rhs;
|
|
ASSIGNZ (dest == 0);
|
|
if ((lhs | rhs) >> 30)
|
|
{ /* possible C,V,N to set */
|
|
ASSIGNN (NEG (dest));
|
|
ARMul_AddCarry (state, lhs, rhs, dest);
|
|
ARMul_AddOverflow (state, lhs, rhs, dest);
|
|
}
|
|
else
|
|
{
|
|
CLEARN;
|
|
CLEARC;
|
|
CLEARV;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x38: /* ORR immed */
|
|
dest = LHS | DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x39: /* ORRS immed */
|
|
DPSImmRHS;
|
|
dest = LHS | rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x3a: /* MOV immed */
|
|
dest = DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x3b: /* MOVS immed */
|
|
DPSImmRHS;
|
|
WRITESDEST (rhs);
|
|
break;
|
|
|
|
case 0x3c: /* BIC immed */
|
|
dest = LHS & ~DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x3d: /* BICS immed */
|
|
DPSImmRHS;
|
|
dest = LHS & ~rhs;
|
|
WRITESDEST (dest);
|
|
break;
|
|
|
|
case 0x3e: /* MVN immed */
|
|
dest = ~DPImmRHS;
|
|
WRITEDEST (dest);
|
|
break;
|
|
|
|
case 0x3f: /* MVNS immed */
|
|
DPSImmRHS;
|
|
WRITESDEST (~rhs);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Single Data Transfer Immediate RHS Instructions *
|
|
\***************************************************************************/
|
|
|
|
case 0x40: /* Store Word, No WriteBack, Post Dec, Immed */
|
|
lhs = LHS;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs - LSImmRHS;
|
|
break;
|
|
|
|
case 0x41: /* Load Word, No WriteBack, Post Dec, Immed */
|
|
lhs = LHS;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = lhs - LSImmRHS;
|
|
break;
|
|
|
|
case 0x42: /* Store Word, WriteBack, Post Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
temp = lhs - LSImmRHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = temp;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x43: /* Load Word, WriteBack, Post Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = lhs - LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed */
|
|
lhs = LHS;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs - LSImmRHS;
|
|
break;
|
|
|
|
case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed */
|
|
lhs = LHS;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = lhs - LSImmRHS;
|
|
break;
|
|
|
|
case 0x46: /* Store Byte, WriteBack, Post Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs - LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x47: /* Load Byte, WriteBack, Post Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = lhs - LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x48: /* Store Word, No WriteBack, Post Inc, Immed */
|
|
lhs = LHS;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
break;
|
|
|
|
case 0x49: /* Load Word, No WriteBack, Post Inc, Immed */
|
|
lhs = LHS;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
break;
|
|
|
|
case 0x4a: /* Store Word, WriteBack, Post Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x4b: /* Load Word, WriteBack, Post Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed */
|
|
lhs = LHS;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
break;
|
|
|
|
case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed */
|
|
lhs = LHS;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = lhs + LSImmRHS;
|
|
break;
|
|
|
|
case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs + LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = lhs + LSImmRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
|
|
case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed */
|
|
(void) StoreWord (state, instr, LHS - LSImmRHS);
|
|
break;
|
|
|
|
case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed */
|
|
(void) LoadWord (state, instr, LHS - LSImmRHS);
|
|
break;
|
|
|
|
case 0x52: /* Store Word, WriteBack, Pre Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS - LSImmRHS;
|
|
if (StoreWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x53: /* Load Word, WriteBack, Pre Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS - LSImmRHS;
|
|
if (LoadWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed */
|
|
(void) StoreByte (state, instr, LHS - LSImmRHS);
|
|
break;
|
|
|
|
case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed */
|
|
(void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
|
|
break;
|
|
|
|
case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS - LSImmRHS;
|
|
if (StoreByte (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS - LSImmRHS;
|
|
if (LoadByte (state, instr, temp, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed */
|
|
(void) StoreWord (state, instr, LHS + LSImmRHS);
|
|
break;
|
|
|
|
case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed */
|
|
(void) LoadWord (state, instr, LHS + LSImmRHS);
|
|
break;
|
|
|
|
case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS + LSImmRHS;
|
|
if (StoreWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS + LSImmRHS;
|
|
if (LoadWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed */
|
|
(void) StoreByte (state, instr, LHS + LSImmRHS);
|
|
break;
|
|
|
|
case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed */
|
|
(void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
|
|
break;
|
|
|
|
case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS + LSImmRHS;
|
|
if (StoreByte (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed */
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
temp = LHS + LSImmRHS;
|
|
if (LoadByte (state, instr, temp, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Single Data Transfer Register RHS Instructions *
|
|
\***************************************************************************/
|
|
|
|
case 0x60: /* Store Word, No WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs - LSRegRHS;
|
|
break;
|
|
|
|
case 0x61: /* Load Word, No WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs - LSRegRHS;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs - LSRegRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x63: /* Load Word, WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs - LSRegRHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = temp;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs - LSRegRHS;
|
|
break;
|
|
|
|
case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs - LSRegRHS;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs - LSRegRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x67: /* Load Byte, WriteBack, Post Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs - LSRegRHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = temp;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x68: /* Store Word, No WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs + LSRegRHS;
|
|
break;
|
|
|
|
case 0x69: /* Load Word, No WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs + LSRegRHS;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreWord (state, instr, lhs))
|
|
LSBase = lhs + LSRegRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x6b: /* Load Word, WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs + LSRegRHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadWord (state, instr, lhs))
|
|
LSBase = temp;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs + LSRegRHS;
|
|
break;
|
|
|
|
case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs + LSRegRHS;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
state->NtransSig = LOW;
|
|
if (StoreByte (state, instr, lhs))
|
|
LSBase = lhs + LSRegRHS;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
lhs = LHS;
|
|
temp = lhs + LSRegRHS;
|
|
state->NtransSig = LOW;
|
|
if (LoadByte (state, instr, lhs, LUNSIGNED))
|
|
LSBase = temp;
|
|
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
|
break;
|
|
|
|
|
|
case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) StoreWord (state, instr, LHS - LSRegRHS);
|
|
break;
|
|
|
|
case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) LoadWord (state, instr, LHS - LSRegRHS);
|
|
break;
|
|
|
|
case 0x72: /* Store Word, WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS - LSRegRHS;
|
|
if (StoreWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x73: /* Load Word, WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS - LSRegRHS;
|
|
if (LoadWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) StoreByte (state, instr, LHS - LSRegRHS);
|
|
break;
|
|
|
|
case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
|
|
break;
|
|
|
|
case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS - LSRegRHS;
|
|
if (StoreByte (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS - LSRegRHS;
|
|
if (LoadByte (state, instr, temp, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) StoreWord (state, instr, LHS + LSRegRHS);
|
|
break;
|
|
|
|
case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) LoadWord (state, instr, LHS + LSRegRHS);
|
|
break;
|
|
|
|
case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS + LSRegRHS;
|
|
if (StoreWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS + LSRegRHS;
|
|
if (LoadWord (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) StoreByte (state, instr, LHS + LSRegRHS);
|
|
break;
|
|
|
|
case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
(void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
|
|
break;
|
|
|
|
case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS + LSRegRHS;
|
|
if (StoreByte (state, instr, temp))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg */
|
|
if (BIT (4))
|
|
{
|
|
/* Check for the special breakpoint opcode.
|
|
This value should correspond to the value defined
|
|
as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */
|
|
if (BITS (0, 19) == 0xfdefe)
|
|
{
|
|
if (!ARMul_OSHandleSWI (state, SWI_Breakpoint))
|
|
ARMul_Abort (state, ARMul_SWIV);
|
|
}
|
|
else
|
|
ARMul_UndefInstr (state, instr);
|
|
break;
|
|
}
|
|
UNDEF_LSRBaseEQOffWb;
|
|
UNDEF_LSRBaseEQDestWb;
|
|
UNDEF_LSRPCBaseWb;
|
|
UNDEF_LSRPCOffWb;
|
|
temp = LHS + LSRegRHS;
|
|
if (LoadByte (state, instr, temp, LUNSIGNED))
|
|
LSBase = temp;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Multiple Data Transfer Instructions *
|
|
\***************************************************************************/
|
|
|
|
case 0x80: /* Store, No WriteBack, Post Dec */
|
|
STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
|
|
break;
|
|
|
|
case 0x81: /* Load, No WriteBack, Post Dec */
|
|
LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
|
|
break;
|
|
|
|
case 0x82: /* Store, WriteBack, Post Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
STOREMULT (instr, temp + 4L, temp);
|
|
break;
|
|
|
|
case 0x83: /* Load, WriteBack, Post Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
LOADMULT (instr, temp + 4L, temp);
|
|
break;
|
|
|
|
case 0x84: /* Store, Flags, No WriteBack, Post Dec */
|
|
STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
|
|
break;
|
|
|
|
case 0x85: /* Load, Flags, No WriteBack, Post Dec */
|
|
LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
|
|
break;
|
|
|
|
case 0x86: /* Store, Flags, WriteBack, Post Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
STORESMULT (instr, temp + 4L, temp);
|
|
break;
|
|
|
|
case 0x87: /* Load, Flags, WriteBack, Post Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
LOADSMULT (instr, temp + 4L, temp);
|
|
break;
|
|
|
|
|
|
case 0x88: /* Store, No WriteBack, Post Inc */
|
|
STOREMULT (instr, LSBase, 0L);
|
|
break;
|
|
|
|
case 0x89: /* Load, No WriteBack, Post Inc */
|
|
LOADMULT (instr, LSBase, 0L);
|
|
break;
|
|
|
|
case 0x8a: /* Store, WriteBack, Post Inc */
|
|
temp = LSBase;
|
|
STOREMULT (instr, temp, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x8b: /* Load, WriteBack, Post Inc */
|
|
temp = LSBase;
|
|
LOADMULT (instr, temp, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x8c: /* Store, Flags, No WriteBack, Post Inc */
|
|
STORESMULT (instr, LSBase, 0L);
|
|
break;
|
|
|
|
case 0x8d: /* Load, Flags, No WriteBack, Post Inc */
|
|
LOADSMULT (instr, LSBase, 0L);
|
|
break;
|
|
|
|
case 0x8e: /* Store, Flags, WriteBack, Post Inc */
|
|
temp = LSBase;
|
|
STORESMULT (instr, temp, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x8f: /* Load, Flags, WriteBack, Post Inc */
|
|
temp = LSBase;
|
|
LOADSMULT (instr, temp, temp + LSMNumRegs);
|
|
break;
|
|
|
|
|
|
case 0x90: /* Store, No WriteBack, Pre Dec */
|
|
STOREMULT (instr, LSBase - LSMNumRegs, 0L);
|
|
break;
|
|
|
|
case 0x91: /* Load, No WriteBack, Pre Dec */
|
|
LOADMULT (instr, LSBase - LSMNumRegs, 0L);
|
|
break;
|
|
|
|
case 0x92: /* Store, WriteBack, Pre Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
STOREMULT (instr, temp, temp);
|
|
break;
|
|
|
|
case 0x93: /* Load, WriteBack, Pre Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
LOADMULT (instr, temp, temp);
|
|
break;
|
|
|
|
case 0x94: /* Store, Flags, No WriteBack, Pre Dec */
|
|
STORESMULT (instr, LSBase - LSMNumRegs, 0L);
|
|
break;
|
|
|
|
case 0x95: /* Load, Flags, No WriteBack, Pre Dec */
|
|
LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
|
|
break;
|
|
|
|
case 0x96: /* Store, Flags, WriteBack, Pre Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
STORESMULT (instr, temp, temp);
|
|
break;
|
|
|
|
case 0x97: /* Load, Flags, WriteBack, Pre Dec */
|
|
temp = LSBase - LSMNumRegs;
|
|
LOADSMULT (instr, temp, temp);
|
|
break;
|
|
|
|
|
|
case 0x98: /* Store, No WriteBack, Pre Inc */
|
|
STOREMULT (instr, LSBase + 4L, 0L);
|
|
break;
|
|
|
|
case 0x99: /* Load, No WriteBack, Pre Inc */
|
|
LOADMULT (instr, LSBase + 4L, 0L);
|
|
break;
|
|
|
|
case 0x9a: /* Store, WriteBack, Pre Inc */
|
|
temp = LSBase;
|
|
STOREMULT (instr, temp + 4L, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x9b: /* Load, WriteBack, Pre Inc */
|
|
temp = LSBase;
|
|
LOADMULT (instr, temp + 4L, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x9c: /* Store, Flags, No WriteBack, Pre Inc */
|
|
STORESMULT (instr, LSBase + 4L, 0L);
|
|
break;
|
|
|
|
case 0x9d: /* Load, Flags, No WriteBack, Pre Inc */
|
|
LOADSMULT (instr, LSBase + 4L, 0L);
|
|
break;
|
|
|
|
case 0x9e: /* Store, Flags, WriteBack, Pre Inc */
|
|
temp = LSBase;
|
|
STORESMULT (instr, temp + 4L, temp + LSMNumRegs);
|
|
break;
|
|
|
|
case 0x9f: /* Load, Flags, WriteBack, Pre Inc */
|
|
temp = LSBase;
|
|
LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Branch forward *
|
|
\***************************************************************************/
|
|
|
|
case 0xa0:
|
|
case 0xa1:
|
|
case 0xa2:
|
|
case 0xa3:
|
|
case 0xa4:
|
|
case 0xa5:
|
|
case 0xa6:
|
|
case 0xa7:
|
|
state->Reg[15] = pc + 8 + POSBRANCH;
|
|
FLUSHPIPE;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Branch backward *
|
|
\***************************************************************************/
|
|
|
|
case 0xa8:
|
|
case 0xa9:
|
|
case 0xaa:
|
|
case 0xab:
|
|
case 0xac:
|
|
case 0xad:
|
|
case 0xae:
|
|
case 0xaf:
|
|
state->Reg[15] = pc + 8 + NEGBRANCH;
|
|
FLUSHPIPE;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Branch and Link forward *
|
|
\***************************************************************************/
|
|
|
|
case 0xb0:
|
|
case 0xb1:
|
|
case 0xb2:
|
|
case 0xb3:
|
|
case 0xb4:
|
|
case 0xb5:
|
|
case 0xb6:
|
|
case 0xb7:
|
|
#ifdef MODE32
|
|
state->Reg[14] = pc + 4; /* put PC into Link */
|
|
#else
|
|
state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; /* put PC into Link */
|
|
#endif
|
|
state->Reg[15] = pc + 8 + POSBRANCH;
|
|
FLUSHPIPE;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Branch and Link backward *
|
|
\***************************************************************************/
|
|
|
|
case 0xb8:
|
|
case 0xb9:
|
|
case 0xba:
|
|
case 0xbb:
|
|
case 0xbc:
|
|
case 0xbd:
|
|
case 0xbe:
|
|
case 0xbf:
|
|
#ifdef MODE32
|
|
state->Reg[14] = pc + 4; /* put PC into Link */
|
|
#else
|
|
state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; /* put PC into Link */
|
|
#endif
|
|
state->Reg[15] = pc + 8 + NEGBRANCH;
|
|
FLUSHPIPE;
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Co-Processor Data Transfers *
|
|
\***************************************************************************/
|
|
|
|
case 0xc4:
|
|
if (state->is_XScale)
|
|
{
|
|
if (BITS (4, 7) != 0x00)
|
|
ARMul_UndefInstr (state, instr);
|
|
|
|
if (BITS (8, 11) != 0x00)
|
|
ARMul_UndefInstr (state, instr); /* Not CP0. */
|
|
|
|
/* XScale MAR insn. Move two registers into accumulator. */
|
|
if (BITS (0, 3) == 0x00)
|
|
{
|
|
state->Accumulator = state->Reg[BITS (12, 15)];
|
|
state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32;
|
|
break;
|
|
}
|
|
/* Access to any other acc is unpredicatable. */
|
|
break;
|
|
}
|
|
/* Drop through. */
|
|
|
|
case 0xc0: /* Store , No WriteBack , Post Dec */
|
|
ARMul_STC (state, instr, LHS);
|
|
break;
|
|
|
|
case 0xc5:
|
|
if (state->is_XScale)
|
|
{
|
|
if (BITS (4, 7) != 0x00)
|
|
ARMul_UndefInstr (state, instr);
|
|
|
|
if (BITS (8, 11) != 0x00)
|
|
ARMul_UndefInstr (state, instr); /* Not CP0. */
|
|
|
|
/* XScale MRA insn. Move accumulator into two registers. */
|
|
if (BITS (0, 3) == 0x00)
|
|
{
|
|
ARMword t1 = (state->Accumulator >> 32) & 255;
|
|
|
|
if (t1 & 128)
|
|
t1 -= 256;
|
|
|
|
state->Reg[BITS (12, 15)] = state->Accumulator;
|
|
state->Reg[BITS (16, 19)] = t1;
|
|
break;
|
|
}
|
|
/* Access to any other acc is unpredicatable. */
|
|
break;
|
|
}
|
|
/* Drop through. */
|
|
|
|
case 0xc1: /* Load , No WriteBack , Post Dec */
|
|
ARMul_LDC (state, instr, LHS);
|
|
break;
|
|
|
|
case 0xc2:
|
|
case 0xc6: /* Store , WriteBack , Post Dec */
|
|
lhs = LHS;
|
|
state->Base = lhs - LSCOff;
|
|
ARMul_STC (state, instr, lhs);
|
|
break;
|
|
|
|
case 0xc3:
|
|
case 0xc7: /* Load , WriteBack , Post Dec */
|
|
lhs = LHS;
|
|
state->Base = lhs - LSCOff;
|
|
ARMul_LDC (state, instr, lhs);
|
|
break;
|
|
|
|
case 0xc8:
|
|
case 0xcc: /* Store , No WriteBack , Post Inc */
|
|
ARMul_STC (state, instr, LHS);
|
|
break;
|
|
|
|
case 0xc9:
|
|
case 0xcd: /* Load , No WriteBack , Post Inc */
|
|
ARMul_LDC (state, instr, LHS);
|
|
break;
|
|
|
|
case 0xca:
|
|
case 0xce: /* Store , WriteBack , Post Inc */
|
|
lhs = LHS;
|
|
state->Base = lhs + LSCOff;
|
|
ARMul_STC (state, instr, LHS);
|
|
break;
|
|
|
|
case 0xcb:
|
|
case 0xcf: /* Load , WriteBack , Post Inc */
|
|
lhs = LHS;
|
|
state->Base = lhs + LSCOff;
|
|
ARMul_LDC (state, instr, LHS);
|
|
break;
|
|
|
|
|
|
case 0xd0:
|
|
case 0xd4: /* Store , No WriteBack , Pre Dec */
|
|
ARMul_STC (state, instr, LHS - LSCOff);
|
|
break;
|
|
|
|
case 0xd1:
|
|
case 0xd5: /* Load , No WriteBack , Pre Dec */
|
|
ARMul_LDC (state, instr, LHS - LSCOff);
|
|
break;
|
|
|
|
case 0xd2:
|
|
case 0xd6: /* Store , WriteBack , Pre Dec */
|
|
lhs = LHS - LSCOff;
|
|
state->Base = lhs;
|
|
ARMul_STC (state, instr, lhs);
|
|
break;
|
|
|
|
case 0xd3:
|
|
case 0xd7: /* Load , WriteBack , Pre Dec */
|
|
lhs = LHS - LSCOff;
|
|
state->Base = lhs;
|
|
ARMul_LDC (state, instr, lhs);
|
|
break;
|
|
|
|
case 0xd8:
|
|
case 0xdc: /* Store , No WriteBack , Pre Inc */
|
|
ARMul_STC (state, instr, LHS + LSCOff);
|
|
break;
|
|
|
|
case 0xd9:
|
|
case 0xdd: /* Load , No WriteBack , Pre Inc */
|
|
ARMul_LDC (state, instr, LHS + LSCOff);
|
|
break;
|
|
|
|
case 0xda:
|
|
case 0xde: /* Store , WriteBack , Pre Inc */
|
|
lhs = LHS + LSCOff;
|
|
state->Base = lhs;
|
|
ARMul_STC (state, instr, lhs);
|
|
break;
|
|
|
|
case 0xdb:
|
|
case 0xdf: /* Load , WriteBack , Pre Inc */
|
|
lhs = LHS + LSCOff;
|
|
state->Base = lhs;
|
|
ARMul_LDC (state, instr, lhs);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Co-Processor Register Transfers (MCR) and Data Ops *
|
|
\***************************************************************************/
|
|
|
|
case 0xe2:
|
|
if (state->is_XScale)
|
|
switch (BITS (18, 19))
|
|
{
|
|
case 0x0:
|
|
{
|
|
/* XScale MIA instruction. Signed multiplication of two 32 bit
|
|
values and addition to 40 bit accumulator. */
|
|
long long Rm = state->Reg[MULLHSReg];
|
|
long long Rs = state->Reg[MULACCReg];
|
|
|
|
if (Rm & (1 << 31))
|
|
Rm -= 1ULL << 32;
|
|
if (Rs & (1 << 31))
|
|
Rs -= 1ULL << 32;
|
|
state->Accumulator += Rm * Rs;
|
|
}
|
|
goto donext;
|
|
|
|
case 0x2:
|
|
{
|
|
/* XScale MIAPH instruction. */
|
|
ARMword t1 = state->Reg[MULLHSReg] >> 16;
|
|
ARMword t2 = state->Reg[MULACCReg] >> 16;
|
|
ARMword t3 = state->Reg[MULLHSReg] & 0xffff;
|
|
ARMword t4 = state->Reg[MULACCReg] & 0xffff;
|
|
long long t5;
|
|
|
|
if (t1 & (1 << 15))
|
|
t1 -= 1 << 16;
|
|
if (t2 & (1 << 15))
|
|
t2 -= 1 << 16;
|
|
if (t3 & (1 << 15))
|
|
t3 -= 1 << 16;
|
|
if (t4 & (1 << 15))
|
|
t4 -= 1 << 16;
|
|
t1 *= t2;
|
|
t5 = t1;
|
|
if (t5 & (1 << 31))
|
|
t5 -= 1ULL << 32;
|
|
state->Accumulator += t5;
|
|
t3 *= t4;
|
|
t5 = t3;
|
|
if (t5 & (1 << 31))
|
|
t5 -= 1ULL << 32;
|
|
state->Accumulator += t5;
|
|
}
|
|
goto donext;
|
|
|
|
case 0x3:
|
|
{
|
|
/* XScale MIAxy instruction. */
|
|
ARMword t1;
|
|
ARMword t2;
|
|
long long t5;
|
|
|
|
if (BIT (17))
|
|
t1 = state->Reg[MULLHSReg] >> 16;
|
|
else
|
|
t1 = state->Reg[MULLHSReg] & 0xffff;
|
|
|
|
if (BIT (16))
|
|
t2 = state->Reg[MULACCReg] >> 16;
|
|
else
|
|
t2 = state->Reg[MULACCReg] & 0xffff;
|
|
|
|
if (t1 & (1 << 15))
|
|
t1 -= 1 << 16;
|
|
if (t2 & (1 << 15))
|
|
t2 -= 1 << 16;
|
|
t1 *= t2;
|
|
t5 = t1;
|
|
if (t5 & (1 << 31))
|
|
t5 -= 1ULL << 32;
|
|
state->Accumulator += t5;
|
|
}
|
|
goto donext;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
/* Drop through. */
|
|
|
|
case 0xe0:
|
|
case 0xe4:
|
|
case 0xe6:
|
|
case 0xe8:
|
|
case 0xea:
|
|
case 0xec:
|
|
case 0xee:
|
|
if (BIT (4))
|
|
{ /* MCR */
|
|
if (DESTReg == 15)
|
|
{
|
|
UNDEF_MCRPC;
|
|
#ifdef MODE32
|
|
ARMul_MCR (state, instr, state->Reg[15] + isize);
|
|
#else
|
|
ARMul_MCR (state, instr, ECC | ER15INT | EMODE |
|
|
((state->Reg[15] + isize) & R15PCBITS));
|
|
#endif
|
|
}
|
|
else
|
|
ARMul_MCR (state, instr, DEST);
|
|
}
|
|
else /* CDP Part 1 */
|
|
ARMul_CDP (state, instr);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* Co-Processor Register Transfers (MRC) and Data Ops *
|
|
\***************************************************************************/
|
|
|
|
case 0xe1:
|
|
case 0xe3:
|
|
case 0xe5:
|
|
case 0xe7:
|
|
case 0xe9:
|
|
case 0xeb:
|
|
case 0xed:
|
|
case 0xef:
|
|
if (BIT (4))
|
|
{ /* MRC */
|
|
temp = ARMul_MRC (state, instr);
|
|
if (DESTReg == 15)
|
|
{
|
|
ASSIGNN ((temp & NBIT) != 0);
|
|
ASSIGNZ ((temp & ZBIT) != 0);
|
|
ASSIGNC ((temp & CBIT) != 0);
|
|
ASSIGNV ((temp & VBIT) != 0);
|
|
}
|
|
else
|
|
DEST = temp;
|
|
}
|
|
else /* CDP Part 2 */
|
|
ARMul_CDP (state, instr);
|
|
break;
|
|
|
|
/***************************************************************************\
|
|
* SWI instruction *
|
|
\***************************************************************************/
|
|
|
|
case 0xf0:
|
|
case 0xf1:
|
|
case 0xf2:
|
|
case 0xf3:
|
|
case 0xf4:
|
|
case 0xf5:
|
|
case 0xf6:
|
|
case 0xf7:
|
|
case 0xf8:
|
|
case 0xf9:
|
|
case 0xfa:
|
|
case 0xfb:
|
|
case 0xfc:
|
|
case 0xfd:
|
|
case 0xfe:
|
|
case 0xff:
|
|
if (instr == ARMul_ABORTWORD && state->AbortAddr == pc)
|
|
{ /* a prefetch abort */
|
|
ARMul_Abort (state, ARMul_PrefetchAbortV);
|
|
break;
|
|
}
|
|
|
|
if (!ARMul_OSHandleSWI (state, BITS (0, 23)))
|
|
{
|
|
ARMul_Abort (state, ARMul_SWIV);
|
|
}
|
|
break;
|
|
} /* 256 way main switch */
|
|
} /* if temp */
|
|
|
|
#ifdef MODET
|
|
donext:
|
|
#endif
|
|
|
|
#ifdef NEED_UI_LOOP_HOOK
|
|
if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
|
|
{
|
|
ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
|
|
ui_loop_hook (0);
|
|
}
|
|
#endif /* NEED_UI_LOOP_HOOK */
|
|
|
|
if (state->Emulate == ONCE)
|
|
state->Emulate = STOP;
|
|
/* If we have changed mode, allow the PC to advance before stopping. */
|
|
else if (state->Emulate == CHANGEMODE)
|
|
continue;
|
|
else if (state->Emulate != RUN)
|
|
break;
|
|
}
|
|
while (!stop_simulator); /* do loop */
|
|
|
|
state->decoded = decoded;
|
|
state->loaded = loaded;
|
|
state->pc = pc;
|
|
|
|
return pc;
|
|
} /* Emulate 26/32 in instruction based mode */
|
|
|
|
|
|
/***************************************************************************\
|
|
* This routine evaluates most Data Processing register RHS's with the S *
|
|
* bit clear. It is intended to be called from the macro DPRegRHS, which *
|
|
* filters the common case of an unshifted register with in line code *
|
|
\***************************************************************************/
|
|
|
|
static ARMword
|
|
GetDPRegRHS (ARMul_State * state, ARMword instr)
|
|
{
|
|
ARMword shamt, base;
|
|
|
|
base = RHSReg;
|
|
if (BIT (4))
|
|
{ /* shift amount in a register */
|
|
UNDEF_Shift;
|
|
INCPC;
|
|
#ifndef MODE32
|
|
if (base == 15)
|
|
base = ECC | ER15INT | R15PC | EMODE;
|
|
else
|
|
#endif
|
|
base = state->Reg[base];
|
|
ARMul_Icycles (state, 1, 0L);
|
|
shamt = state->Reg[BITS (8, 11)] & 0xff;
|
|
switch ((int) BITS (5, 6))
|
|
{
|
|
case LSL:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt >= 32)
|
|
return (0);
|
|
else
|
|
return (base << shamt);
|
|
case LSR:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt >= 32)
|
|
return (0);
|
|
else
|
|
return (base >> shamt);
|
|
case ASR:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt >= 32)
|
|
return ((ARMword) ((long int) base >> 31L));
|
|
else
|
|
return ((ARMword) ((long int) base >> (int) shamt));
|
|
case ROR:
|
|
shamt &= 0x1f;
|
|
if (shamt == 0)
|
|
return (base);
|
|
else
|
|
return ((base << (32 - shamt)) | (base >> shamt));
|
|
}
|
|
}
|
|
else
|
|
{ /* shift amount is a constant */
|
|
#ifndef MODE32
|
|
if (base == 15)
|
|
base = ECC | ER15INT | R15PC | EMODE;
|
|
else
|
|
#endif
|
|
base = state->Reg[base];
|
|
shamt = BITS (7, 11);
|
|
switch ((int) BITS (5, 6))
|
|
{
|
|
case LSL:
|
|
return (base << shamt);
|
|
case LSR:
|
|
if (shamt == 0)
|
|
return (0);
|
|
else
|
|
return (base >> shamt);
|
|
case ASR:
|
|
if (shamt == 0)
|
|
return ((ARMword) ((long int) base >> 31L));
|
|
else
|
|
return ((ARMword) ((long int) base >> (int) shamt));
|
|
case ROR:
|
|
if (shamt == 0) /* its an RRX */
|
|
return ((base >> 1) | (CFLAG << 31));
|
|
else
|
|
return ((base << (32 - shamt)) | (base >> shamt));
|
|
}
|
|
}
|
|
return (0); /* just to shut up lint */
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine evaluates most Logical Data Processing register RHS's *
|
|
* with the S bit set. It is intended to be called from the macro *
|
|
* DPSRegRHS, which filters the common case of an unshifted register *
|
|
* with in line code *
|
|
\***************************************************************************/
|
|
|
|
static ARMword
|
|
GetDPSRegRHS (ARMul_State * state, ARMword instr)
|
|
{
|
|
ARMword shamt, base;
|
|
|
|
base = RHSReg;
|
|
if (BIT (4))
|
|
{ /* shift amount in a register */
|
|
UNDEF_Shift;
|
|
INCPC;
|
|
#ifndef MODE32
|
|
if (base == 15)
|
|
base = ECC | ER15INT | R15PC | EMODE;
|
|
else
|
|
#endif
|
|
base = state->Reg[base];
|
|
ARMul_Icycles (state, 1, 0L);
|
|
shamt = state->Reg[BITS (8, 11)] & 0xff;
|
|
switch ((int) BITS (5, 6))
|
|
{
|
|
case LSL:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt == 32)
|
|
{
|
|
ASSIGNC (base & 1);
|
|
return (0);
|
|
}
|
|
else if (shamt > 32)
|
|
{
|
|
CLEARC;
|
|
return (0);
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((base >> (32 - shamt)) & 1);
|
|
return (base << shamt);
|
|
}
|
|
case LSR:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt == 32)
|
|
{
|
|
ASSIGNC (base >> 31);
|
|
return (0);
|
|
}
|
|
else if (shamt > 32)
|
|
{
|
|
CLEARC;
|
|
return (0);
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((base >> (shamt - 1)) & 1);
|
|
return (base >> shamt);
|
|
}
|
|
case ASR:
|
|
if (shamt == 0)
|
|
return (base);
|
|
else if (shamt >= 32)
|
|
{
|
|
ASSIGNC (base >> 31L);
|
|
return ((ARMword) ((long int) base >> 31L));
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
|
|
return ((ARMword) ((long int) base >> (int) shamt));
|
|
}
|
|
case ROR:
|
|
if (shamt == 0)
|
|
return (base);
|
|
shamt &= 0x1f;
|
|
if (shamt == 0)
|
|
{
|
|
ASSIGNC (base >> 31);
|
|
return (base);
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((base >> (shamt - 1)) & 1);
|
|
return ((base << (32 - shamt)) | (base >> shamt));
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{ /* shift amount is a constant */
|
|
#ifndef MODE32
|
|
if (base == 15)
|
|
base = ECC | ER15INT | R15PC | EMODE;
|
|
else
|
|
#endif
|
|
base = state->Reg[base];
|
|
shamt = BITS (7, 11);
|
|
switch ((int) BITS (5, 6))
|
|
{
|
|
case LSL:
|
|
ASSIGNC ((base >> (32 - shamt)) & 1);
|
|
return (base << shamt);
|
|
case LSR:
|
|
if (shamt == 0)
|
|
{
|
|
ASSIGNC (base >> 31);
|
|
return (0);
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((base >> (shamt - 1)) & 1);
|
|
return (base >> shamt);
|
|
}
|
|
case ASR:
|
|
if (shamt == 0)
|
|
{
|
|
ASSIGNC (base >> 31L);
|
|
return ((ARMword) ((long int) base >> 31L));
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
|
|
return ((ARMword) ((long int) base >> (int) shamt));
|
|
}
|
|
case ROR:
|
|
if (shamt == 0)
|
|
{ /* its an RRX */
|
|
shamt = CFLAG;
|
|
ASSIGNC (base & 1);
|
|
return ((base >> 1) | (shamt << 31));
|
|
}
|
|
else
|
|
{
|
|
ASSIGNC ((base >> (shamt - 1)) & 1);
|
|
return ((base << (32 - shamt)) | (base >> shamt));
|
|
}
|
|
}
|
|
}
|
|
return (0); /* just to shut up lint */
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine handles writes to register 15 when the S bit is not set. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
WriteR15 (ARMul_State * state, ARMword src)
|
|
{
|
|
/* The ARM documentation states that the two least significant bits
|
|
are discarded when setting PC, except in the cases handled by
|
|
WriteR15Branch() below. It's probably an oversight: in THUMB
|
|
mode, the second least significant bit should probably not be
|
|
discarded. */
|
|
#ifdef MODET
|
|
if (TFLAG)
|
|
src &= 0xfffffffe;
|
|
else
|
|
#endif
|
|
src &= 0xfffffffc;
|
|
#ifdef MODE32
|
|
state->Reg[15] = src & PCBITS;
|
|
#else
|
|
state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
|
|
ARMul_R15Altered (state);
|
|
#endif
|
|
FLUSHPIPE;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine handles writes to register 15 when the S bit is set. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
WriteSR15 (ARMul_State * state, ARMword src)
|
|
{
|
|
#ifdef MODE32
|
|
if (state->Bank > 0)
|
|
{
|
|
state->Cpsr = state->Spsr[state->Bank];
|
|
ARMul_CPSRAltered (state);
|
|
}
|
|
#ifdef MODET
|
|
if (TFLAG)
|
|
src &= 0xfffffffe;
|
|
else
|
|
#endif
|
|
src &= 0xfffffffc;
|
|
state->Reg[15] = src & PCBITS;
|
|
#else
|
|
#ifdef MODET
|
|
if (TFLAG)
|
|
abort (); /* ARMul_R15Altered would have to support it. */
|
|
else
|
|
#endif
|
|
src &= 0xfffffffc;
|
|
if (state->Bank == USERBANK)
|
|
state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
|
|
else
|
|
state->Reg[15] = src;
|
|
ARMul_R15Altered (state);
|
|
#endif
|
|
FLUSHPIPE;
|
|
}
|
|
|
|
/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
|
|
will switch to Thumb mode if the least significant bit is set. */
|
|
|
|
static void
|
|
WriteR15Branch (ARMul_State * state, ARMword src)
|
|
{
|
|
#ifdef MODET
|
|
if (src & 1)
|
|
{ /* Thumb bit */
|
|
SETT;
|
|
state->Reg[15] = src & 0xfffffffe;
|
|
}
|
|
else
|
|
{
|
|
CLEART;
|
|
state->Reg[15] = src & 0xfffffffc;
|
|
}
|
|
FLUSHPIPE;
|
|
#else
|
|
WriteR15 (state, src);
|
|
#endif
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine evaluates most Load and Store register RHS's. It is *
|
|
* intended to be called from the macro LSRegRHS, which filters the *
|
|
* common case of an unshifted register with in line code *
|
|
\***************************************************************************/
|
|
|
|
static ARMword
|
|
GetLSRegRHS (ARMul_State * state, ARMword instr)
|
|
{
|
|
ARMword shamt, base;
|
|
|
|
base = RHSReg;
|
|
#ifndef MODE32
|
|
if (base == 15)
|
|
base = ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but .... */
|
|
else
|
|
#endif
|
|
base = state->Reg[base];
|
|
|
|
shamt = BITS (7, 11);
|
|
switch ((int) BITS (5, 6))
|
|
{
|
|
case LSL:
|
|
return (base << shamt);
|
|
case LSR:
|
|
if (shamt == 0)
|
|
return (0);
|
|
else
|
|
return (base >> shamt);
|
|
case ASR:
|
|
if (shamt == 0)
|
|
return ((ARMword) ((long int) base >> 31L));
|
|
else
|
|
return ((ARMword) ((long int) base >> (int) shamt));
|
|
case ROR:
|
|
if (shamt == 0) /* its an RRX */
|
|
return ((base >> 1) | (CFLAG << 31));
|
|
else
|
|
return ((base << (32 - shamt)) | (base >> shamt));
|
|
}
|
|
return (0); /* just to shut up lint */
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine evaluates the ARM7T halfword and signed transfer RHS's. *
|
|
\***************************************************************************/
|
|
|
|
static ARMword
|
|
GetLS7RHS (ARMul_State * state, ARMword instr)
|
|
{
|
|
if (BIT (22) == 0)
|
|
{ /* register */
|
|
#ifndef MODE32
|
|
if (RHSReg == 15)
|
|
return ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but ... */
|
|
#endif
|
|
return state->Reg[RHSReg];
|
|
}
|
|
|
|
/* else immediate */
|
|
return BITS (0, 3) | (BITS (8, 11) << 4);
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of loading a word for a LDR instruction. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
LoadWord (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
ARMword dest;
|
|
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
#endif
|
|
dest = ARMul_LoadWordN (state, address);
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
if (address & 3)
|
|
dest = ARMul_Align (state, address, dest);
|
|
WRITEDESTB (dest);
|
|
ARMul_Icycles (state, 1, 0L);
|
|
|
|
return (DESTReg != LHSReg);
|
|
}
|
|
|
|
#ifdef MODET
|
|
/***************************************************************************\
|
|
* This function does the work of loading a halfword. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
|
|
int signextend)
|
|
{
|
|
ARMword dest;
|
|
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
#endif
|
|
dest = ARMul_LoadHalfWord (state, address);
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
UNDEF_LSRBPC;
|
|
if (signextend)
|
|
{
|
|
if (dest & 1 << (16 - 1))
|
|
dest = (dest & ((1 << 16) - 1)) - (1 << 16);
|
|
}
|
|
WRITEDEST (dest);
|
|
ARMul_Icycles (state, 1, 0L);
|
|
return (DESTReg != LHSReg);
|
|
}
|
|
|
|
#endif /* MODET */
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of loading a byte for a LDRB instruction. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
|
|
{
|
|
ARMword dest;
|
|
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
#endif
|
|
dest = ARMul_LoadByte (state, address);
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
UNDEF_LSRBPC;
|
|
if (signextend)
|
|
{
|
|
if (dest & 1 << (8 - 1))
|
|
dest = (dest & ((1 << 8) - 1)) - (1 << 8);
|
|
}
|
|
WRITEDEST (dest);
|
|
ARMul_Icycles (state, 1, 0L);
|
|
return (DESTReg != LHSReg);
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of storing a word from a STR instruction. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
StoreWord (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
BUSUSEDINCPCN;
|
|
#ifndef MODE32
|
|
if (DESTReg == 15)
|
|
state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
|
|
#endif
|
|
#ifdef MODE32
|
|
ARMul_StoreWordN (state, address, DEST);
|
|
#else
|
|
if (VECTORACCESS (address) || ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
(void) ARMul_LoadWordN (state, address);
|
|
}
|
|
else
|
|
ARMul_StoreWordN (state, address, DEST);
|
|
#endif
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
return (TRUE);
|
|
}
|
|
|
|
#ifdef MODET
|
|
/***************************************************************************\
|
|
* This function does the work of storing a byte for a STRH instruction. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
BUSUSEDINCPCN;
|
|
|
|
#ifndef MODE32
|
|
if (DESTReg == 15)
|
|
state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
|
|
#endif
|
|
|
|
#ifdef MODE32
|
|
ARMul_StoreHalfWord (state, address, DEST);
|
|
#else
|
|
if (VECTORACCESS (address) || ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
(void) ARMul_LoadHalfWord (state, address);
|
|
}
|
|
else
|
|
ARMul_StoreHalfWord (state, address, DEST);
|
|
#endif
|
|
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
|
|
return (TRUE);
|
|
}
|
|
|
|
#endif /* MODET */
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of storing a byte for a STRB instruction. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
StoreByte (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
BUSUSEDINCPCN;
|
|
#ifndef MODE32
|
|
if (DESTReg == 15)
|
|
state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
|
|
#endif
|
|
#ifdef MODE32
|
|
ARMul_StoreByte (state, address, DEST);
|
|
#else
|
|
if (VECTORACCESS (address) || ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
(void) ARMul_LoadByte (state, address);
|
|
}
|
|
else
|
|
ARMul_StoreByte (state, address, DEST);
|
|
#endif
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
return (state->lateabtSig);
|
|
}
|
|
UNDEF_LSRBPC;
|
|
return (TRUE);
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of loading the registers listed in an LDM *
|
|
* instruction, when the S bit is clear. The code here is always increment *
|
|
* after, it's up to the caller to get the input address correct and to *
|
|
* handle base register modification. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
|
|
{
|
|
ARMword dest, temp;
|
|
|
|
UNDEF_LSMNoRegs;
|
|
UNDEF_LSMPCBase;
|
|
UNDEF_LSMBaseInListWb;
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
#endif
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
|
|
for (temp = 0; !BIT (temp); temp++); /* N cycle first */
|
|
dest = ARMul_LoadWordN (state, address);
|
|
if (!state->abortSig && !state->Aborted)
|
|
state->Reg[temp++] = dest;
|
|
else if (!state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
|
|
for (; temp < 16; temp++) /* S cycles from here on */
|
|
if (BIT (temp))
|
|
{ /* load this register */
|
|
address += 4;
|
|
dest = ARMul_LoadWordS (state, address);
|
|
if (!state->abortSig && !state->Aborted)
|
|
state->Reg[temp] = dest;
|
|
else if (!state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
}
|
|
|
|
if (BIT (15) && !state->Aborted)
|
|
{ /* PC is in the reg list */
|
|
WriteR15Branch(state, PC);
|
|
}
|
|
|
|
ARMul_Icycles (state, 1, 0L); /* to write back the final register */
|
|
|
|
if (state->Aborted)
|
|
{
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
TAKEABORT;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of loading the registers listed in an LDM *
|
|
* instruction, when the S bit is set. The code here is always increment *
|
|
* after, it's up to the caller to get the input address correct and to *
|
|
* handle base register modification. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
LoadSMult (ARMul_State * state, ARMword instr,
|
|
ARMword address, ARMword WBBase)
|
|
{
|
|
ARMword dest, temp;
|
|
|
|
UNDEF_LSMNoRegs;
|
|
UNDEF_LSMPCBase;
|
|
UNDEF_LSMBaseInListWb;
|
|
BUSUSEDINCPCS;
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
#endif
|
|
|
|
if (!BIT (15) && state->Bank != USERBANK)
|
|
{
|
|
(void) ARMul_SwitchMode (state, state->Mode, USER26MODE); /* temporary reg bank switch */
|
|
UNDEF_LSMUserBankWb;
|
|
}
|
|
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
|
|
for (temp = 0; !BIT (temp); temp++); /* N cycle first */
|
|
dest = ARMul_LoadWordN (state, address);
|
|
if (!state->abortSig)
|
|
state->Reg[temp++] = dest;
|
|
else if (!state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
|
|
for (; temp < 16; temp++) /* S cycles from here on */
|
|
if (BIT (temp))
|
|
{ /* load this register */
|
|
address += 4;
|
|
dest = ARMul_LoadWordS (state, address);
|
|
if (!state->abortSig && !state->Aborted)
|
|
state->Reg[temp] = dest;
|
|
else if (!state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
}
|
|
|
|
if (BIT (15) && !state->Aborted)
|
|
{ /* PC is in the reg list */
|
|
#ifdef MODE32
|
|
if (state->Mode != USER26MODE && state->Mode != USER32MODE)
|
|
{
|
|
state->Cpsr = GETSPSR (state->Bank);
|
|
ARMul_CPSRAltered (state);
|
|
}
|
|
WriteR15 (state, PC);
|
|
#else
|
|
if (state->Mode == USER26MODE || state->Mode == USER32MODE)
|
|
{ /* protect bits in user mode */
|
|
ASSIGNN ((state->Reg[15] & NBIT) != 0);
|
|
ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
|
|
ASSIGNC ((state->Reg[15] & CBIT) != 0);
|
|
ASSIGNV ((state->Reg[15] & VBIT) != 0);
|
|
}
|
|
else
|
|
ARMul_R15Altered (state);
|
|
FLUSHPIPE;
|
|
#endif
|
|
}
|
|
|
|
if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE)
|
|
(void) ARMul_SwitchMode (state, USER26MODE, state->Mode); /* restore the correct bank */
|
|
|
|
ARMul_Icycles (state, 1, 0L); /* to write back the final register */
|
|
|
|
if (state->Aborted)
|
|
{
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
TAKEABORT;
|
|
}
|
|
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of storing the registers listed in an STM *
|
|
* instruction, when the S bit is clear. The code here is always increment *
|
|
* after, it's up to the caller to get the input address correct and to *
|
|
* handle base register modification. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
StoreMult (ARMul_State * state, ARMword instr,
|
|
ARMword address, ARMword WBBase)
|
|
{
|
|
ARMword temp;
|
|
|
|
UNDEF_LSMNoRegs;
|
|
UNDEF_LSMPCBase;
|
|
UNDEF_LSMBaseInListWb;
|
|
if (!TFLAG)
|
|
{
|
|
BUSUSEDINCPCN; /* N-cycle, increment the PC and update the NextInstr state */
|
|
}
|
|
|
|
#ifndef MODE32
|
|
if (VECTORACCESS (address) || ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
if (BIT (15))
|
|
PATCHR15;
|
|
#endif
|
|
|
|
for (temp = 0; !BIT (temp); temp++); /* N cycle first */
|
|
#ifdef MODE32
|
|
ARMul_StoreWordN (state, address, state->Reg[temp++]);
|
|
#else
|
|
if (state->Aborted)
|
|
{
|
|
(void) ARMul_LoadWordN (state, address);
|
|
for (; temp < 16; temp++) /* Fake the Stores as Loads */
|
|
if (BIT (temp))
|
|
{ /* save this register */
|
|
address += 4;
|
|
(void) ARMul_LoadWordS (state, address);
|
|
}
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
TAKEABORT;
|
|
return;
|
|
}
|
|
else
|
|
ARMul_StoreWordN (state, address, state->Reg[temp++]);
|
|
#endif
|
|
if (state->abortSig && !state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
|
|
for (; temp < 16; temp++) /* S cycles from here on */
|
|
if (BIT (temp))
|
|
{ /* save this register */
|
|
address += 4;
|
|
ARMul_StoreWordS (state, address, state->Reg[temp]);
|
|
if (state->abortSig && !state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
}
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of storing the registers listed in an STM *
|
|
* instruction when the S bit is set. The code here is always increment *
|
|
* after, it's up to the caller to get the input address correct and to *
|
|
* handle base register modification. *
|
|
\***************************************************************************/
|
|
|
|
static void
|
|
StoreSMult (ARMul_State * state, ARMword instr,
|
|
ARMword address, ARMword WBBase)
|
|
{
|
|
ARMword temp;
|
|
|
|
UNDEF_LSMNoRegs;
|
|
UNDEF_LSMPCBase;
|
|
UNDEF_LSMBaseInListWb;
|
|
BUSUSEDINCPCN;
|
|
#ifndef MODE32
|
|
if (VECTORACCESS (address) || ADDREXCEPT (address))
|
|
{
|
|
INTERNALABORT (address);
|
|
}
|
|
if (BIT (15))
|
|
PATCHR15;
|
|
#endif
|
|
|
|
if (state->Bank != USERBANK)
|
|
{
|
|
(void) ARMul_SwitchMode (state, state->Mode, USER26MODE); /* Force User Bank */
|
|
UNDEF_LSMUserBankWb;
|
|
}
|
|
|
|
for (temp = 0; !BIT (temp); temp++); /* N cycle first */
|
|
#ifdef MODE32
|
|
ARMul_StoreWordN (state, address, state->Reg[temp++]);
|
|
#else
|
|
if (state->Aborted)
|
|
{
|
|
(void) ARMul_LoadWordN (state, address);
|
|
for (; temp < 16; temp++) /* Fake the Stores as Loads */
|
|
if (BIT (temp))
|
|
{ /* save this register */
|
|
address += 4;
|
|
(void) ARMul_LoadWordS (state, address);
|
|
}
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
TAKEABORT;
|
|
return;
|
|
}
|
|
else
|
|
ARMul_StoreWordN (state, address, state->Reg[temp++]);
|
|
#endif
|
|
if (state->abortSig && !state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
|
|
if (BIT (21) && LHSReg != 15)
|
|
LSBase = WBBase;
|
|
|
|
for (; temp < 16; temp++) /* S cycles from here on */
|
|
if (BIT (temp))
|
|
{ /* save this register */
|
|
address += 4;
|
|
ARMul_StoreWordS (state, address, state->Reg[temp]);
|
|
if (state->abortSig && !state->Aborted)
|
|
state->Aborted = ARMul_DataAbortV;
|
|
}
|
|
|
|
if (state->Mode != USER26MODE && state->Mode != USER32MODE)
|
|
(void) ARMul_SwitchMode (state, USER26MODE, state->Mode); /* restore the correct bank */
|
|
|
|
if (state->Aborted)
|
|
{
|
|
TAKEABORT;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of adding two 32bit values together, and *
|
|
* calculating if a carry has occurred. *
|
|
\***************************************************************************/
|
|
|
|
static ARMword
|
|
Add32 (ARMword a1, ARMword a2, int *carry)
|
|
{
|
|
ARMword result = (a1 + a2);
|
|
unsigned int uresult = (unsigned int) result;
|
|
unsigned int ua1 = (unsigned int) a1;
|
|
|
|
/* If (result == RdLo) and (state->Reg[nRdLo] == 0),
|
|
or (result > RdLo) then we have no carry: */
|
|
if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
|
|
*carry = 1;
|
|
else
|
|
*carry = 0;
|
|
|
|
return (result);
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of multiplying two 32bit values to give a *
|
|
* 64bit result. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
|
|
{
|
|
int nRdHi, nRdLo, nRs, nRm; /* operand register numbers */
|
|
ARMword RdHi = 0, RdLo = 0, Rm;
|
|
int scount; /* cycle count */
|
|
|
|
nRdHi = BITS (16, 19);
|
|
nRdLo = BITS (12, 15);
|
|
nRs = BITS (8, 11);
|
|
nRm = BITS (0, 3);
|
|
|
|
/* Needed to calculate the cycle count: */
|
|
Rm = state->Reg[nRm];
|
|
|
|
/* Check for illegal operand combinations first: */
|
|
if (nRdHi != 15
|
|
&& nRdLo != 15
|
|
&& nRs != 15
|
|
&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm)
|
|
{
|
|
ARMword lo, mid1, mid2, hi; /* intermediate results */
|
|
int carry;
|
|
ARMword Rs = state->Reg[nRs];
|
|
int sign = 0;
|
|
|
|
if (msigned)
|
|
{
|
|
/* Compute sign of result and adjust operands if necessary. */
|
|
|
|
sign = (Rm ^ Rs) & 0x80000000;
|
|
|
|
if (((signed long) Rm) < 0)
|
|
Rm = -Rm;
|
|
|
|
if (((signed long) Rs) < 0)
|
|
Rs = -Rs;
|
|
}
|
|
|
|
/* We can split the 32x32 into four 16x16 operations. This ensures
|
|
that we do not lose precision on 32bit only hosts: */
|
|
lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
|
|
mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
|
|
mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
|
|
hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
|
|
|
|
/* We now need to add all of these results together, taking care
|
|
to propogate the carries from the additions: */
|
|
RdLo = Add32 (lo, (mid1 << 16), &carry);
|
|
RdHi = carry;
|
|
RdLo = Add32 (RdLo, (mid2 << 16), &carry);
|
|
RdHi +=
|
|
(carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
|
|
|
|
if (sign)
|
|
{
|
|
/* Negate result if necessary. */
|
|
|
|
RdLo = ~RdLo;
|
|
RdHi = ~RdHi;
|
|
if (RdLo == 0xFFFFFFFF)
|
|
{
|
|
RdLo = 0;
|
|
RdHi += 1;
|
|
}
|
|
else
|
|
RdLo += 1;
|
|
}
|
|
|
|
state->Reg[nRdLo] = RdLo;
|
|
state->Reg[nRdHi] = RdHi;
|
|
} /* else undefined result */
|
|
else
|
|
fprintf (stderr, "MULTIPLY64 - INVALID ARGUMENTS\n");
|
|
|
|
if (scc)
|
|
{
|
|
/* Ensure that both RdHi and RdLo are used to compute Z, but
|
|
don't let RdLo's sign bit make it to N. */
|
|
ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
|
|
}
|
|
|
|
/* The cycle count depends on whether the instruction is a signed or
|
|
unsigned multiply, and what bits are clear in the multiplier: */
|
|
if (msigned && (Rm & ((unsigned) 1 << 31)))
|
|
Rm = ~Rm; /* invert the bits to make the check against zero */
|
|
|
|
if ((Rm & 0xFFFFFF00) == 0)
|
|
scount = 1;
|
|
else if ((Rm & 0xFFFF0000) == 0)
|
|
scount = 2;
|
|
else if ((Rm & 0xFF000000) == 0)
|
|
scount = 3;
|
|
else
|
|
scount = 4;
|
|
|
|
return 2 + scount;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of multiplying two 32bit values and adding *
|
|
* a 64bit value to give a 64bit result. *
|
|
\***************************************************************************/
|
|
|
|
static unsigned
|
|
MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
|
|
{
|
|
unsigned scount;
|
|
ARMword RdLo, RdHi;
|
|
int nRdHi, nRdLo;
|
|
int carry = 0;
|
|
|
|
nRdHi = BITS (16, 19);
|
|
nRdLo = BITS (12, 15);
|
|
|
|
RdHi = state->Reg[nRdHi];
|
|
RdLo = state->Reg[nRdLo];
|
|
|
|
scount = Multiply64 (state, instr, msigned, LDEFAULT);
|
|
|
|
RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
|
|
RdHi = (RdHi + state->Reg[nRdHi]) + carry;
|
|
|
|
state->Reg[nRdLo] = RdLo;
|
|
state->Reg[nRdHi] = RdHi;
|
|
|
|
if (scc)
|
|
{
|
|
/* Ensure that both RdHi and RdLo are used to compute Z, but
|
|
don't let RdLo's sign bit make it to N. */
|
|
ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
|
|
}
|
|
|
|
return scount + 1; /* extra cycle for addition */
|
|
}
|