250 lines
8.6 KiB
C
250 lines
8.6 KiB
C
/* CPU data header for sh.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef SH_CPU_H
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#define SH_CPU_H
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#define CGEN_ARCH sh
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/* Given symbol S, return sh_cgen_<S>. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define CGEN_SYM(s) sh##_cgen_##s
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#else
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#define CGEN_SYM(s) sh/**/_cgen_/**/s
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#endif
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/* Selected cpu families. */
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#define HAVE_CPU_SH64
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#define CGEN_INSN_LSB0_P 1
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/* Minimum size of any insn (in bytes). */
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#define CGEN_MIN_INSN_SIZE 2
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/* Maximum size of any insn (in bytes). */
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#define CGEN_MAX_INSN_SIZE 4
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#define CGEN_INT_INSN_P 1
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/* Maximum nymber of syntax bytes in an instruction. */
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#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of fields in an instruction. */
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
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/* Enums. */
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/* Enum declaration for . */
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typedef enum frc_names {
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H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
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, H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
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, H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
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, H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
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} FRC_NAMES;
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/* Enum declaration for . */
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typedef enum drc_names {
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H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
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, H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
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} DRC_NAMES;
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/* Enum declaration for . */
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typedef enum xf_names {
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H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
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, H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
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, H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
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, H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
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} XF_NAMES;
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/* Attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
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, MACH_SH4, MACH_SH5, MACH_MAX
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} MACH_ATTR;
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/* Enum declaration for instruction set selection. */
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typedef enum isa_attr {
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ISA_COMPACT, ISA_MEDIA, ISA_MAX
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} ISA_ATTR;
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/* Number of architecture variants. */
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#define MAX_ISAS ((int) ISA_MAX)
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#define MAX_MACHS ((int) MACH_MAX)
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/* Ifield attribute indices. */
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/* Enum declaration for cgen_ifld attrs. */
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typedef enum cgen_ifld_attr {
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CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
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, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
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, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
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} CGEN_IFLD_ATTR;
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/* Number of non-boolean elements in cgen_ifld_attr. */
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#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
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/* Enum declaration for sh ifield types. */
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typedef enum ifield_type {
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SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
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, SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
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, SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
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, SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
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, SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
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, SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
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, SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
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, SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
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, SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
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, SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
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, SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
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, SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
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, SH_F_DISP16, SH_F_MAX
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} IFIELD_TYPE;
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#define MAX_IFLD ((int) SH_F_MAX)
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/* Hardware attribute indices. */
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/* Enum declaration for cgen_hw attrs. */
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typedef enum cgen_hw_attr {
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CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
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, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
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} CGEN_HW_ATTR;
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/* Number of non-boolean elements in cgen_hw_attr. */
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#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
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/* Enum declaration for sh hardware types. */
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typedef enum cgen_hw_type {
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HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
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, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
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, HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
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, HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
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, HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
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, HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
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, HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
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, HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
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, HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
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, HW_MAX
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} CGEN_HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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/* Operand attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
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, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
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, CGEN_OPERAND_END_NBOOLS
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand_attr. */
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#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
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/* Enum declaration for sh operand types. */
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typedef enum cgen_operand_type {
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SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
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, SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
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, SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
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, SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
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, SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
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, SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
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, SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
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, SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
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, SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
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, SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
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, SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
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, SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
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, SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
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, SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
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, SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
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, SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
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, SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
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, SH_OPERAND_LIKELY, SH_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Number of operands types. */
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#define MAX_OPERANDS 72
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 8
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/* Insn attribute indices. */
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
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, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
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, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
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, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
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, CGEN_INSN_END_NBOOLS
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn_attr. */
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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/* cgen.h uses things we just defined. */
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#include "opcode/cgen.h"
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/* Attributes. */
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extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
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extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
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extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
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extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
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/* Hardware decls. */
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extern CGEN_KEYWORD sh_cgen_opval_h_gr;
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extern CGEN_KEYWORD sh_cgen_opval_h_grc;
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extern CGEN_KEYWORD sh_cgen_opval_h_cr;
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extern CGEN_KEYWORD sh_cgen_opval_h_fr;
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extern CGEN_KEYWORD sh_cgen_opval_h_fp;
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extern CGEN_KEYWORD sh_cgen_opval_h_fv;
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extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
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extern CGEN_KEYWORD sh_cgen_opval_h_dr;
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extern CGEN_KEYWORD sh_cgen_opval_h_tr;
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extern CGEN_KEYWORD sh_cgen_opval_frc_names;
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extern CGEN_KEYWORD sh_cgen_opval_drc_names;
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extern CGEN_KEYWORD sh_cgen_opval_xf_names;
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extern CGEN_KEYWORD sh_cgen_opval_frc_names;
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extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
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/* Ifield support. */
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extern const struct cgen_ifld sh_cgen_ifld_table[];
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#endif /* SH_CPU_H */
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