244 lines
5.9 KiB
C
244 lines
5.9 KiB
C
// -*- C -*-
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// Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
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// Copyright (C) 2002-2018 Free Software Foundation, Inc.
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// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
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// Corporation (SiByte).
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// Helper:
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//
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// Check that the SB-1 extension instruction can currently be used, and
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// signal a ReservedInstruction exception if not.
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//
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:function:::void:check_sbx:instruction_word insn
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*sb1:
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{
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if ((SR & status_SBX) == 0)
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SignalException(ReservedInstruction, insn);
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}
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// MDMX ASE Instructions
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// ---------------------
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//
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// The SB-1 implements the format OB subset of MDMX
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// and has three additions (pavg, pabsdiff, pabsdifc).
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// In addition, there are a couple of partial-decoding
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// issues for the read/write accumulator instructions.
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//
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// This code is structured so that mdmx.igen can be used by
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// selecting the allowed instructions either via model, or by
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// using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
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// exception if the instruction is not allowed.
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:function:::void:check_mdmx:instruction_word insn
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*sb1:
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{
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if (!COP_Usable(1))
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SignalExceptionCoProcessorUnusable(1);
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if ((SR & status_MX) == 0)
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SignalExceptionMDMX();
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check_u64 (SD_, insn);
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}
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:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
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*sb1:
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{
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switch (fmtsel & 0x03)
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{
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case 0x00: /* ob */
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case 0x02:
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return 1;
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case 0x01: /* qh */
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case 0x03: /* UNPREDICTABLE */
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SignalException (ReservedInstruction, insn);
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return 0;
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}
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return 0;
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}
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:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
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*sb1:
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{
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switch (fmtop & 0x01)
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{
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case 0x00: /* ob */
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return 1;
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case 0x01: /* qh */
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SignalException (ReservedInstruction, insn);
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return 0;
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}
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return 0;
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}
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011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
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"rach.?<X>.%s<FMTOP> v<VD>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
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"racl.?<X>.%s<FMTOP> v<VD>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
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"racm.?<X>.%s<FMTOP> v<VD>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
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"rac?<X1>.?<X2> v<VD>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
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"wach.?<X>.%s<FMTOP> v<VS>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
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"wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
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"wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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/* No op. */
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
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"pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_sbx (SD_, instruction_0);
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check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
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StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
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"pabsdifc.%<FMTSEL> v<VS>,v<VT>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_sbx (SD_, instruction_0);
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check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
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MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
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"pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_sbx (SD_, instruction_0);
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check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
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StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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// Paired-Single Extension Instructions
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// ------------------------------------
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//
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// The SB-1 implements several .PS format instructions that are
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// extensions to the MIPS64 architecture.
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010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS
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"div.%s<FMT> f<FD>, f<FS>, f<FT>"
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*sb1:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_sbx (SD_, instruction_0);
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StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
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}
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010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS
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"recip.%s<FMT> f<FD>, f<FS>"
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*sb1:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_sbx (SD_, instruction_0);
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StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
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}
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010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS
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"rsqrt.%s<FMT> f<FD>, f<FS>"
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*sb1:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_sbx (SD_, instruction_0);
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StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
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}
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010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS
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"sqrt.%s<FMT> f<FD>, f<FS>"
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*sb1:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_sbx (SD_, instruction_0);
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StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
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}
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